2016 DI2CM IP Core I2C Bus Interface - Master v. 4.01 COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. APPLICATIONS ● ● ● ● ● ● Embedded microprocessor boards Consumer and professional audio/video Home and automotive radio Low-power applications Communication systems Cost-effective reliable automotive systems DELIVERABLES ♦ Source code: ● ● ● ♦ VHDL & VERILOG test bench environment ● ● ● IP CORE OVERVIEW 2 The I C is a two-wire, bi-directional serial bus, which provides simple and efficient method of data transmission over short distance, between many devices. The DI2CM core provides an interface between a microprocessor / microcontroller and 2 an I C bus. It can work as a master transmitter or a master receiver - depending on a working mode determined by the microprocessor / microcontroller. The DI2CM core incorporates all features re2 quired by the latest I C specification, including clock synchronization, arbitration, multi-master systems and a High-speed transmission mode. Built-in timer allows operation from a wide range of clk frequencies. KEY FEATURES ● ● 2 Conforms to v.4.0 of the I C specification Master operation ○ ○ ● Support for all transmission speeds ○ ○ ○ ○ ● ● ● ● ● ● ● ● ● ● ● Master transmitter Master receiver Standard (up to 100 kb/s) Fast (up to 400 kb/s) Fast Plus (up to 1 Mb/s) High Speed (up to 3,4 Mb/s) Arbitration and clock synchronization Support for multi-master systems Support for both 7-bit and 10-bit addressing for2 mats on the I C bus Interrupt generation Built-in 8-bit timer for data transfers speed adjusting Host side interface dedicated for microprocessors / microcontrollers User-defined timing (data setup, start setup, start hold, etc.) Fully synthesizable Static synchronous design with positive edge clocking and synchronous reset No internal tri-states Scan test ready VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF ♦ Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation ● ● ● ♦ ♦ ♦ Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support ● ● IP Core implementation support 3 months maintenance ● Delivery of the IP Core and documentation updates, minor and major versions changes Phone & email support ● PINS DESCRIPTION PIN clk rst address(1:0) cs we rd scli sdai datai(7:0) datao(7:0) sclo sclhs sdao irq TYPE input input input input input input input input input output output output output output DESCRIPTION Global clock Global reset Processor address lines Chip select Processor write strobe Processor read strobe I2C bus clock line (input) I2C bus data line (input) Processor data bus (input) Processor data bus (output) I2C bus clock line (output) High-speed clock line (output) I2C bus data line (output) Processor interrupt line SYMBOL datai(7:0) datao(7:0) rd we address(1:0) scli sdai cs rst clk sclhs sclo sdao irq 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. IMPLEMENTATION Figures below show typical DI2CM implementations in system with Standard, Fast, Fast Plus and High-speed devices. VDD RP RP SDA SCL RS RS RS RS sdai sda sdao open drain Slave device DI2CM scli scl sclo open drain sclhs DI2CM implementation in I2C-bus system with Standard, Fast and Fast Plus devices only VDD RP RP SDA SCL RS RS sdai RS RS sda sdao open drain Slave device DI2CM scli scl sclo open drain current-source pull-up sclhs VDD DI2CM implementation in I2C-bus system with High-speed devices 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. BLOCK DIAGRAM The figure below shows the DI2CM IP Core block diagram. Slave Address address(1:0) Input Filter sdai Output Register sdao datai(7:0) datao(7:0) Shift Register CPU Interface Send Data cs we rd Receive Data irq Control Register Arbitration Logic Control Logic Status Register Clock Synchronization Timer Clock Generator rst clk Input Filter scli Output Register sclo Output Register sclhs DI2CX CORES OVERVIEW 2 - - Spike filtering User defined timing High-speed mode Fast Plus mode Fast mode - Standard mode - 10-bit addressing - - 7-bit addressing Arbitration Passive device interface CPU interface Slave operation - - Clock synchronization 3.0 3.0 3.0 3.0 Interrupt generation DI2CM DI2CS DI2CSB DI2CMS Master operation Design I2C specification version The main features of all Digital Core Design I C compliant cores have been summarized in the table below. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. - I2C Cores summary table 3 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. LICENSING PERFORMANCE Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. The following table gives a survey about the Core area and performance in ASIC devices (all key features included): Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code called HDL Source code Technology 0.25 typical 0.25 typical Optimization Gates area 1300 speed 2200 Core performance in ASIC device Fmax 160 MHz 600 MHz CONTACT Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: [email protected] 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales FPGA EDIF/NGO/NGD/QXP/VQM called Netlist UNITS SUMMARY CPU Interface – Performs the interface functions between DI2CM internal blocks and microprocessor. Allows easy connection between the core and a microprocessor/microcontroller system. Control Logic – Manages execution of all commands sent via interface. Synchronizes internal data flow. Shift Register – Controls SDA line, performs data and address shifts, during the data transmission and reception. Control Register – Contains five control bits, used 2 for performing all types of I C Bus transmissions. Status Register – Contains seven status bits that 2 indicate state of the I C Bus and the DI2CM core. Clock Generator of the serial clock. – Performs generation Input Filter – Performs spike filtering. Clock Synchronization – Performs clock synchronization. Arbitration Logic – Performs arbitration during operations in multi-master systems. Timer – Allows operation from a wide range of the input frequencies. It is programmed by the user before transmission and can be reprogrammed to change the SCL frequency. 4 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.