2016 DI2CMS IP Core I2C Bus Interface - Master/Slave v. 4.04 ○ ○ ○ COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. Slave transmitter Slave receiver Support for all transmission speeds ○ Allows operation from a wide range of input clock frequencies User-defined data setup time ○ ● ● ● ● ● ● IP CORE OVERVIEW Simple interface allows easy connection to microprocessor/microcontroller devices Interrupt generation Fully synthesizable Static synchronous design with positive edge clocking and synchronous reset No internal tri-states Scan test ready DELIVERABLES 2 The I C is a two-wire, bi-directional serial bus, which provides simple and efficient method of data transmission over short distance, between many devices. The DI2CMS core provides an interface between a microprocessor / microcontroller 2 and an I C bus. It can work as a master or as a slave transmitter/receiver, depending on a working mode, determined by the microprocessor/microcontroller. The DI2CMS core incorporates 2 all features required by the latest I C specification, including clock synchronization, arbitration, multimaster systems and High-speed transmission mode. The DI2CMS supports all transmission speed modes. A built-in timer allows operation from a wide range of clk frequencies. The DI2CMS is a technology independent VHDL or VERILOG design, which can be implemented in a variety of process technologies and may be fully customized, according to customer’s needs. The DI2CMS is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow. KEY FEATURES ● ● 2 Conforms to v.4.0 of the I C specification Master mode ○ ○ ○ ○ ○ ○ ○ ○ ○ ● Master operation Master transmitter Master receiver Support for all transmission speeds Standard (up to 100 kb/s) Fast (up to 400 kb/s) Fast Plus (up to 1 Mb/s) High Speed (up to 3,4 Mb/s) Arbitration and clock synchronization Support for multi-master systems Support for both 7-bit and 10-bit addressing formats on the I2C bus Build-in 8-bit timer for data transfers speed adjusting User-defined timing (data setup, start setup, start hold, etc.) Standard (up to 100 kb/s) Fast (up to 400 kb/s) Fast Plus (up to 1 Mb/s) High Speed (up to 3,4 Mb/s) ♦ Source code: ● ● ● ♦ VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF VHDL & VERILOG test bench environment ● ● ● ♦ Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation ● ● ● ♦ ♦ ♦ Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support ● ● IP Core implementation support 3 months maintenance ● ● Delivery of the IP Core and documentation updates, minor and major versions changes Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code FPGA EDIF/NGO/NGD/QXP/VQM (Netlist) Slave mode ○ Slave operation 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. IMPLEMENTATION Figures below show typical DI2CMS implementations in a system with Standard, Fast, Fast Plus and High-speed devices. VDD RP RP SDA SCL RS RS RS RS sdai sda sdao open drain Master/Slave device DI2CMS scli scl sclo open drain sclhs DI2CMS implementation in I2C-bus system with Standard, Fast and Fast Plus devices only. VDD RP RP SDA SCL RS RS sdai RS RS sda sdao open drain Master/Slave device DI2CMS scli scl sclo open drain current-source pull-up sclhs VDD DI2CMS implementation in I2C-bus system with High-speed devices 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. BLOCK DIAGRAM Slave Address address(2:0) datai(7:0) datao(7:0) Shift Register CPU Interface Send Data cs we rd Input Filter sdai Output Register sdao Receive Data irq Control Register Arbitration Logic Control Logic Status Register Clock Control Logic Timer rst clk Input Filter scli Output Register sclo Output Register sclhs DI2CX CORES OVERVIEW 2 - - Spike filtering User defined timing High-speed mode Fast Plus mode Fast mode - Standard mode - 10-bit addressing - - 7-bit addressing Arbitration - Clock synchronization Passive device interface CPU interface - Slave operation 3.0 3.0 3.0 3.0 Interrupt generation DI2CM DI2CS DI2CSB DI2CMS Master operation Design I2C specification version The main features of each Digital Core Design I C compliant cores have been summarized in the table below. It gives a brief member characteristic helping you to select the most suitable IP Core for your application. - I2C Cores summary table APPLICATIONS ● ● ● ● ● ● Embedded microprocessor boards Consumer and professional audio/video Home and automotive radio Low-power applications Communication systems Cost-effective reliable automotive systems PINS DESCRIPTION PIN clk rst address(1:0) cs we rd scli sdai datai(7:0) datao(7:0) sclo sclhs sdao irq TYPE input input input input input input input input input output output output output output DESCRIPTION Global clock Global reset Processor address lines Chip select Processor write strobe Processor read strobe I2C bus clock line (input) I2C bus data line (input) Processor data bus (input) Processor data bus (output) I2C bus clock line (output) High-speed clock line (output) I2C bus data line (output) Processor interrupt line 3 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. Input Filter – Performs spike filtering. SYMBOL datai(7:0) datao(7:0) rd we address(2:0) scli sdai Clock Control Logic – Performs clock synchronization, clock generation in master mode and clock stretching in slave mode. Arbitration Logic – Performs arbitration during operations in multi-master systems. sclhs sclo sdao Timer – Allows operation from a wide range of the input frequencies. It is programmed by the user before transmission and can be reprogrammed to change the SCL frequency. PERFORMANCE cs rst clk irq UNITS SUMMARY CPU Interface – Performs the interface functions between DI2CMS internal blocks and microprocessor. Allows easy connection between the core and a microprocessor/microcontroller system. Control Logic – Manages execution of all commands sent via interface. Synchronizes internal data flow. Shift Register – Controls SDA line, performs data and address shifts during the data transmission and reception. Control Register – Contains five control bits, used for performing all types of I2C Bus transmissions. Status Register – Contains seven status bits that indicate state of the I2C Bus and the DI2CMS core. Input Filter – Performs spike filtering. Clock Control Logic – Performs clock synchronization, clock generation in master mode and clock stretching in slave mode. Arbitration Logic – Performs arbitration during operations in multi-master systems. Timer – Allows operation from a wide range of the input frequencies. It is programmed by the user before transmission and can be reprogrammed to change the SCL frequency. The following table gives a survey about the Core area and performance in XILINX® devices after Place & Route (all key features included): Speed LUT Slice grade Spartan-3 xc3s50 -5 424 286 Spartan-3E xc3s100e -5 417 285 Spartan-6 xc6slx4 -3 289 119 Virtex-4 xc4vfx12 -12 464 290 Virtex-5 xc5vlx20t -2 313 173 Virtex-6 xc6vlx75t -3 290 93 Virtex-7 xc7vx330t -3 324 109 Kintex-7 xc7k70t -3 321 129 Artix-7 xc7a100t -3 292 119 Virtex UltraScale xcvu065 -3 376 57 Zynq-7000 xc7z010 -3 374 112 Core performance in XILINX® devices Family Device Fmax 161 MHz 166 MHz 269 MHz 310 MHz 382 MHz 375 MHz 492 MHz 511 MHz 329 MHz 500 MHz 330 MHz CONTACT Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: [email protected] 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales CPU Interface – Performs the interface functions between DI2CMS internal blocks and microprocessor. Allows easy connection between the core and a microprocessor/ microcontroller system. Control Logic – Manages execution of all commands sent via interface. Synchronizes internal data flow. Shift Register – Controls SDA line, performs data and address shifts during the data transmission and reception. Control Register – Contains five control bits, used for performing all types of I2C Bus transmissions. Status Register – Contains seven status bits that indicate state of the I2C Bus and the DI2CMS core. 4 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.