High Voltage Latch-Up Proof, Triple/Quad SPDT Switches ADG5433/ADG5434 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS Latch-up proof Human body model (HBM) ESD rating: 8 kV Low on resistance (13.5 Ω) ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V VSS to VDD analog signal range ADG5433 S1A D1 S1B S3B D3 S2B S3A D2 S2A APPLICATIONS LOGIC Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems 09207-001 IN1 IN2 IN3 EN SWITCHES SHOWN FOR A LOGIC 1 INPUT. Figure 1. ADG5433 TSSOP and LFCSP_WQ ADG5434 S4A S1A D4 D1 S1B S4B S2B S3B D3 D2 S3A S2A LOGIC 09207-002 IN1 IN2 IN3 IN4 SWITCHES SHOWN FOR A LOGIC 1 INPUT. Figure 2. ADG5434 TSSOP and LFCSP_WQ GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG5433 and ADG5434 are monolithic industrial CMOS analog switches comprising three independently selectable single-pole, double-throw (SPDT) switches and four independently selectable SPDT switches, respectively. 1. All channels exhibit break-before-make switching action that prevents momentary shorting when switching channels. An EN input on the ADG5433 (LFCSP and TSSOP packages) is used to enable or disable the device. When disabled, all channels are switched off. The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications, where low distortion is critical. Rev. C 2. 3. 4. 5. 6. Trench isolation guards against latch-up. A dielectric trench separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions. Low RON. Dual-supply operation. For applications where the analog signal is bipolar, the ADG5433/ADG5434 can be operated from dual supplies up to ±22 V. Single-supply operation. For applications where the analog signal is unipolar, the ADG5433/ADG5434 can be operated from a single-rail power supply up to 40 V. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. 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Technical Support www.analog.com ADG5433/ADG5434 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Continuous Current per Channel, Sx or Dx ..............................8 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................9 Functional Block Diagrams ............................................................. 1 ESD Caution...................................................................................9 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ......................... 10 Product Highlights ........................................................................... 1 Typical Performance Characteristics ........................................... 12 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 16 Specifications..................................................................................... 3 Terminology .................................................................................... 18 ±15 V Dual Supply ....................................................................... 3 Trench Isolation .............................................................................. 19 ±20 V Dual Supply ....................................................................... 4 Applications Information .............................................................. 20 12 V Single Supply ........................................................................ 5 Outline Dimensions ....................................................................... 21 36 V Single Supply ........................................................................ 6 Ordering Guide .......................................................................... 22 REVISION HISTORY 6/13—Rev. B to Rev. C Changes to Table 6 ............................................................................ 8 Added Figure 6; Renumbered Sequentially ................................ 10 Changes to Table 10 ........................................................................ 10 Changes to Figure 9 ........................................................................ 12 Changes to Figure 26 and Figure 27............................................. 16 Deleted Figure 29 ............................................................................ 16 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 5/12—Rev. A to Rev. B Removed Automotive Information (Throughout)....................... 1 Changes to Ordering Guide .......................................................... 22 Deleted Automotive Products Section ......................................... 22 6/11—Rev. 0 to Rev. A Change to Features Section ............................................................. 1 Change to ISS Parameter, Table 2 ..................................................... 5 Changes to Figure 4 ........................................................................ 10 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 Added Automotive Products Section .......................................... 22 10/10—Revision 0: Initial Version Rev. C | Page 2 of 24 Data Sheet ADG5433/ADG5434 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) 25°C 13.5 15 0.3 0.8 1.8 2.2 ±0.05 ±0.25 ±0.1 ±0.4 ±0.1 ±0.4 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments VDD to VSS V Ω typ Ω max Ω typ VS = ±10 V, IS = −10 mA; see Figure 27 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −10 mA 18 22 1.3 1.4 2.6 3 Ω max Ω typ Ω max ±1 ±7 ±4 ±30 ±4 ±30 nA typ nA max nA typ nA max nA typ nA max 2.0 V min 0.8 V max µA typ µA max pF typ VS = ±10 V, IS = −10 mA VDD = +16.5 V, VSS = −16.5 V VS = ±10 V, VD = 10 V VS = ±10 V, VD = 10 V VS = VD = ±10 V; see Figure 26 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 6 Break-Before-Make Time Delay, tD 157 207 160 196 91 106 45 Charge Injection, QINJ 130 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −60 dB typ Channel-to-Channel Crosstalk −60 dB typ Total Harmonic Distortion + Noise 0.01 % typ −3 dB Bandwidth Insertion Loss 145 −0.9 MHz typ dB typ CS (Off ) CD (Off ) CD (On), CS (On) 14 24 53 pF typ pF typ pF typ tON (EN) tOFF (EN) 245 272 241 274 138 140 21 Rev. C | Page 3 of 24 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 10 V RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V; see Figure 33 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 35 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28 RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz ADG5433/ADG5434 Parameter POWER REQUIREMENTS IDD ISS Data Sheet 25°C −40°C to +85°C 45 55 0.001 70 1 ±9/±22 VDD/VSS 1 −40°C to +125°C Unit µA typ µA max µA typ µA max V min/V max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C Unit VDD to VSS V Ω typ 12.5 14 0.3 17 21 Ω max Ω typ 0.8 2.3 2.7 1.3 1.4 3.1 3.5 Ω max Ω typ Ω max ±0.05 ±0.25 ±0.1 ±0.4 ±0.1 ±0.4 ±1 ±7 ±4 ±30 ±4 ±30 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 6 nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ Break-Before-Make Time Delay, tD 150 199 152 186 90 104 36 Charge Injection, QINJ 176 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −60 dB typ Channel-to-Channel Crosstalk −60 dB typ Total Harmonic Distortion + Noise 0.012 % typ −3 dB Bandwidth 140 MHz typ tON (EN) tOFF (EN) 230 253 223 253 118 130 17 Rev. C | Page 4 of 24 Test Conditions/Comments VS = ±15 V, IS = −10 mA; see Figure 27 VDD = +18 V, VSS = −18 V VS = ±15 V, IS = −10 mA VS = ±15 V, IS = −10 mA VDD = +22 V, VSS = −22 V VS = ±15 V, VD = 15 V VS = ±15 V, VD = 15 V VS = VD = ±15 V; see Figure 26 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 10 V RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V; see Figure 33 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 35 RL = 50 Ω, CL = 5 pF, f = 1MHz; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 31 Data Sheet ADG5433/ADG5434 Parameter Insertion Loss 25°C −0.8 CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 15 23 52 ISS −40°C to +85°C Unit dB typ pF typ pF typ pF typ 50 70 0.001 Test Conditions/Comments RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = −22 V Digital inputs = 0 V or VDD 1 ±9/±22 µA typ µA max µA typ µA max V min/V max GND = 0 V −40°C to +125°C Unit Test Conditions/Comments 0 V to VDD V Ω typ 110 VDD/VSS 1 −40°C to +125°C Digital inputs = 0 V or VDD Guaranteed by design; not subject to production test. 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C 26 30 0.3 36 42 Ω max Ω typ 1 5.5 6.5 1.5 1.6 8 12 Ω max Ω typ Ω max ±0.05 ±0.25 ±0.1 ±0.4 ±0.1 ±0.4 ±1 ±7 ±4 ±30 ±4 ±30 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 6 nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ Break-Before-Make Time Delay, tD 220 290 228 289 90 115 106 Charge Injection, QINJ 60 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −60 dB typ tON (EN) tOFF (EN) 357 400 370 426 131 151 54 Rev. C | Page 5 of 24 VS = 0 V to 10 V, IS = −10 mA; see Figure 27 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −10 mA VS = 0 V to 10 V, IS = −10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V VS = 1 V/10 V, VD = 10 V/1 V VS = VD = 1 V/10 V; see Figure 26 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 8 V RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 33 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 35 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 ADG5433/ADG5434 Parameter Channel-to-Channel Crosstalk Data Sheet 25°C −60 −40°C to +85°C Unit dB typ Total Harmonic Distortion + Noise 0.1 % typ −3 dB Bandwidth 150 MHz typ Insertion Loss −0.8 dB typ 18 28 54 pF typ pF typ pF typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 40 50 VDD 1 −40°C to +125°C Test Conditions/Comments RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD 65 9/40 µA typ µA max V min/V max GND = 0 V, VSS = 0 V −40°C to +125°C Unit Test Conditions/Comments 0 V to VDD V Ω typ Guaranteed by design; not subject to production test. 36 V SINGLE SUPPLY VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C 14.5 16 0.3 19 23 Ω max Ω typ 0.8 3.5 4.3 1.3 1.4 5.5 6.5 Ω max Ω typ Ω max ±0.05 ±0.25 ±0.1 ±0.4 ±0.1 ±0.4 ±1 ±7 ±4 ±30 ±4 ±30 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD 6 180 262 176 216 98 123 50 274 289 238 268 127 129 21 Rev. C | Page 6 of 24 nA typ nA max nA typ nA max nA typ nA max VS = 0 V to 30 V, IS = −10 mA; see Figure 27 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = −10 mA VS = 0 V to 30 V, IS = −10 mA VDD = 39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V VS = 1 V/30 V, VD = 30 V/1 V VS = VD = 1 V/30 V; see Figure 26 V min V max µA typ µA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max ns typ ns max ns typ ns min RL = 300 Ω, CL = 35 pF VS = 18 V RL = 300 Ω, CL = 35 pF VS = 18 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS = 18 V; see Figure 34 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 18 V; see Figure 33 Data Sheet Parameter Charge Injection, QINJ ADG5433/ADG5434 25°C 150 −40°C to +85°C −40°C to +125°C Unit pC typ Off Isolation −60 dB typ Channel-to-Channel Crosstalk −60 dB typ Total Harmonic Distortion + Noise 0.4 % typ −3 dB Bandwidth Insertion Loss 135 −1 MHz typ dB typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 18 28 46 pF typ pF typ pF typ VDD 1 80 100 130 9/40 Guaranteed by design; not subject to production test. Rev. C | Page 7 of 24 µA typ µA max V min/V max Test Conditions/Comments VS = 18 V, RS = 0 Ω, CL = 1 nF; see Figure 35 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 1 kΩ, 18 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V ADG5433/ADG5434 Data Sheet CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Table 5. ADG5433 Parameter CONTINUOUS CURRENT, Sx OR Dx VDD = +15 V, VSS = −15 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = +20 V, VSS = −20 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 36 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) 25°C 85°C 125°C Unit 80 147 58 103 36 70 mA maximum mA maximum 85 156 63 109 39 74 mA maximum mA maximum 63 116 45 84 28 53 mA maximum mA maximum 83 151 60 107 37 72 mA maximum mA maximum 25°C 85°C 125°C Unit 70 117 51 76 31 49 mA maximum mA maximum 74 123 54 79 33 50 mA maximum mA maximum 54 94 39 64 23 44 mA maximum mA maximum 73 120 53 78 32 50 mA maximum mA maximum Table 6. ADG5434 Parameter CONTINUOUS CURRENT, Sx OR Dx VDD = +15 V, VSS = −15 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = +20 V, VSS = −20 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 36 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) Rev. C | Page 8 of 24 Data Sheet ADG5433/ADG5434 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pins ADG5433 ADG5434 Continuous Current, Sx or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 20-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free Rating 48 V −0.3 V to +48 V +0.3 V to −48 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION 280 mA (pulsed at 1 ms, 10% duty cycle maximum) 240 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% −40°C to +125°C −65°C to +150°C 150°C 112.6°C/W 143°C/W 30.4°C/W 260(+0/−5)°C 1 Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5 and Table 6. Rev. C | Page 9 of 24 ADG5433/ADG5434 Data Sheet 14 GND 13 IN1 16 S1A 15 VDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 16 GND S1A 2 15 IN1 D1 1 D1 3 14 EN S1B 2 ADG5433 11 VSS VSS S2B 3 TOP VIEW (Not to Scale) 10 S3B D3 10 S3A IN2 8 9 IN3 NOTES 1. EXPOSED PAD IS TIED TO SUBSTRATE, VSS. Figure 3. ADG5433 TSSOP Pin Configuration 09207-005 D2 S2A 7 9 D3 IN3 7 S3B 11 D2 4 S3A 8 12 6 13 IN2 6 TOP VIEW (Not to Scale) S2A 5 S2B 5 09207-003 S1B 4 ADG5433 12 EN Figure 4. ADG5433 LFCSP_WQ Pin Configuration Table 8. ADG5433 Pin Function Descriptions TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 Pin No. LFCSP_WQ 15 16 1 2 3 4 5 6 7 8 9 10 11 Mnemonic VDD S1A D1 S1B S2B D2 S2A IN2 IN3 S3A D3 S3B VSS 14 12 EN 15 16 13 14 EP IN1 GND Exposed Pad Description Most Positive Power Supply Potential. Source Terminal 1A. This pin can be an input or an output. Drain Terminal 1. This pin can be an input or an output. Source Terminal 1B. This pin can be an input or an output. Source Terminal 2B. This pin can be an input or an output. Drain Terminal 2. This pin can be an input or an output. Source Terminal 2A. This pin can be an input or an output. Logic Control Input 2. Logic Control Input 3. Source Terminal 3A. This pin can be an input or an output. Drain Terminal 3. This pin can be an input or an output. Source Terminal 3B. This pin can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx logic inputs determine the on switches. Logic Control Input 1. Ground (0 V) Reference. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table 9. ADG5433 Truth Table EN 1 0 0 INx X 0 1 SxA Off Off On SxB Off On Off Rev. C | Page 10 of 24 ADG5433/ADG5434 20 19 18 17 16 S1A IN1 EN IN4 S4A Data Sheet IN1 1 20 IN4 18 D4 S1B 4 17 S4B VSS 5 ADG5434 16 VDD GND 6 TOP VIEW (Not to Scale) 15 NC S2B 7 14 S3B D2 8 13 D3 S2A 9 12 S3A IN2 10 11 IN3 NC = NO CONNECT ADG5434 TOP VIEW (Not to Scale) 15 14 13 12 11 D4 S4B VDD S3B D3 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS. 09207-006 D1 3 D1 1 S1B 2 VSS 3 GND 4 S2B 5 6 7 8 9 10 S4A D2 S2A IN2 IN3 S3A 19 09207-004 S1A 2 Figure 6. ADG5434 LFCSP_WQ Pin Configuration Figure 5. ADG5434 TSSOP Pin Configuration Table 10. ADG5434 Pin Function Descriptions Pin No. TSSOP LFCSP_WQ 1 19 2 20 3 1 4 2 5 3 Mnemonic IN1 S1A D1 S1B VSS 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 N/A 4 5 6 7 8 9 10 11 12 N/A 13 14 15 16 17 18 GND S2B D2 S2A IN2 IN3 S3A D3 S3B NC VDD S4B D4 S4A IN4 EN N/A EP Exposed Pad Description Logic Control Input 1. Source Terminal 1A. This pin can be an input or an output. Drain Terminal 1. This pin can be an input or an output. Source Terminal 1B. This pin can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Ground (0 V) Reference. Source Terminal 2B. This pin can be an input or an output. Drain Terminal 2. This pin can be an input or an output. Source Terminal 2A. This pin can be an input or an output. Logic Control Input 2. Logic Control Input 3. Source Terminal 3A. This pin can be an input or an output. Drain Terminal 3. This pin can be an input or an output. Source Terminal 3B. This pin can be an input or an output. No Connect. Most Positive Power Supply Potential. Source Terminal 4B. This pin can be an input or an output. Drain Terminal 4. This pin can be an input or an output. Source Terminal 4A. This pin can be an input or an output. Logic Control Input 4. Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx logic inputs determine the on switches. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table 11. ADG5434 Truth Table INx 0 1 SxA Off On SxB On Off Rev. C | Page 11 of 24 ADG5433/ADG5434 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 25 16 TA = 25°C TA = 25°C VDD = +10V VSS = –10V VDD = +9V VSS = –9V 14 12 VDD = +11V VSS = –11V ON RESISTANCE (Ω) ON RESISTANCE (Ω) 20 15 10 VDD = +13.5V VSS = –13.5V VDD = +15V VSS = –15V VDD = +16.5V VSS = –16.5V 10 VDD = 32.4V VSS = 0V 8 VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 6 4 5 –14 –6 –10 2 –2 6 10 14 18 VS, VD (V) 0 09207-047 0 –18 0 5 10 15 25 20 30 35 40 45 VS, VD (V) Figure 7. On Resistance as a Function of VS, VD (Dual Supply) 09207-046 2 Figure 10. On Resistance as a Function of VS, VD (Single Supply) 25 16 TA = 25°C 14 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 20 VDD = +18V VSS = –18V 12 10 8 VDD = +22V VSS = –22V VDD = +20V VSS = –20V 6 TA = +125°C 15 TA = +85°C TA = +25°C 10 TA = –40°C 4 –15 –20 –10 –5 0 5 10 15 25 20 VS, VD (V) Figure 8. On Resistance as a Function of VS, VD (Dual Supply) 35 VDD = 10V VSS = 0V 5 10 15 Figure 11. On Resistance as a Function of VS (VD) for Different Temperatures, ±15 V Dual Supply VDD = 10.8V VSS = 0V VDD = 9V VSS = 0V 0 –5 VS, VD (V) 25 TA = 25°C 30 VDD = +20V VSS = –20V 20 ON RESISTANCE (Ω) 25 20 15 VDD = 13.2V VSS = 0V VDD = 12V VSS = 0V VDD = 11V VSS = 0V TA = +125°C 15 TA = +85°C TA = +25°C 10 TA = –40°C 10 5 0 0 2 4 6 8 VS, VD (V) 10 12 14 Figure 9. On Resistance as a Function of VS, VD (Single Supply) 0 –20 –15 –10 –5 0 VS, VD (V) 5 10 15 20 09207-045 5 09207-044 ON RESISTANCE (Ω) VDD = +15V VSS = –15V 0 –10 –15 09207-048 0 –25 09207-049 5 2 Figure 12. On Resistance as a Function of VS (VD) for Different Temperatures, ±20 V Dual Supply Rev. C | Page 12 of 24 Data Sheet ADG5433/ADG5434 40 0.4 VDD = +20V VSS = –20V VBIAS = +15V/–15V 35 ID, IS (ON) + + IS (OFF) + – 0.2 ON RESISTANCE (Ω) LEAKAGE CURRENT (nA) TA = +125°C 30 TA = +85°C 25 20 TA = +25°C 15 TA = –40°C 10 ID (OFF) – + 0 ID, IS (ON) – – –0.2 IS (OFF) – + –0.4 ID (OFF) + – 5 4 2 6 8 10 12 VS, VD (V) –0.6 50 75 100 125 Figure 16. Leakage Currents as a Function of Temperature, ±20 V Dual Supply 0.4 VDD = 36V VSS = 0V VDD = 12V VSS = 0V VBIAS = 1V/10V 0.3 LEAKAGE CURRENT (nA) 20 ON RESISTANCE (Ω) 25 TEMPERATURE (°C) Figure 13. On Resistance as a Function of VS (VD) for Different Temperatures, 12 V Single Supply 25 0 09207-042 0 09207-050 0 VDD = 12V VSS = 0V TA = +125°C 15 TA = +85°C TA = +25°C 10 TA = –40°C ID, IS (ON) + + 0.2 ID, IS (ON) – – IS (OFF) + – 0.1 0 ID (OFF) – + 5 –0.1 IS (OFF) – + 5 10 15 20 25 30 35 40 VS, VD (V) –0.2 09207-051 0 0 50 75 100 Figure 17. Leakage Currents as a Function of Temperature, 12 V Single Supply 0.4 0.6 VDD = 36V VSS = 0V VBIAS = 1V/30V VDD = +15V VSS = –15V VBIAS = +10V/–10V LEAKAGE CURRENT (nA) IS (OFF) + – ID (OFF) – + 0.2 ID, IS (ON) – – 0 IS (OFF) – + –0.2 ID, IS (ON) + + 0.2 ID, IS (ON) + + IS (OFF) + – 0 ID (OFF) – + ID, IS (ON) – – –0.2 IS (OFF) – + –0.4 ID (OFF) + – 0 25 50 75 TEMPERATURE (°C) 100 125 09207-041 ID (OFF) + – Figure 15. Leakage Currents as a Function of Temperature, ±15 V Dual Supply Rev. C | Page 13 of 24 –0.6 0 25 50 75 100 125 TEMPERATURE (°C) Figure 18. Leakage Currents as a Function of Temperature, 36 V Single Supply 09207-043 0.4 –0.4 125 TEMPERATURE (°C) Figure 14. On Resistance as a Function of VS (VD) for Different Temperatures, 36 V Single Supply LEAKAGE CURRENT (nA) 25 09207-040 ID (OFF) + – 0 ADG5433/ADG5434 –20 –30 –30 ACPSRR (dB) –20 –40 –50 –60 –50 –60 DECOUPLING CAPACITORS –70 –80 –80 –90 –90 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) NO DECOUPLING CAPACITORS –40 –70 –100 1k TA = 25°C VDD = +15V VSS = –15V –10 –100 1k 09207-036 OFF ISOLATION (dB) –10 0 TA = 25°C VDD = +15V VSS = –15V 100k 1M 10M FREQUENCY (Hz) Figure 19. Off Isolation vs. Frequency Figure 22. ACPSRR vs. Frequency 0 TA = 25°C –10 VDD = +15V VSS = –15V 0.12 VDD= 12V, VSS= 0V, VS = 6V p-p 0.10 –20 –30 LOAD = 1kΩ TA = 25°C 0.08 THD + N (%) CROSSTALK (dB) 10k 09207-037 0 Data Sheet –40 –50 –60 0.06 VDD = 36V, VSS = 0V, VS = 18V p-p 0.04 –70 –80 VDD = 15V, VSS = 15V, VS = 15V p-p 0.02 –90 1M 10M 100M 1G FREQUENCY (Hz) 09207-039 100k 0 10k 15k 20k FREQUENCY (Hz) Figure 20. Crosstalk vs. Frequency 350 5k 0 09207-038 VDD = 20V, VSS = 20V, VS = 20V p-p –100 10k Figure 23. THD + N vs. Frequency 0 TA = 25°C TA = 25°C VDD = +15V VSS = –15V –0.5 300 VDD = +20V VSS = –20V 200 INSERTION LOSS (dB) VDD = +15V VSS = –15V VDD = +36V VSS = 0V 150 100 VDD = +12V VSS = 0V 50 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 10 0 10 20 30 VS (V) 40 Figure 21. Charge Injection vs. Source Voltage –5.0 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 24. Bandwidth Rev. C | Page 14 of 24 100M 1G 09207-035 –4.5 0 –20 09207-033 CHARGE INJECTION (pC) –1.0 250 Data Sheet ADG5433/ADG5434 350 300 VDD = +12V, VSS = 0V VDD = +36V, VSS = 0V 200 150 VDD = +15V, VSS = –15V 100 VDD = +20V, VSS = –20V 50 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 09207-034 TIME (ns) 250 Figure 25. tTRANSITION Times vs. Temperature Rev. C | Page 15 of 24 ADG5433/ADG5434 Data Sheet TEST CIRCUITS S1 NC D VSS 0.1µF 0.1µF A S2 A VDD ID (ON) IS (OFF) VDD 09206-023 VD VS SxA IN NETWORK ANALYZER VSS NC SxB 50Ω 50Ω VS Figure 26. On and Off Leakage Dx VIN RL 50Ω GND VOUT S OFF ISOLATION = 20 log D VOUT VS Figure 29. Off Isolation IDS 09207-021 RON = V/IDS VS VDD VSS 0.1µF 0.1µF Figure 27. On Resistance AUDIO PRECISION VDD VDD VSS VS V p-p INx Dx VSS VIN RL 1kΩ VOUT 09207-031 GND RL 50Ω Dx SxB VS RS R 50Ω Figure 30. THD + Noise INx GND VDD VSS 0.1µF 0.1µF 09207-030 VOUT CHANNEL-TO-CHANNEL CROSSTALK = 20 log VS VDD Figure 28. Channel-to-Channel Crosstalk INx NETWORK ANALYZER VSS SxA NC SxB 50Ω 50Ω VS Dx VIN RL 50Ω GND INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 31. Bandwidth Rev. C | Page 16 of 24 VOUT 09207-029 VOUT VDD SxA VSS Sx 0.1µF 0.1µF NETWORK ANALYZER 09207-028 V Data Sheet ADG5433/ADG5434 VDD 0.1µF VSS VDD VIN 50% 50% VIN 50% 50% VSS SxB VS 0.1µF Dx SxA VOUT RL 300Ω INx CL 35pF 90% 90% VOUT tON tOFF 09207-024 GND VIN Figure 32. Switching Timing 0.1µF VDD VSS VDD VSS SxB VS 0.1µF VIN Dx SxA VOUT RL 300Ω INx VOUT 80% CL 35pF tD GND tD 09207-025 VIN Figure 33. Break-Before-Make Delay, tD VDD VSS VDD VSS 0.1µF 3V ENABLE DRIVE (VIN) ADG5433 IN1 S1A IN2 S1B VS 0V VOUT IN3 VIN VOUT D1 EN RL 300Ω GND 50Ω 50% 50% CL 35pF OUTPUT 0V tOFF (EN) 0.9VOUT 0.9VOUT 09207-026 0.1µF tON (EN) Figure 34. Enable Delay, tON (EN), tOFF (EN) VS VDD VSS VDD VSS VIN (NORMALLY CLOSED SWITCH) SxB Dx NC SxA CL 1nF INx VIN 0.1µF GND VOUT ON OFF VIN (NORMALLY OPEN SWITCH) VOUT ∆VOUT Figure 35. Charge Injection Rev. C | Page 17 of 24 QINJ = CL × ∆VOUT 09207-027 0.1µF ADG5433/ADG5434 Data Sheet TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN represents digital input capacitance. ISS ISS represents the negative supply current. tON (EN) tON (EN) represents the delay time between the 50% and 90% points of the digital input and switch on condition. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. tOFF (EN) tOFF (EN) represents the delay time between the 50% and 90% points of the digital input and switch off condition. RON RON is the ohmic resistance between Terminal D and Terminal S. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. ∆RON ∆RON represents the difference between the RON of any two channels. RFLAT (ON) The difference between the maximum and minimum value of on resistance as measured over the specified analog signal range is represented by RFLAT (ON). IS (Off) IS (Off) is the source leakage current with the switch off. tD tD represents the off time measured between the 80% point of both switches when switching from one address state to another. Off Isolation Off isolation is a measure of unwanted signal coupling through an off channel. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. VINH VINH is the minimum input voltage for Logic 1. On Response On response is the frequency response of the on switch. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. CD (Off) CD (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. CD (On), CS (On) CD (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by THD + N. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is a measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. Rev. C | Page 18 of 24 Data Sheet ADG5433/ADG5434 TRENCH ISOLATION In the ADG5433/ADG5434, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. PMOS P-WELL N-WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 36. Trench Isolation Rev. C | Page 19 of 24 09207-032 In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up proof switch. NMOS ADG5433/ADG5434 Data Sheet APPLICATIONS INFORMATION The ADG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, aerospace and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5433/ADG5434 high voltage switches allow single-supply operation from 9 V to 40 V and dual supply operation from ±9 V to ±22 V. The ADG5433/ADG5434 (as well as other select devices within this family) achieve 8 kV human body model ESD ratings, which provide a robust solution eliminating the need for separate protect circuitry designs in some applications. Rev. C | Page 20 of 24 Data Sheet ADG5433/ADG5434 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.70 SEATING PLANE 0.45 0.40 0.35 5 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters Rev. C | Page 21 of 24 08-16-2010-C TOP VIEW 8 ADG5433/ADG5434 Data Sheet 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 39. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.75 2.60 SQ 2.35 11 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 5 10 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 020509-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-20-8) Dimensions shown in millimeters ORDERING GUIDE Model1 ADG5433BRUZ ADG5433BRUZ-REEL7 ADG5433BCPZ-REEL7 ADG5434BRUZ ADG5434BRUZ-REEL7 ADG5434BCPZ-REEL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. Rev. C | Page 22 of 24 EN Pin Yes Yes Yes No No Yes Package Option RU-16 RU-16 CP-16-17 RU-20 RU-20 CP-20-8 Data Sheet ADG5433/ADG5434 NOTES Rev. C | Page 23 of 24 ADG5433/ADG5434 Data Sheet NOTES ©2010–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09207-0-6/13(C) Rev. C | Page 24 of 24