ALTERA Datasheet

2016
DFPIC165X IP Core
8-bit RISC Microcontroller v. 2.03
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
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33 instructions
12 bit wide instruction word
Up to 256 bytes of internal Data Memory
Up to 4K bytes of Program Memory
Configurable hardware stack
Power saving SLEEP mode
Fully synthesizable, static synchronous design with
no internal tri-states
● Scan test ready
PERIPHERALS
● Three 8 bit I/O ports
○ Three 8-bit corresponding TRIS registers
● Timer 0
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IP CORE OVERVIEW
The DFPIC165X is a low-cost, high performance, 8bit, fully static soft IP Core, dedicated to operate
with fast memory (typically on-chip). The core has
been designed with a special concern about low
power consumption. The DFPIC165X is software
compatible with PIC16C54, PIC16C55, PIC16C56,
PIC16C57 and PIC16C58 industry standards. It contains modified RISC architecture (2 times faster
than original implementation). The DFPIC165X
have enhanced core features and configurable
hardware stack. Separate instruction and data
buses allow a 12 bit wide instruction word, with a
separate 8 -bit wide data. The DFPIC165X typically
achieves a 2:1 code compression and an 8:1 speed
improvement over other 8-bit microcontrollers in
its class. The Core has 24 I/O lines and an 8-bit
timer/counter with an 8-bit programmable prescaler. The power-down SLEEP mode allows user
to reduce power consumption. The user can wake
the controller up from the SLEEP mode through a
user reset or a watchdog overflow. An integrated
Watchdog Timer with its own clock signal provides
protection against software lock-up. The
DFPIC165X Microcontroller fits perfectly in applications ranging from high-speed automotive and
appliance motor control, to low-power remote
transmitters/receivers, pointing devices and telecom processors. A built-in power save mode and a
small used area in programmable devices, make
this IP perfect for applications with space and
power consumption limitations. The DFPIC165X is
delivered with fully automated test bench and
complete set of tests, allowing easy package validation at each stage of SoC design flow.
8-bit timer/counter
Readable and Writable
8-bit software programmable prescaler
Internal or external clock select
Edge select for external clock
● Watchdog Timer
○ Configurable Time out period
○ 7-bit software programmable prescaler
○ Dedicated independent Watchdog Clock input
OPTIONAL PERIPHERALS
Optional peripherals (not included in the presented
DFPIC165X Microcontroller Core) are also available. The optional peripherals can be implemented
upon customer’s request.
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Full duplex UART
SPI – Master and Slave Serial Peripheral Interface
I2C bus controller – Master
I2C bus controller – Slave
CONFIGURATION
The following parameters of the DFPIC165X core
can be easily adjusted to requirements of a dedicated application and technology. The configuration of the core can be effortlessly done, by changing appropriate constants in the package file. There
is no need to change any parts of the code.
 RAM memory type
 RAM size
 Program Memory size
 Number of hardware stack levels
 SLEEP mode
 WATCHDOG Timer
CPU FEATURES
 Timer system
● Software compatible with industry standard
PIC16C5X
● Harvard architecture 2 times faster compared to
original implementation
 PORTS A,B,C
-
synchronous
asynchronous
up to 256
default 128
up 4 kWords
default 2k
1-8
default 2
used
unused
used / width
unused
used
unused
used
unused
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
DELIVERABLES
♦
Source code:
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VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
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Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
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Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
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IP Core implementation support
3 months maintenance
● Delivery of the IP Core and documentation updates, minor
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and major versions changes
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use. There are two formats of the delivered IP
Core:
VHDL or Verilog RTL synthesizable source code
FPGA EDIF/NGO/NGD/QXP/VQM (Netlist)
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs arithmetic
and logic operations, during execution of an instruction. This module contains work register (W)
and Status register.
Control Unit – It performs the core synchronization
and data flow control. This module manages execution of all instructions. Performs decode
and control functions for all other blocks. It contains program counter (PC) and hardware stack.
Hardware Stack – The DFPIC165X configurable
hardware stack. The stack space is not a part
of either program or data space and the stack
pointer is not readable or writable. The PC is
pushed onto the stack, when CALL instruction is
executed or an interrupt causes a branch.
The stack is popped during RETLW instruction execution. The stack operates as a circular buffer. This
means that after the stack has been pushed two
times, the third push overwrites the value that was
stored from the first push.
RAM Controller – It performs interface functions
between Data memory and DFPIC165X internal
logic. It assures correct Data memory addressing
and data transfers. The DFPIC165X supports two
addressing modes: direct or indirect. In Direct
Addressing, the 8-bit direct address is computed
from FSR(7:5) bits and from 5 least significant bits
of instruction word. Indirect addressing is possible,
by using the INDF register. Any instruction using
INDF register, actually accesses data pointed
to by FSR (file select register). Reading INDF register indirectly, will produce 00h. Writing to the INDF
register indirectly, results in a no-operation. An
effective 8-bit address is obtained from an 8-bit
FSR register.
Timer 0 – Main system’s timer and prescaler.
The DFPIC165X Timer operates in two modes: 8-bit
timer or 8-bit counter. In the “timer mode”, timer
registers are incremented every 4 CLK periods.
When the prescaler is assigned into the TIMER prescale ratio can be divided by 2, 4 .. 256. In the
“counter mode”, the timer register is incremented
every falling or rising edge of T0CKI pin, depending
on T0SE bit in OPTION register.
Watchdog Timer – it is a free running timer. WDT
has own clock input, separate from system clock. It
means, that the WDT will run even if the system
clock is stopped by execution of SLEEP instruction.
During normal operation, a WDT timeout generates a Watchdog reset. If the device is in SLEEP
mode, the WDT timeout causes the device to wake
up and continue with normal operation.
I/O Ports – Block contains DFPIC165X’s general
purpose I/O ports and data direction registers
(TRIS). The DFPIC165X has three 8-bit full bidirectional ports PORT A, PORT B and PORT C. Read
and write accesses to the I/O port are performed
via their corresponding SFR’s PORTA, PORTB,
PORTC. The reading instruction always reads the
status of Port pins. Writing instructions always
write into the Port latches. Each port’s pin has a
corresponding bit in TRISA, TRISB and TRISC registers. When the bit of TRIS register is set,
this means that the corresponding bit of port is
configured as an input (output drivers are set into
the High Impedance).
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
BLOCK DIAGRAM
clk
por
Hardware
Stack
mclr
sleep
prgdata
prgaddr
Most instruction of DFPIC165X is executed within 2
CLK cycles. Except the conditional program
memory branches, in case the condition of branch
instruction is met. The table below shows sample
instructions execution times:
ALU
Control
Unit
t0cki
RAM
Controller
Timer
0
ramdatai
ramdatao
ramaddr
ramwe
ramoe
Mnemonic
DFPIC165X
PIC16C54
Impr.
operands
(CLK cycles)
(CLK cycles)
ADDWF
2
4
2
ANDWF
2
4
2
RLF
2
4
2
BCF
2
4
2
DECFSZ
2(4)1
4(8)1
2
INCFSZ
2(4)1
4(8)1
2
BTFSC
2(4)1
4(8)1
2
BTFSS
2(4)1
4(8)1
2
CALL
2
8
4
GOTO
2
8
4
RETLW
2
8
4
1
- number of clock in case that result of operation is 0.
portai
portbi
portci
portao
portbo
portco
trisa
trisb
trisc
I/O
Ports
Watchdog
Timer
clkwdt
IMPROVEMENT
DFPIC&DRPIC FAMILY OVERVIEW
-
-
5
5
5
1
5
5
-
2
2
-
Size (gate)
32
-
1
DoCDTM Debugger
35
-
5
Speed rate
512
-
Wake up on port pin
change
32
-
Internal Interrupts
14
32
35
-
External interrupts
64k
35
512
-
Sleep Mode
DRPIC166X
512
USART
14
CCP1
14
64k
24
16
Watchdog Timer
64k
DRPIC1655X
33
35
Timer 2
DFPIC166X
-
Timer 1
128
512
Timer 0
12
14
I/O Ports
Data Memory space
2k
64k
Number of instructions
Program word length
DFPIC165X
DFPIC1655X
Design
RAM extension to 32kB
Program Memory space
The family of DCD DFPICXX & DRPICXX IP Cores combines high–performance, low cost, and small compact size,
offering best price/performance ratio in the IP Market. DCD’s Cores are designed to be used in cost-sensitive
consumer products, computer peripherals, office automation, automotive control systems, security and telecommunication applications. DCD’s DFPICXX & DRPICXX IP Cores family contains four 8-bit microcontroller
Cores to meet your needs in the best way: DFPIC165X 12-bit program word, DFPIC1655X 14-bit program word,
and also DRPIC1655X and DRPIC177X single cycle microcontrollers with 14-bit program word. All three microcontroller cores are binary compatible with widely accepted PIC16C5X and PIC16CXXX. They have modified
RISC architectures, two or four times faster than the original ones. The DFPICXXX & DRPICXX IP Cores are written in pure VHDL/VERILOG HDL languages, which makes them technologically independent. All of the DFPICXX
& DRPICXX family members are supported by a power saving SLEEP mode, which allows the user to configure
the watchdog time-out period and a number of hardware stack levels. DFPICXX & DRPICXX can be fully customized, according to the customer requirements.
*
2 700
3 900
2
*
6 000
4
*
4 800
4
*
6 700
DFPIC & DRPIC family of High Performance Microcontroller Cores
* Optional
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
PINOUT
Digital Core Design Headquarters:
clk
clkwdt
por
mclr
Wroclawska 94, 41-902 Bytom, POLAND
prgdata(11:0)
prgaddr(11:0)
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramwe
t0cki
portai(7:0)
portbi(7:0)
portci(7:0)
CONTACT
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
sleep
portao(7:0)
portbo(7:0)
portco(7:0)
trisa(7:0)
trisb(7:0)
trisc(7:0)
PINS DESCRIPTION
PIN
clk
clkwdt
por
mclr
prgdata[11:0]
ramdatai[7:0]
t0cki
portxi[7:0]
prgdata[11:0]
ramdatai[7:0]
prgaddr[11:0]
ramdatao[7:0]
ramaddr[7:0]
ramwe
ramoe
sleep
portxo[7:0]
trisx[7:0]
TYPE
input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output
output
output
DESCRIPTION
Global clock
Watchdog clock
Global reset Power On Reset
User reset
Data bus from program memory
Data bus from int. data memory
Timer 0 input
Port A, B, C input
Data bus from program memory
Data bus from int. data memory
Program memory address bus
Data bus for internal data memory
RAM address bus
Data memory write
Data memory output enable
Sleep signal
Port A, B, C output
Port data direction pins
PERFORMANCE
The following table gives a survey about the Core
area and performance in ALTERA® devices after
Place & Route:
Device
Speed grade
Logic Cells
Fmax
CYCLONE
-6
551
105 MHz
CYCLONE II
-6
547
108 MHz
STRATIX
-5
551
108 MHz
STRATIX II
-3
456
178 MHz
STRATIX GX
-5
551
109 MHz
APEX II
-7
635
73 MHz
APEX20KC
-7
635
68 MHz
APEX20KE
-1
635
56 MHz
APEX20K
-1
635
45 MHz
ACEX1K
-1
648
50 MHz
FLEX10KE
-1
648
48 MHz
*CPU – consisted of ALU, Control Unit, Bus Controller, Hardware Stack, 256 B RAM, 4k of Program memory
Core performance in ALTERA® devices
4
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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