2016 DMAC-RMII IP Core Media Access Controller with RMII v. 2.09 COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. ● Static synchronous design with positive edge clocking and synchronous reset ● No internal tri-states ● Scan test ready APPLICATIONS ● Embedded microprocessor boards ● Networking devices (Network Interface Cards, routers, switches) ● Communications systems DELIVERABLES ♦ Source code: ● ● ● IP CORE OVERVIEW The DMAC-RMII is a hardware implementation of the media access control protocol, defined by the IEEE 802 standard. The DMAC-RMII, in cooperation with an external PHY device, enables network functionality in design. It is capable of transmitting and receiving Ethernet frames, to and from the network. Half and full duplex modes are supported, as well as 10 and 100 Mbit/s speed. The core is able to work with wide a range of processors: 8, 16 and 32 bit data bus, with little or big endian byte order format. The design is technology independent and thus can be implemented in various process technologies. This core strictly conforms to the IEEE 802.3 standard. KEY FEATURES ● Conforms to IEEE 802.3-2002 specification ● 8/16/32-bit CPU slave interface with little or big endianess ● Simple interface allows easy connection to CPU ● Narrow address bus with indirect I/O interface to the transmit and receive data dual port memories ● Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant RMII PHYs ● Reduced Media Independent Interface (RMII) for connection to external 10/100 Mbps PHY transceivers ● Supports full and half duplex operation at 10 or 100 Mbps ● CRC-32 algorithm calculates the FCS nibble at a time, automatic FCS generation and checking, able to capture frames with CRC errors if required ● Lite design, small gate count and fast operation ● Programmable or fixed MAC address ● Promiscuous mode support ● Dynamic PHY configuration by STA management interface ● Receive FIFO able to store many messages at a time ● Allows operation from a wide range of input bus clock frequencies ● Fully synthesizable ♦ VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF VHDL & VERILOG test bench environment ● ● ● ♦ Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation ● ● ● ♦ ♦ ♦ Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support ● ● IP Core implementation support 3 months maintenance ● ● Delivery of the IP Core and documentation updates, minor and major versions changes Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code called HDL Source code FPGA EDIF/NGO/NGD/QXP/VQM called Netlist 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. BLOCK DIAGRAM The figure below shows the DMAC-RMII IP Core block diagram. TX RAM pins rmiiclk mb100 rmiitxen rmiitxd(1:0) mdi mdc mdo mdoe rmiirxer rmiicrsdv rmiirxd(1:0) Transmit Module STA Receive Module TX RAM Interface Synchronization Logic Control & I/O Logic RX FIFO clk rst rdcs wrcs rd wr docdbusctrl be(3:0) rdaddr(4:0) wraddr(4:0) datai(31:0) datai(31:0) datao(31:0) RX RAM pins PINS DESCRIPTION PIN clk rmiiclk mb100 rst rdcs wrcs rd wr rdaddr(4:0) wraddr(4:0) be(3:0) 2 datai(31:0)1 qmr(31:0) qmt(31:0) rmiirxd(1:0) rmiicrsdv rmiirxer mdi docdbusctrl datao(31:0)1 irq dmr(31:0) waddrmr(8:0) raddrmr(8:0) enrmr enwmr dmt(31:0) waddrmt(8:0) raddrmt(8:0) enrmt enwmt rmiitxen rmiitxd(1:0) mdc mdo mdoe TYPE input input input input input input input input input input input input input input input input input input input output output output output output output output output output output output output output output output output output DESCRIPTION Global CPU clock RMII 50 MHz reference clock Select 100 Mb speed Global reset Read chip select Write chip select Read data strobe Write data strobe Host read address bus Host write address bus Host byte enable Host output data bus RX DPRAM data output TX DPRAM data output RMII receive data RMII carrier sense/receive valid RMII receive error Management data input DoCD debugger input Host input data bus Interrupt signal RX DPRAM data input RX DPRAM write address RX DPRAM read address RX DPRAM read enable RX DPRAM write enable TX DPRAM data input TX DPRAM write address TX DPRAM read address TX DPRAM read enable TX DPRAM write enable RMII transmit enable RMII transmit data Management clock Management data output Management data output enable SYMBOL rst rdcs wrcs qmt(31:0) rd wr be(3:0)2 datai(31:0)1 rdaddr(4:0) wraddr(4:0) clk qmr(31:0) rmiirxd(1:0) rmiicrsdv rmiirxer rmiiclk mdi docdbusctrl dmt(31:0) waddrmt(8:0) raddrmt(8:0) enrmt enwmt datao(31:0)1 irq dmr(31:0) waddrmr(8:0) raddrmr(8:0) enrmr enwmr rmiitxd(1:0) rmiitxen mdo mdoe mdc 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. UNITS SUMMARY CONTACT Transmit module – Performs transmit management functions, sends frames to Ethernet medium. Digital Core Design Headquarters: Receive module – is responsible for receiving frames from the Ethernet. Provides necessary functions for frame decapsulation, CRC checking, address recognizing and error detection. e-mail: tel.: fax: Synchronization logic – There are 3 clock domains in the DMAC-RMII core - this module performs synchronization between them. Please check: Wroclawska 94, 41-902 Bytom, POLAND [email protected] 0048 32 282 82 66 0048 32 282 74 37 Distributors: http://dcd.pl/sales TX RAM / RX FIFO RAM interfaces – Interfaces to external dual port memories used by the DMACRMII core, to store received and transmitted frames. Control and I/O logic – This module provides interface to CPU/BUS. It exchanges data and control logic with transmit and receive modules, thus controls these, to perform transmit and receive operations. STA – Station Management entity, enables communication with PHY, via simple serial management interface. PERFORMANCE The following table gives a survey about the Core area and performance in ALTERA® devices after Place & Route (all key features included): Device STRATIX IV STRATIX III STRATIX II CYCLONE IV CYCLONE III CYCLONE II STRATIX GX STRATIX CYCLONE APEX II APEX20KC APEX20KE APEX20K Speed grade Logic Cells -1 896 + 4 kB RAM -2 898 + 4 kB RAM -3 892 + 4 kB RAM -6 1341 + 4 kB RAM -6 1342 + 4 kB RAM -6 1340 + 4 kB RAM -5 1255 + 4 kB RAM -5 1255 + 4 kB RAM -6 1254 + 4 kB RAM -7 1622 + 4 kB RAM -7 1622 + 4 kB RAM -1 1622 + 4 kB RAM -1 1622 + 4 kB RAM Core performance in ALTERA® devices Fmax [MHz] clk / rmiiclk 420 / 350 400 / 350 300 / 260 200 / 200 190 / 190 158 / 170 152 / 138 162 / 137 148 / 133 145 / 111 127 / 117 108 / 111 86 / 88 3 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.