2016 DQSPI IP Core Serial Peripheral Interface – Master/Slave with single, dual and quad SPI Bus support v. 2.01 COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. IP CORE OVERVIEW The DQSPI is a revolutionary quad SPI designed to offer the fastest available operations for any serial SPI memory. It is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Moreover, IP Core supports all 8, 16, 32 bit processors available on the market. The DQSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock SCK. It lets the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it’s capable of interprocessor communications in a multi‐master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the four serial data lines. In the Single SPI mode data is simultaneously transmitted and received, in DUAL and QUAD SPI modes – data is shifted in or out on respectively two or four data lines at once. Transfer speed can additionally be doubled by using the DDR protocol (Double Data Rate, this feature allows the DQSPI to transfer/receive data on both falling and rising edges of SCK. DDR together with the QUAD SPI transfer allows the 8 bits of data to be sent/received within single SCK clock cycle. This makes the DQSPI perfect for systems where performance is essential where code can be moved from non-volatile memory to fast RAM, or for systems where device size and cost are the key, where program code can be executed directly from nonvolatile memory using an approach known as Execute-in-Place. DCD’s IP Core is a technology independent design that can be implemented in a variety of process technologies. The system can be configured as a master or a slave device. Data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. Clock control logic allows a selection of clock polarity, phase and a choice of four fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects bit rates for the serial clock. The DQSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. Error‐detection logic is included to support interprocessor communications. A write‐collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple‐master mode‐fault detector automatically disables DQSPI output drivers, if more than one SPI device simultaneously attempts to become bus master. The DQSPI supports two DMA modes: single transfer and multi‐transfer. These modes allow DQSPI to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. DQSPI is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. PINS DESCRIPTION PIN TYPE ACTIVE DESCRIPTION clk input Global clock rst input Low Global reset datai* input Data bus input addr input Processor address lines cs input Low Chip select rd input Low Processor read strobe we input Low Processor write strobe scki input SPI clock input mi input Master serial data input si input Slave serial data input ss input Low Slave select rxdmaclr input High DMA Request Clear txdmaclr input High DMA Request Clear Io2i, io3i input ‐ QUAD SPI data input datao* output Data bus output irq output High Interrupt request txdmareq output High DMA service request rxdmareq output High DMA service request scko output SPI clock output scken output SPI clock output enable mo output Master serial data output so output Slave serial data output soen output Slave data output enable ss7o-ss0o output low Slave select outputs oo2o, io3o output QUAD SPI data outputs * Configurable Data Bus size – the same as used FIFO’s. Allows 8, 16 or 32 bits data reads and writes to and from TX and RX FIFO’s. 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. FEATURES ● ● ● ● ● ● ● ● ● ● ● Operates with 8, 16 and 32 bit CPUs Full duplex synchronous serial data transfer DMA support Support for 32, 16 and 8 bit systems Support for various system Bus Standards Single, Dual and Quad SPI transfer DDR support (Double Data Rate) Optionally available Execute-in-Place Multi-master system supported Optional FIFO size extension (128, 256, 512B) Up to 8 SPI slaves can be addressed o o ● ● ● ● ● ● ● Software Slave Select Output – SSO ‐ selection Automatic Slave Select outputs assertion during each byte transfer System error detection Interrupt generation Various Bit rates supported Bit rate in fast SPI Mode ½ CLK Four transfer formats Simple SPU and DMA interface Fully synthesizable, static synchronous design with no internal tri‐states data buffer. The system is single buffered in the transmit direction and double buffered in the receive direction. This fact means new data for transmission cannot be written to the shifter until the previous transaction is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition will occur. DELIVERABLES ♦ ● VHDL Source Code or/and ● VERILOG Source Code or/and ● Encrypted, or plain text EDIF ♦ MSB LSB Shift Register io2o io3o TX-FIFO 64 512 moen soen ioen clk addr cs we rd Divider 2 - 512 SPR RX-FIFO 64 512 SPI Clock Logic ♦ mi si io2i io3i scko Synthesis scripts Example application Technical support ● IP Core implementation support ● 3 months maintenance ● Delivery of the IP Core and documentation updates, minor and major versions changes ● Phone & email support scki scken SPI Controller SS Ctrl. Reg. datai ss ss7o ss6o ss5o ss4o ss3o ss2o ss1o ss0o Read buffer FIFO Ctrl. Reg. ♦ ♦ ♦ LICENSING SPI Ctrl. Reg. datao Technical documentation ● Installation notes ● HDL core specification ● Datasheet CPHA CPOL SPI Status Reg. VHDL & VERILOG test bench environment ● Active-HDL automatic simulation macros ● ModelSim automatic simulation macros ● Tests with reference responses BLOCK DIAGRAM mo so Source code: STFCR When an SPI transfer occurs (in single SPI mode), an 8‐bit character is shifted out on data pin while a different 8‐bit character is simultaneously shifted in though a second data pin. Another way to view this transfer is that an 8‐bit shift register in the master and another 8‐bit shift register in the slave are connected as a circular 16‐bit shift register. When a transfer occurs, this distributed shift register is shifted eight bit positions; thus, the characters in the master and slave are effectively exchanged. The central element in the SPI system is the block containing the shift register and the read Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code called HDL Source code FPGA EDIF/NGO/NGD/QXP/VQM called Netlist 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. TYPICAL uC / BUS CONNECTION The figure below shows a typical connection the DQSPI Core with microcontroller and other SPI Master/Slave devices. VDD RP RP RP RP RP MISO MOSI SCK IO2 IO3 RS NOR data RS RS RS RS RS RS RS RS tri-state buffer 8 datao datai addr 3 uC RS addr cs rd wr irq cs rd we irq system clk system rst clk rst mi io0 so Tris Slave device io1 soen si DQSPI sck mo Tris moen io2 scki io3 scko tris scken DSPI ASIC/FPGA chip ss io2i io2o tris ioen tris io3o io3i ss7o-ss0o ss QUAD SPI TRANSFER DDR (Double Data Rate) QUAD SPI TRANSFER 3 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. TRANSFER FORMATS The software can select any of four combinations of serial clock (SCK) phase and polarity, using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit, selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers, to allow a master device to communicate with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial peripheral. SCK CYCLE# 1 2 3 4 5 6 7 8 LSB SCK (CPOL=0) SCK (CPOL=1) MOSI MISO MSB MSB 6 5 4 3 2 1 6 5 4 3 2 1 4 5 6 7 8 LSB LSB SS SCK CYCLE# 1 2 3 SCK (CPOL=0) SCK (CPOL=1) MOSI MISO MSB MSB 6 5 4 3 2 1 6 5 4 3 2 1 LSB SS PERFORMANCE UNIT SUMMARY Shift Register – The heart of the DSPI controller, shifts in and out data from the DSPI controller regarding to the appropriate edge of the SCK. Receiver FIFO ‐ The Rx FIFO can be 64 (128, 256, 512) levels deep, it receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if interrupt is enabled, the DSPI will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it is full, and will not accept any next byte. Any more data entering the Rx shift register will set the Overrun Error flag. Transmitter FIFO ‐ the Tx portion of the DSPI transmits data through SO/MO as soon as the CPU loads a byte into the Tx FIFO in Master mode. In Slave mode the transmission is started after correct edge of the SCK signal. The DSPI will prevent loads to the Tx FIFO if it currently holds 64 (128, 256, 512) characters (depending on SFCR(5) bit value and selected FIFO size). Loading to the Tx FIFO again will be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. Divider – Divider allows dividing the global CLK signal by 2 up to 1024. This divided signal is used to generate the SCKO – Serial Clock Signal in Master mode. SPI Clock Logic, ‐ this module controls phase and polarity of generated/received SCK signal. On correct SCK edge generates shift signal to SPI Shift register. SPI Controller ‐ controls Master/Slave operations, manages the interrupt requests, error detection etc. The following table gives a survey about the Core area and performance in XILINX® devices, after Place & Route: Memory Blocks ZYNQ 7000 368 1 ZYNQ 364/163 2 KINTEX Ultra Scale 364 1 KINTEX 7 348/173 2 ARTIX 7 331/199 2 VIRTEX Ultra Scale 364 1 VIRTEX 7 356/184 2 VIRTEX 6 363/130 2 VIRTEX 5 371/201 2 VIRTEX 4 573/348 2 SPARTAN 6 330/130 2 SPARTAN 3E 556/344 2 SPARTAN 3 552/342 2 Core performance in XILINX® devices Device LUTs/Slices Fmax MHz 330 201 330 355 202 330 293 186 202 149 116 108 109 CONTACT Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: [email protected] 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales 4 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.