DI2SB Core connection to passive device and global I2C bus

Application note v4.04 DI2CSB connection to passive device The document describes connection of the DI2CSB Core to global I2C Bus and passive devices (LCD Driver, Memory etc.). It also illustrates a DI2CSB read from passive device and write to device timings. VDD
RP
RP
SDA
SCL
RS
Device
clk
rst
datai
datao
datao
datai
rd
wr
rd
wr
RS
RS
RS
sdai
sda
sdao
open drain
DI2CSB
clk
rst
scli
Master
device
scl
Connection DI2CSB to global I2C bus and a target device. Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved -1- All trademarks mentioned in this document are trademarks of their respective owners. Application note v4.04 After completion of I2C data transfer the DI2CSB initiates a parallel data transfer to/from passive device. The figures below illustrate a parallel data read and write sequences. 0ns
100ns
200ns
300ns
400ns
500ns
600ns
700ns
8
clk
datao
DWA
DWB
1 clk
wr
rd
DEVICE_REG
OLD VALUE
DWA
DWB
datai
DI2CSB data write to device timing Note: clk datao datai DEVICE_REG 0ns
100ns
‐ system clock period ‐ DI2CSB data output bus ‐ DI2CSB data input bus ‐ written register inside Device 200ns
300ns
400ns
500ns
600ns
700ns
8
clk
datai
DRA
DRB
1 clk
rd
wr
DI2CSB_REG
OLD VALUE
DRA
DRB
datao
DI2CSB data read from device timing Note: clk datao datai DI2CSB_REG ‐ system clock period ‐ DI2CSB data output bus ‐ DI2CSB data input bus ‐ written register inside DI2CSB Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved -2- All trademarks mentioned in this document are trademarks of their respective owners. 
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