DSPI Core connection to SPI bus

Application note v4.04 DSPI Core connection to SPI Bus This document describes how to connect DSPI Core into global SPI Bus. VDD
RP
RP
RP
MISO
MOSI
SCK
DSPI
ASIC/FPGA chip
RS
RS
RS
RS
RS
RS
Slave
device
datao
mi
datai
addr
so
cs
rd
we
int
miso
mosi
open drain
si
DSPI
mo
sck
open drain
ss
scki
clk
rst
scko
sckz
tris-state buffer
ss7o-ss0o
ss
Slave select signal drived by another
SPI master, in multimaster system
Connection DSPI to global SPI bus Input Schmidt gates are recommended especially in systems with fast data transfer (>3Mb per second). They prevent incidental erroneous behavior caused by slow rising edges on input MI, SI and SCKI lines. The tri‐state buffer on SCKO pin, should be implemented only in multimaster systems, it prevents driving SCK line by two different SPI Master devices. When the DSPI device is configured as an SPI Slave, the SCKO line is driven in to high impedance. Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved All trademarks mentioned in this document are trademarks of their respective owners. 
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