ASIC Datasheet

2016
D68HC08
8-bit Microcontroller v. 1.00
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
CPU FEATURES
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Software compatible with standard 68HC08
Cycle compatible with the original implementation
Pin-out and memory interface identical
to MC68H08 Microcontrollers
Optional enhanced memory interface with Demultiplexed Address/Data Bus to allow easy integration with external memories
Interrupt Controller
Two power saving modes: STOP, WAIT
Fully synthesizable, static synchronous design with
no internal tri-states
No internal reset generator or gated clock
Scan test ready
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DELIVERABLES
IP CORE OVERVIEW
The D68HC08 is an advanced 8-bit MCU IP Core
with highly sophisticated, on-chip peripheral capabilities. The D68HC08 soft core is binary and cycle compatible with the industry standard Motorola
68HC08 8-bit microcontroller. In the standard
configuration, the Core has integrated on-chip
major peripheral functions. The D68HC08 Microcontroller Core contains a full-duplex UART - Asynchronous Serial Communication Interface (SCI) and
a Synchronous Serial Peripheral Interface (SPI).
Two 16-bit, flexible timing systems with input capture lines, output-compare lines and PWM functionality. A self-monitoring circuitry is included onchip, to protect against system errors. A computer
operating properly (COP) watchdog system protects against software failures. An illegal opcode
detection circuit provides a non-maskable interrupt, if an illegal opcode is detected. Two softwarecontrolled power-saving modes - WAIT and STOP
are available to conserve additional power. These
modes make the D68HC08 IP Core especially attractive for automotive and battery-driven applications. The D68HC08 is fully customizable - it is
delivered in an exact configuration to meet users’
requirements. It includes fully automated test
bench with complete set of tests, allowing easy
package validation at each stage of SoC design
flow. Each DCD's D68XX Core has a built-in support
TM
for DCD Hardware Debug System called DoCD .
It's a real-time hardware debugger, which provides debugging capability of a whole System-onTM
Chip (SoC). DoCD provides non-intrusive debugging of running application. It can halt, run, step
into or skip an instruction, read/write any contents
of a microcontroller, including all registers, SFRs,
including user defined peripherals, data and program memories.
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Source code:
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VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
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Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
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Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
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IP Core implementation support
3 months maintenance
o
o
Delivery of the IP Core and documentation updates, minor
and major versions changes
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use.
There are two formats of the delivered IP Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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PERIPHERALS
The peripherals listed below are implemented
in a standard configuration of the D68HC08.
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TM
DoCD
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Standard non-return-to-zero format (NRZ)
8 or 9 bit data transfer
Integrated BAUD Rate generator
Enhanced receiver data sampling technique
Noise, Overrun and Framing errors detection
IDLE and BREAK characters generation
Wake-up block to recognize UART wakeup from IDLE
Three SCI Related interrupts
Floating-Point Math Coprocessor (DFPMU) - IEEE754 standard single precision real, word and short
integers
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FADD, FSUB- addition, subtraction
FMUL, FDIV- multiplication, division
FSQRT- square root
FUCOM- compare
FCHS - change sign
FABS - absolute value
FSIN, FCOS- sine, cosine
FPTAN, FPATAN- tangent, arcs tangent
Additional special internal interrupt dedicated for
DFPAU or DFPMU
BLOCK DIAGRAM
clk
reset
Opcode
Decoder
Memory
controller
SPI – Master and Slave Serial Peripheral Interface
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Mode fault error
Write collision error
Software selectable polarity and phase of serial clock
SCK
System errors detection
Allows operation from a wide range of system clock
frequencies
Interrupt generation
DESIGN FEATURES
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FADD, FSUB - addition, subtraction
FMUL, FDIV- multiplication, division
FSQRT- square root
FUCOM - compare
FCHS - change sign
FABS - absolute value
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Four input capture/compare channels
Buffered and not buffered PWM
Programmable TIM clock input
Free-running or modulo up-count operation
TIM counter stop and reset bits
Full-duplex UART - SCI
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Dedicated vector and interrupt priority for each interrupt source
Programmable PIT clock input
Free-running or modulo up-count operation
PIT counter stop and reset bits
Floating-Point Arithmetic Coprocessor (DFPAU)
IEEE-754 standard single precision
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Programmable Interrupt Timer (PIT)
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BUS
moda
Controller
modb
On-Chip Debugger
16-bit Timer Interface Modules TIMA and TIMB
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Processor execution control
Read, write all processor contents
Hardware execution breakpoints
Three wire communication interface
I/O Ports
Interrupt Controller
Allows operation from a wide range of clock frequencies (build-in 8-bit timer)
User-defined timing
One global system clock
Synchronous reset
All asynchronous input signals are synchronized
before internal use
halt
porta
portb
Control
Unit
I/O
Ports
irq
Interrupt
Controller
PIT
Programmable
Interrupt
Timer
portc
portd
porte
portf
Timer
A
Timer
B
OPTIONAL PERIPHERALS
Optional peripherals (not included in the presented D68HC08 Microcontroller Core) are also available. The optional peripherals can be implemented
upon customer’s request.
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PWM – Pulse Width Modulation Timer/Counter
with up to four 8-bit or two 16-bit PWM channels
Memory extension unit and Chip select
I2C Master & Slave bus controllers
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Master operation
Multi-master systems supported
Performs arbitration and clock synchronization
Interrupt generation
Supports speed up to 3,4Mb/s (standard, fast & HS
modes)
SCI Unit
ADC
Controller
adcdatai
adcdataoi
adcclock
adccs
SPI Unit
EEPROM
Controller
esi
eso
esck
ecs
ALU
DoCD
Debugger
TM
clkdocd
docddatai
docddatao
docdclk
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
clk
input
Global system clock
reset
input
Power on reset vector fetch
irq
input
Interrupt input
halt
output Stop CLK generator during STOP
portx
in/out Ports I/O pins shared with peripheral functions
D68HC11 Microcontroller pins
adcdatai
input
Serial ADC data input
adcdatao
output
Serial Data output
adcclock
output
Serial Clock to external ADC
adccs
output
Chip Select to external ADC
Optional external ADC Controller pins
esi
input
eso
output
Serial EEPROM Data input
Serial EEPROM Data output
esck
output
Serial EEPROM Clock
ecs
output
EEPROM Chip Select
Optional external EEPROM controller pins
clkdocd
input
DoCDTM clock input
docddatai
input
DoCDTM serial Data input
docddatao
output
docdclk
output
DoCDTM Serial Clock Output
DoCD debugger interface pins
DoCDTM Serial Data Output
UNITS SUMMARY
Control Unit - Performs the core synchronization and
data flow control. This module manages execution of
all instructions. The Control Unit also manages execution of STOP instruction and waking-up the processor
from the STOP mode.
Opcode Decoder - Performs an instruction opcode
decoding and the control functions for all other
blocks.
ALU - Arithmetic Logic Unit performs the arithmetic
and
logic
operations
during
execution
of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG), Index registers X and
related logic like arithmetic unit, logic unit, multiplier
and divider.
Bus Controller – Program Memory, Data Memory &
SFR’s (Special Function Register) interface controls
access into the program and data memories
and special registers. It contains Program Counter
(PC), Stack Pointer (SP) register, and related logic.
Interrupt Controller –The interrupt requests may
come from external pins (IRQ) as well as from particular peripherals. The D68HC08 peripheral systems
generate maskable interrupts, which are recognized
only if the global interrupt mask bit (I) in the CCR
is cleared. Maskable interrupts are prioritized according to default arrangement, established during reset.
When interrupt condition occurs, an interrupt status
flag is set to indicate the condition.
Timer, Compare Capture & COP Watchdog –
This timer system is based on a free-running 16-bit
counter with a programmable prescaler. A timer
overflow function allows software to extend the
timing capability of the system, beyond the 16-bit
range of the counter. Input-capture function is used
to automatically record the time, when a selected
transition is detected at a respective timer input pin.
Output-compare function is included for generating
output signals, or for timing software delays. Since
the input-capture and output-compare functions may
not be familiar to all users, these concepts are explained in greater detail.
SCI - The SCI is a full-duplex UART type asynchronous
system, using standard, non-return to zero (NRZ)
format: 1 start bit, 8 or 9 data bits and a 1 stop bit.
The D68HC08 resynchronizes the receiver bit clock on
all one to zero transitions in the bit stream. Therefore, the differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the
middle of data bit time and majority logic decides the
sense for the bit. The receiver also has the ability to
enter a temporary standby mode (called receiver
wakeup), to ignore messages intended for a different
receiver. Logic automatically wakes up the receiver in
time to see the first character of the next message.
This wakeup feature greatly reduces CPU overhead in
multi-drop SCI networks. The SCI transmitter can
produce queued characters of idle (whole characters
of all logic 1) and break (whole characters of all logic
0). In addition to the usual transmit data register
empty (TDRE) status flag, this SCI also provides
a transmit complete (TC) indication that can be used
in applications with a modem.
SPI Unit – it’s a fully configurable master/slave Serial
Peripheral Interface, which allows user to configure
polarity and phase of serial clock signal SCK. It allows
the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor
communications, in a multi-master system. A serial
clock line (SCK) synchronizes shifting and sampling of
the information on the two independent serial data
lines. SPI data are simultaneously transmitted and
received. SPI system is flexible enough to interface
directly with numerous standard product peripherals,
from several manufacturers. Clock control logic allows a selection of clock polarity and a choice of two
fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. Error-detection logic is included to
support interprocessor communications. A writecollision detector indicates when an attempt is made
to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers, if
more than one SPI devices simultaneously attempt
to become a bus master.
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
I/O Ports - All ports are 8-bit general-purpose bidirectional I/O system. The ports data registers have
their corresponding data direction registers (DDR), to
control ports data flow. It assures that all D68HC08’s
ports have full I/O selectable registers. Writes to any
ports pins cause data to be stored in the data registers. If any port pins are configured as output, then
data registers are driven out of those pins. Reads
from port pins configured as input, causes the input
pin to be read. If port pins is configured as output,
during read data register is read. Writes to any ports
pins not configured as outputs, does not cause data
to be driven out of those pins, but the data is stored
in the output registers. Thus, if the pins later become
outputs, the last data written to port will be driven
out of the port pins.
options, so its details are described in separate document.
DoCDTM - Debug Unit – it’s a real-time hardware debugger, providing debugging capability of a whole SoC
system. Unlike other on-chip debuggers DoCD™ provides non-intrusive debugging of running application.
It can halt, run, step into or skip an instruction,
read/write any contents of microcontroller, including
all registers, internal, external, program memories
and all SFRs, including user defined peripherals.
Hardware breakpoints can be set and controlled on
program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address,
with certain data pattern or without pattern. The
DoCDTM system includes three-wire interface and
complete set of tools, to communicate and work with
core in real time debugging. It is built as scalable unit
and some features can be turned off by the user, to
save silicon and reduce power consumption. When
debugger is not used, it is automatically switched to
power save mode. Finally, when debug option is no
longer used, whole debugger is turned off. The separate CLKDOCD clock line allows the debugger to operate, while the CPU is in STOP mode and the major
clock line CLK is stopped.
ADCCTRL – External ADC Controller is used
as an interface between D68HC08 internal registers
and external serial/parallel ADC converter.
This module has several different options, so its details are described in separate document.
EEPROMCTRL – External Serial EEPROM controller. It
manages data exchange between D68HC08
and external EEPROM. During initialization, copies
contents of whole external EEPROM, to internal
EEPRAM (EEPROM Mirror implemented in standard
parallel RAM). This module has several different
D68HC11 AND DF6811 MICROCONTROLLERS OVERVIEW
READY for Prg. and
Data memories
Compare\Capture
Main Timer System
-
-
-
-
-
DF6805
4.1
64k
64k
-
-
-
*
1/1*
1*
D68HC05
1.0
64k
64k
-
-
-
*
1/1*
1*
DF6808
3.2
64k
64k
-
-
-
*
2/2*
1*
D68HC08
1.0
64k
64k
-
-
-
*
2/2*
D68HC11E
1.0
64k
64k
-
1*
*
D68HC11F
1.0
64K
64K
-
1*
D68HC11KW1
1.0
1M
1M
1*
D68HC11K
1.0
1M
1M
DF6811E
4.4
64k
64k
-
DF6811F
4.4
64k
64k
-
DF6811K
4.4
1M
1M
-
-
-
-
-
*
4
+
-
6 700
*
4
+
*
-*
-
6 700
*
4
*
-
8 900
1*
*
4
*
-
8 900
5/3*
1*
*
4
12 000
*
5/3*
1*
*
7
13 500
*
13/6*
3*
*
10
21 000
1*
*
5/3*
2*
*
7
16 000
1*
*
5/3*
1*
*
4
*
*
*
12 000
1*
*
5/3*
1*
*
4
*
*
*
13 000
1*
*
5/3*
2*
*
7
Size – ASIC gates
-
DoCD Debugger
Interface for
additional SFRs
Data Pointers
-
Pulse accumulator
Real Time Interrupt
64k
64k
64k
Watchdog Timer
Motorola Memory
Expansion Logic
64k
64k
64k
SPI M/S Interface
Paged Data
Memory space
1
1
1
I\O Ports
Physical Linear
memory space
D6802
D6803
D6809
Design
SCI (UART)
Speed acceleration
The main features of each DF68XX family member have been summarized in the table below. It gives a brief
member characteristic, helping you to select the most suitable IP Core for your application. You can specify
your own peripheral set (including listed above and others) and request the core modifications.
3 900
6 000
9 000
16 000
D68HCXX family of High Performance Microcontroller Cores
+ optional * configurable
4
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
CONTACT
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
5
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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