Application Notes

THAN0146_Rev.1.20_E
Application Note
THAN0146_Rev.1.20_E
THCV226 Application Note
System Diagram and PCB Design Guideline
Copyright© 2015, THine Electronics, Inc.
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Contents
Contents.................................................................................................................................................................. 2
Application Diagrams ........................................................................................................................................... 3
Selection Table .................................................................................................................................................... 3
Normal LVDS Mode / 10bit Mode (RGB 30bit per pixel) / Connected with THCV215 .................................... 4
HSLVDS Mode / 10bit Mode (RGB 30bit per pixel) / Connected with THCV215 ............................................ 5
Normal LVDS with Crossing Mode / 8bit Mode (RGB 24bit per pixel) / Connected with THCV215............... 6
HSLVDS with Crossing Mode / 8bit Mode (RGB 24bit per pixel) / Connected with THCV215 ....................... 7
Normal LVDS with Distribution Mode 1 / 10bit Mode (RGB 30bit per pixel) / Connected with THCV217 ..... 8
HSLVDS with Distribution Mode 1 / 10bit Mode (RGB 30bit per pixel) / Connected with THCV217............. 9
Normal LVDS with Distribution Mode 2 / 8bit Mode (RGB 24bit per pixel) / Connected with THCV217 ..... 10
HSLVDS with Distribution Mode 2 / 8bit Mode (RGB 24bit per pixel) / Connected with THCV217 ............. 11
Recommendations for Power Supply ................................................................................................................. 11
Note ....................................................................................................................................................................... 12
PCB Layout Considerations ............................................................................................................................... 17
Notices and Requests ........................................................................................................................................... 18
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Application Diagrams
Selection Table
THCV226 Transmission Mode
Case1 (See Page4)
Case2 (See Page5)
Normal LVDS Mode
High-speed LVDS Mode
THCV226
THCV226
Rx0n/p
RLy0n/p
10bit Mode : up to 3.4Gbps
Rx1n/p
RLy1n/p 10bit
8bit Mode : up to 2.7Gbps
Rx2n/p
RLy2n/p
Rx3n/p
RLy3n/p
V-by-One® HS
LVDS
Mode : up to 85MHz
8bit Mode : up to 90MHz
V-by-One® HS
Rx0n/p
RLy0n/p
10bit Mode : up to 3.14Gbps Rx1n/p
8bit Mode : up to 2.36Gbps
HSLVDS
RLy1n/p 10bit
Rx2n/p
RLy2n/p
Rx3n/p
RLy3n/p
Mode : up to 157MHz
8bit Mode : up to 157MHz
Case3 (See Page6)
Case4 (See Page7)
Normal LVDS with Crossing Mode
High-speed LVDS with Crossing Mode
THCV226
THCV226
Rx0n/p
RLy0n/p
Rx0n/p
RLy0n/p
10bit Mode : up to 3.4Gbps
Rx1n/p
RLy1n/p
10bit Mode : up to 85MHz
10bit Mode : up to 3.14Gbps Rx1n/p
RLy1n/p
10bit Mode : up to 157MHz
8bit Mode : up to 2.7Gbps
Rx2n/p
RLy2n/p
8bit Mode : up to 90MHz
8bit Mode : up to 2.36Gbps
Rx2n/p
RLy2n/p
8bit Mode : up to 157MHz
Rx3n/p
RLy3n/p
Rx3n/p
RLy3n/p
V-by-One® HS
LVDS
V-by-One® HS
HSLVDS
Case5 (See Page8)
Case6 (See Page9)
Normal LVDS with Distribution Mode 1
High-speed LVDS with Distribution Mode 1
THCV226
THCV226
Rx0n/p
RLy0n/p
10bit Mode : up to 3.4Gbps
Rx1n/p
RLy1n/p
10bit Mode : up to 85MHz
10bit Mode : up to 3.14Gbps Rx1n/p
8bit Mode : up to 2.7Gbps
Rx2n/p
RLy2n/p
8bit Mode : up to 90MHz
8bit Mode : up to 2.36Gbps
Rx3n/p
RLy3n/p
V-by-One® HS
LVDS
V-by-One® HS
Rx0n/p
RLy0n/p
HSLVDS
RLy1n/p 10bit
Rx2n/p
RLy2n/p
Rx3n/p
RLy3n/p
Mode : up to 157MHz
8bit Mode : up to 157MHz
Case7 (See Page10)
Case8 (See Page11)
Normal LVDS with Distribution Mode 2
High-speed LVDS with Distribution Mode 2
THCV226
THCV226
Rx0n/p
RLy0n/p
10bit Mode : up to 3.4Gbps
Rx1n/p
RLy1n/p
10bit Mode : up to 85MHz
10bit Mode : up to 3.14Gbps Rx1n/p
8bit Mode : up to 2.7Gbps
Rx2n/p
RLy2n/p
8bit Mode : up to 90MHz
8bit Mode : up to 2.36Gbps
Rx3n/p
RLy3n/p
V-by-One® HS
LVDS
Copyright© 2015, THine Electronics, Inc.
V-by-One® HS
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Rx0n/p
RLy0n/p
HSLVDS
RLy1n/p 10bit
Rx2n/p
RLy2n/p
Rx3n/p
RLy3n/p
Mode : up to 157MHz
8bit Mode : up to 157MHz
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Application Diagram (Case1)
Normal LVDS Mode / 10bit Mode (RGB 30bit per pixel) / Connected with THCV215
LVDS Driver
THCV215
TLA0TLA0+
TLB0TLB0+
TLC0TLC0+
TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+
TLB1TLB1+
TLC1TLC1+
TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+
PDN = H :
Normal Operation
SDSEL = H :
Dual Channel Enabled
COL1 = H & COL0 = L :
10bit Mode (RGB 30-bit per pixel)
PRE1 = L & PRE0 = L :
No Pre-emphasis
RDY = H indicates Rx is powered up,
and its PLL is locked to the incoming
signals.
VDL
THCV226
VDL
10kΩ
HTPDN
LOCKN
TP
DGLOCK
*4 Open HTPDN
LOCKN
*4
0.1uF
0.1uF
TX0n
TX0p
Rx0n
Rx0p
TX1n
TX1p
Rx1n
Rx1p
10kΩ
TxPDN_0
TxPDN_0
SDSEL_0
COL1_0
VDL
10kΩ
SDSEL_0
PDN
SDSEL
COL1
COL0
PRE1
PRE0
VDL
10kΩ
TP
COL1_0
VDL
VDL DRV0_0
10kΩ
DRV0_0
N.C.
*3
0Ω
RDY
DRV0
DRV1
Reserved0
LVDS Receiver
100Ω
RLA0n
RLA0p
RLB0n
RLB0p
RLC0n
RLC0p
RLCLK0n
RLCLK0p
RLD0n
RLD0p
RLE0n
RLE0p
RLA1n
RLA1p
RLB1n
RLB1p
RLC1n
RLC1p
RLCLK1n
RLCLK1p
RLD1n
RLD1p
RLE1n
RLE1p
RLA2n
RLA2p
RLB2n
RLB2p
RLC2n
RLC2p
RLCLK2n
RLCLK2p
RLD2n
RLD2p
RLE2n
RLE2p
RLA3n
RLA3p
RLB3n
RLB3p
RLC3n
RLC3p
RLCLK3n
RLCLK3p
RLD3n
RLD3p
RLE3n
RLE3p
Reserved1
COL = H :
10bit Mode (RGB 30-bit per pixel)
LVDS Driver
THCV215
TLA0TLA0+
TLB0TLB0+
TLC0TLC0+
TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+
TLB1TLB1+
TLC1TLC1+
TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+
VDL
OPF = H :
LVDS Low Data Output
COL
TxPDN_1
TxPDN_1
SDSEL_1
COL1_1
10kΩ
SDSEL_1
HTPDN
LOCKN
*4
VDL
VDL DRV0_1
10kΩ
DRV0_1
N.C.
*3
0Ω
VDD
RS = H :
LVDS Output Normal Swing
0.1uF
OE
10kΩ
0.1uF
TX0n
TX0p
Rx2n
Rx2p
TX1n
TX1p
Rx3n
Rx3p
BET_SEL0
PDN
SDSEL
COL1
COL0
PRE1
PRE0
RDY
COL
OPF
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
RxPDN
MAP
10kΩ
VDD
BET_EN
Reserved6 Open
Reserved7 Open
TP
BETOUT
Reserved1
N.C.
*3
0Ω
VDD
RxPDN
10kΩ
VDD
BET_LAT
N.C.
0Ω
VDD
VDD
OPF
10kΩ
MON_EN
RS
10kΩ
N.C.
N.C.
0Ω
N.C.
VDD
VDD
DRV0
DRV1
Reserved0
N.C.
0Ω
VDD
COL
OPF
MODE2
MODE1
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
PDN
Reserved0
Reserved1
Reserved2
Reserved3
Reserved4
Reserved5
N.C.
VDD
PDN = H:
Normal Operation
10kΩ
TP
VDD
BET_SEL1
0Ω
MON_EN = L :
Monitoring Mode Disabled
VDL
COL1_1
10kΩ
OE = H :
Normal Operation
10kΩ
VDL
VDD
MODE2 = L & MODE1 = L & MODE0 = L :
Normal LVDS Output Mode
PRBS
N.C.
0Ω
*2
GND
GND
indicates microstrip lines or cables with their differential characteristic impedance being 100Ω .
*1
*2 Connect GNDs of both Tx and Rx PCB.
*3 Field BET operation. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
*4 No HTPDN connection option. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
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Application Diagram (Case2)
HSLVDS Mode / 10bit Mode (RGB 30bit per pixel) / Connected with THCV215
LVDS Driver
THCV215
TLA0TLA0+
TLB0TLB0+
TLC0TLC0+
TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+
TLB1TLB1+
TLC1TLC1+
TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+
PDN = H :
Normal Operation
SDSEL = H :
Dual Channel Enabled
COL1 = H & COL0 = L :
10bit Mode (RGB 30-bit per pixel)
PRE1 = L & PRE0 = L :
No Pre-emphasis
RDY = H indicates Rx is powered up,
and its PLL is locked to the incoming
signals.
VDL
THCV226
VDL
10kΩ
HTPDN
LOCKN
TP
DGLOCK
*4 Open HTPDN
LOCKN
*4
0.1uF
0.1uF
TX0n
TX0p
Rx0n
Rx0p
TX1n
TX1p
Rx1n
Rx1p
10kΩ
TxPDN_0
TxPDN_0
SDSEL_0
COL1_0
VDL
10kΩ
SDSEL_0
PDN
SDSEL
COL1
COL0
PRE1
PRE0
VDL
10kΩ
TP
COL1_0
VDL
VDL DRV0_0
10kΩ
DRV0_0
N.C.
*3
0Ω
RDY
DRV0
DRV1
Reserved0
RLA0n
RLA0p
RLB0n
RLB0p
RLC0n
RLC0p
RLCLK0n
RLCLK0p
RLD0n
RLD0p
RLE0n
RLE0p
RLA1n
RLA1p
RLB1n
RLB1p
RLC1n
RLC1p
RLCLK1n
RLCLK1p
RLD1n
RLD1p
RLE1n
RLE1p
RLA2n
RLA2p
RLB2n
RLB2p
RLC2n
RLC2p
RLCLK2n
RLCLK2p
RLD2n
RLD2p
RLE2n
RLE2p
RLA3n
RLA3p
RLB3n
RLB3p
RLC3n
RLC3p
RLCLK3n
RLCLK3p
RLD3n
RLD3p
RLE3n
RLE3p
LVDS Receiver
Open
Open
Open
Open
Open
Open
100Ω
Open
Open
Open
Open
Open
Open
Reserved1
VDD
COL = H :
10bit Mode (RGB 30-bit per pixel)
LVDS Driver
THCV215
TLA0TLA0+
TLB0TLB0+
TLC0TLC0+
TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+
TLB1TLB1+
TLC1TLC1+
TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+
VDL
MODE0
OPF = H :
LVDS Low Data Output
MODE2 = L & MODE1 = L & MODE0 = H :
HSLVDS Output Mode
COL
TxPDN_1
TxPDN_1
SDSEL_1
COL1_1
10kΩ
SDSEL_1
HTPDN
LOCKN
*4
VDL
VDL DRV0_1
10kΩ
DRV0_1
N.C.
*3
0Ω
BET_SEL1
VDD
RS = H :
LVDS Output Normal Swing
0.1uF
OE
10kΩ
VDD
BET_SEL0
0.1uF
TX0n
TX0p
Rx2n
Rx2p
TX1n
TX1p
Rx3n
Rx3p
PDN
SDSEL
COL1
COL0
PRE1
PRE0
RDY
VDD
COL
OPF
MODE2
MODE1
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
PDN
Reserved0
Reserved1
Reserved2
Reserved3
Reserved4
Reserved5
COL
OPF
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
RxPDN
MAP
10kΩ
VDD
BET_EN
Reserved6 Open
Reserved7 Open
TP
BETOUT
Reserved1
N.C.
*3
0Ω
VDD
RxPDN
10kΩ
VDD
BET_LAT
N.C.
0Ω
VDD
VDD
OPF
10kΩ
MON_EN
RS
10kΩ
N.C.
N.C.
0Ω
N.C.
VDD
VDD
DRV0
DRV1
Reserved0
N.C.
0Ω
PDN = H:
Normal Operation
10kΩ
TP
VDD
N.C.
0Ω
MON_EN = L :
Monitoring Mode Disabled
VDL
COL1_1
10kΩ
OE = H :
Normal Operation
10kΩ
VDL
VDD
10kΩ
PRBS
N.C.
0Ω
*2
GND
GND
indicates microstrip lines or cables with their differential characteristic impedance being 100Ω .
*1
*2 Connect GNDs of both Tx and Rx PCB.
*3 Field BET operation. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
*4 No HTPDN connection option. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
Application Diagram (Case3)
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Normal LVDS with Crossing Mode / 8bit Mode (RGB 24bit per pixel) / Connected with THCV215
LVDS Driver
THCV215
TLA0TLA0+
TLB0TLB0+
TLC0TLC0+
TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+
TLB1TLB1+
TLC1TLC1+
TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+
PDN = H :
Normal Operation
SDSEL = H :
Dual Channel Enabled
COL1 = L & COL0 = H :
8bit Mode (RGB 24-bit per pixel)
PRE1 = L & PRE0 = L :
No Pre-emphasis
RDY = H indicates Rx is powered up,
And its PLL is locked to the incoming
signals.
VDL
THCV226
VDL
10kΩ
HTPDN
LOCKN
TP
DGLOCK
*4 Open HTPDN
LOCKN
*4
0.1uF
0.1uF
TX0n
TX0p
Rx0n
Rx0p
TX1n
TX1p
Rx1n
Rx1p
10kΩ
TxPDN_0
TxPDN_0
SDSEL_0
COL0_0
VDL
10kΩ
SDSEL_0
PDN
SDSEL
COL0
COL1
PRE1
PRE0
VDL
10kΩ
TP
COL0_0
VDL
10kΩ
DRV0_0
RDY
DRV1
DRV0
Reserved0
VDL DRV0_0
N.C.
*3
0Ω
RLA0n
RLA0p
RLB0n
RLB0p
RLC0n
RLC0p
RLCLK0n
RLCLK0p
RLD0n
RLD0p
RLE0n
RLE0p
RLA1n
RLA1p
RLB1n
RLB1p
RLC1n
RLC1p
RLCLK1n
RLCLK1p
RLD1n
RLD1p
RLE1n
RLE1p
RLA2n
RLA2p
RLB2n
RLB2p
RLC2n
RLC2p
RLCLK2n
RLCLK2p
RLD2n
RLD2p
RLE2n
RLE2p
RLA3n
RLA3p
RLB3n
RLB3p
RLC3n
RLC3p
RLCLK3n
RLCLK3p
RLD3n
RLD3p
RLE3n
RLE3p
LVDS Receiver
100Ω
Open
Open
Open
Open
Reserved1
VDD
LVDS Driver
COL = L :
8bit Mode (RGB 24-bit per pixel)
THCV215
TLA0TLA0+
TLB0TLB0+
TLC0TLC0+
TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+
TLB1TLB1+
TLC1TLC1+
TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+
VDL
TxPDN_1
TxPDN_1
SDSEL_1
COL0_1
10kΩ
SDSEL_1
*4
VDL
VDL DRV0_1
10kΩ
DRV0_1
N.C.
*3
0Ω
10kΩ
VDD
BET_SEL1
N.C.
0Ω
MON_EN = L :
Monitoring Mode Disabled
VDD
RS = H :
LVDS Output Normal Swing
OE
10kΩ
VDD
BET_SEL0
N.C.
0Ω
0.1uF
PDN = H:
Normal Operation
0.1uF
TX0n
TX0p
Rx2n
Rx2p
TX1n
TX1p
Rx3n
Rx3p
PDN
SDSEL
COL0
COL1
PRE1
PRE0
10kΩ
TP
COL
OE = H :
Normal Operation
HTPDN
LOCKN
VDL
COL0_1
VDD
MODE2 = L & MODE1 = H & MODE0 = L :
Normal LVDS Output with Crossing Mode
10kΩ
VDL
MODE1
OPF = H :
LVDS Low Data Output
10kΩ
RDY
VDD
COL
OPF
MODE2
MODE1
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
PDN
Reserved0
Reserved1
Reserved2
Reserved3
Reserved4
Reserved5
COL
OPF
MAP
10kΩ
VDD
BET_EN
Reserved6 Open
Reserved7 Open
TP
BETOUT
Reserved1
*3
0Ω
MODE1
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
RxPDN
VDD
RxPDN
10kΩ
VDD
BET_LAT
N.C.
0Ω
VDD
VDD
OPF
10kΩ
MON_EN
RS
10kΩ
N.C.
N.C.
0Ω
N.C.
VDD
VDD
DRV0
DRV1
Reserved0
N.C.
PRBS
N.C.
0Ω
*2
GND
GND
indicates microstrip lines or cables with their differential characteristic impedance being 100Ω .
*1
*2 Connect GNDs of both Tx and Rx PCB.
*3 Field BET operation. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
*4 No HTPDN connection option. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
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Application Diagram (Case4)
HSLVDS with Crossing Mode / 8bit Mode (RGB 24bit per pixel) / Connected with THCV215
LVDS Driver
THCV215
TLA0TLA0+
TLB0TLB0+
TLC0TLC0+
TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+
TLB1TLB1+
TLC1TLC1+
TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+
PDN = H :
Normal Operation
SDSEL = H :
Dual Channel Enabled
COL1 = L & COL0 = H :
8bit Mode (RGB 24-bit per pixel)
PRE1 = L & PRE0 = L :
No Pre-emphasis
RDY = H indicates Rx is powered up,
And its PLL is locked to the incoming
signals.
VDL
THCV226
VDL
10kΩ
HTPDN
LOCKN
TP
DGLOCK
*4 Open HTPDN
LOCKN
*4
0.1uF
0.1uF
TX0n
TX0p
Rx0n
Rx0p
TX1n
TX1p
Rx1n
Rx1p
10kΩ
TxPDN_0
TxPDN_0
SDSEL_0
COL0_0
VDL
10kΩ
SDSEL_0
PDN
SDSEL
COL0
COL1
PRE1
PRE0
VDL
10kΩ
TP
COL0_0
VDL
VDL DRV0_0
10kΩ
DRV0_0
N.C.
*3
0Ω
RDY
DRV1
DRV0
Reserved0
RLA0n
RLA0p
RLB0n
RLB0p
RLC0n
RLC0p
RLCLK0n
RLCLK0p
RLD0n
RLD0p
RLE0n
RLE0p
RLA1n
RLA1p
RLB1n
RLB1p
RLC1n
RLC1p
RLCLK1n
RLCLK1p
RLD1n
RLD1p
RLE1n
RLE1p
RLA2n
RLA2p
RLB2n
RLB2p
RLC2n
RLC2p
RLCLK2n
RLCLK2p
RLD2n
RLD2p
RLE2n
RLE2p
RLA3n
RLA3p
RLB3n
RLB3p
RLC3n
RLC3p
RLCLK3n
RLCLK3p
RLD3n
RLD3p
RLE3n
RLE3p
LVDS Receiver
Open
Open
Open
Open
Open
Open
100Ω
Open
Open
Open
Open
Open
Open
Open
Open
Reserved1
LVDS Driver
THCV215
TLA0TLA0+
TLB0TLB0+
TLC0TLC0+
TLCLK0TLCLK0+
TLD0TLD0+
TLE0TLE0+
TLF0TLF0+
TLA1TLA1+
TLB1TLB1+
TLC1TLC1+
TLCLK1TLCLK1+
TLD1TLD1+
TLE1TLE1+
TLF1TLF1+
VDL
TxPDN_1
TxPDN_1
SDSEL_1
COL0_1
10kΩ
SDSEL_1
VDL
VDL DRV0_1
10kΩ
DRV0_1
N.C.
*3
0Ω
MODE0
COL
10kΩ
HTPDN
LOCKN
*4
BET_SEL1
VDD
RS = H :
LVDS Output Normal Swing
0.1uF
OE
10kΩ
VDD
BET_SEL0
Rx2n
Rx2p
TX1n
TX1p
Rx3n
Rx3p
PDN
SDSEL
COL0
COL1
PRE1
PRE0
RDY
VDD
COL
OPF
MODE2
MODE1
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
PDN
Reserved0
Reserved1
Reserved2
Reserved3
Reserved4
Reserved5
COL
OPF
MODE1
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
RxPDN
MAP
10kΩ
VDD
BET_EN
Reserved6 Open
Reserved7 Open
TP
BETOUT
Reserved1
N.C.
*3
0Ω
VDD
RxPDN
10kΩ
VDD
BET_LAT
N.C.
0Ω
VDD
VDD
OPF
10kΩ
MON_EN
RS
10kΩ
N.C.
N.C.
0Ω
N.C.
VDD
VDD
DRV0
DRV1
Reserved0
N.C.
0Ω
PDN = H:
Normal Operation
0.1uF
N.C.
0Ω
MON_EN = L :
Monitoring Mode Disabled
TX0n
TX0p
10kΩ
VDD
OE = H :
Normal Operation
10kΩ
COL0_1
10kΩ
VDD
MODE2 = L & MODE1 = H & MODE0 = H :
HSLVDS Output with Crossing Mode
VDL
TP
MODE1
OPF = H :
LVDS Low Data Output
10kΩ
VDL
VDD
VDD
COL = L :
8bit Mode (RGB 24-bit per pixel)
PRBS
N.C.
0Ω
*2
GND
GND
indicates microstrip lines or cables with their differential characteristic impedance being 100Ω .
*1
*2 Connect GNDs of both Tx and Rx PCB.
*3 Field BET operation. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
*4 No HTPDN connection option. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
Copyright© 2015, THine Electronics, Inc.
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Security E
THAN0146_Rev.1.20_E
Application Diagram (Case5)
Normal LVDS with Distribution Mode 1 / 10bit Mode (RGB 30bit per pixel) / Connected with THCV217
CMOS Driver
THCV217
THCV226
R19-R10
G19-10
3.3V
B19-10
10kΩ
CONT11,12
R29-R20
HTPDN
LOCKN
TP
DGLOCK
*4 Open HTPDN
LOCKN
*4
G29-20
B29-20
0.1uF
0.1uF
CONT21,22
TX0n
TX0p
Rx0n
Rx0p
DE, H/VSYNC
TX1n
TX1p
Rx1n
Rx1p
CLKIN
RLA0n
RLA0p
RLB0n
RLB0p
RLC0n
RLC0p
RLCLK0n
RLCLK0p
RLD0n
RLD0p
RLE0n
RLE0p
RLA1n
RLA1p
RLB1n
RLB1p
RLC1n
RLC1p
RLCLK1n
RLCLK1p
RLD1n
RLD1p
RLE1n
RLE1p
LVDS Receiver
100Ω
LVDS Receiver
3.3V
RLA2n
RLA2p
RLB2n
RLB2p
RLC2n
RLC2p
RLCLK2n
RLCLK2p
RLD2n
RLD2p
RLE2n
RLE2p
RLA3n
RLA3p
RLB3n
RLB3p
RLC3n
RLC3p
RLCLK3n
RLCLK3p
RLD3n
RLD3p
RLE3n
RLE3p
3.3V
10kΩ
10kΩ
TxPDN
R/F
TxPDN
R/F
COL = L :
10bit Mode (RGB 30-bit per pixel)
PDN
R/F
COL
DEMUX
MODE
PRE
Reserved0
DEMUX = L & MODE = L
Dual-in / Dual-out
PRE = L
Pre-emphasis 0%
3.3V
BET = L :
Normal Mode
PDN = H :
Normal Operation
R/F = H :
Clock’s Rising Edge
N.C.
*3
BET
0Ω
VDD
COL = H :
10bit Mode (RGB 30-bit per pixel)
MODE2
OPF = H :
LVDS Low Data Output
VDD
MODE2 = H & MODE1 = L & MODE0 = L :
Normal LVDS Output with Distribution Mode 1
COL
10kΩ
VDD
BET_SEL1
VDD
MON_EN = L :
Monitoring Mode Disabled
Open Rx3n
or GND Rx3p
OE
RS = H :
LVDS Output Normal Swing
10kΩ
VDD
BET_SEL0
0Ω
VDD
COL
OPF
MODE2
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
RxPDN
MAP
10kΩ
VDD
BET_EN
N.C.
*3
0Ω
VDD
RxPDN
10kΩ
VDD
BET_LAT
N.C.
0Ω
VDD
VDD
OPF
10kΩ
MON_EN
RS
10kΩ
N.C.
N.C.
0Ω
N.C.
VDD
VDD
Reserved6 Open
Reserved7 Open
TP
BETOUT
*2
N.C.
PDN = H:
Normal Operation
COL
OPF
MODE2
MODE1
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
PDN
Reserved0
Reserved1
Reserved2
Reserved3
Reserved4
Reserved5
GND
N.C.
0Ω
OE = H :
Normal Operation
Open Rx2n
or GND Rx2p
10kΩ
PRBS
N.C.
0Ω
GND
indicates microstrip lines or cables with their differential characteristic impedance being 100Ω .
*1
*2 Connect GNDs of both Tx and Rx PCB.
*3 Field BET operation. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
*4 No HTPDN connection option. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
Copyright© 2015, THine Electronics, Inc.
8/18
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THAN0146_Rev.1.20_E
Application Diagram (Case6)
HSLVDS with Distribution Mode 1 / 10bit Mode (RGB 30bit per pixel) / Connected with THCV217
CMOS Driver
THCV217
RLA0n
RLA0p
RLB0n
RLB0p
RLC0n
RLC0p
RLCLK0n
RLCLK0p
RLD0n
RLD0p
RLE0n
RLE0p
G19-10
3.3V
B19-10
10kΩ
CONT11,12
R29-R20
100Ω LVDS Receiver
THCV226
R19-R10
HTPDN
LOCKN
TP
DGLOCK
*4 Open HTPDN
LOCKN
*4
LVDS Receiver
G29-20
RLA1n
RLA1p
RLB1n
RLB1p
RLC1n
RLC1p
RLCLK1n
RLCLK1p
RLD1n
RLD1p
RLE1n
RLE1p
B29-20
0.1uF
0.1uF
CONT21,22
TX0n
TX0p
Rx0n
Rx0p
DE, H/VSYNC
TX1n
TX1p
Rx1n
Rx1p
CLKIN
LVDS Receiver
3.3V
RLA2n
RLA2p
RLB2n
RLB2p
RLC2n
RLC2p
RLCLK2n
RLCLK2p
RLD2n
RLD2p
RLE2n
RLE2p
3.3V
10kΩ
10kΩ
TxPDN_0
R/F_0
TxPDN_0
R/F_0
COL = L :
10bit Mode (RGB 30-bit per pixel)
PDN
R/F
COL
DEMUX
MODE
PRE
Reserved0
DEMUX = L & MODE = L
Dual-in / Dual-out
LVDS Receiver
PRE = L
Pre-emphasis 0%
RLA3n
RLA3p
RLB3n
RLB3p
RLC3n
RLC3p
RLCLK3n
RLCLK3p
RLD3n
RLD3p
RLE3n
RLE3p
3.3V
BET = L :
Normal Mode
N.C.
PDN = H :
Normal Operation
*3
BET
0Ω
R/F = H :
Clock’s Rising Edge
CMOS Driver
THCV217
G19-10
CONT11,12
HTPDN
LOCKN
*4
COL
10kΩ
MODE0
BET_SEL1
0.1uF
0.1uF
Rx2n
Rx2p
TX1n
TX1p
Rx3n
Rx3p
N.C.
0Ω
VDD
MON_EN = L :
Monitoring Mode Disabled
TX0n
TX0p
10kΩ
VDD
OE = H :
Normal Operation
B29-20
DE, H/VSYNC
10kΩ
VDD
MODE2 = H & MODE1 = L & MODE0 = H :
HSLVDS Output with Distribution Mode 1
G29-20
CONT21,22
MODE1
OPF = H :
LVDS Low Data Output
B19-10
R29-R20
VDD
VDD
COL = H :
10bit Mode (RGB 30-bit per pixel)
R19-R10
OE
RS = H :
LVDS Output Normal Swing
10kΩ
VDD
BET_SEL0
N.C.
0Ω
PDN = H:
Normal Operation
VDD
VDD
CLKIN
3.3V
10kΩ
COL
OPF
MODE2
MODE1
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
PDN
Reserved0
Reserved1
Reserved2
Reserved3
Reserved4
Reserved5
3.3V
TxPDN_1
10kΩ
R/F_1
TxPDN_1
R/F_1
PDN
R/F
COL
DEMUX
MODE
PRE
Reserved0
3.3V
COL
OPF
MODE2
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
RxPDN
MAP
BET_EN
VDD
RxPDN
10kΩ
Reserved6 Open
Reserved7 Open
TP
BETOUT
*2
N.C.
0Ω
VDD
VDD
OPF
10kΩ
MON_EN
RS
10kΩ
N.C.
0Ω
N.C.
N.C.
GND
*3
VDD
BET_LAT
VDD
VDD
BET
0Ω
N.C.
0Ω
N.C.
*3
10kΩ
PRBS
N.C.
0Ω
GND
indicates microstrip lines or cables with their differential characteristic impedance being 100Ω .
*1
*2 Connect GNDs of both Tx and Rx PCB.
*3 Field BET operation. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
*4 No HTPDN connection option. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
Copyright© 2015, THine Electronics, Inc.
9/18
THine Electronics, Inc.
Security E
THAN0146_Rev.1.20_E
Application Diagram (Case7)
Normal LVDS with Distribution Mode 2 / 8bit Mode (RGB 24bit per pixel) / Connected with THCV217
THCV226
3.3V
10kΩ
TP
DGLOCK
*4 Open HTPDN
LOCKN
Open Rx0n
or GND Rx0p
Open Rx1n
or GND Rx1p
RLA0n
RLA0p
RLB0n
RLB0p
RLC0n
RLC0p
RLCLK0n
RLCLK0p
RLD0n
RLD0p
RLE0n
RLE0p
RLA1n
RLA1p
RLB1n
RLB1p
RLC1n
RLC1p
RLCLK1n
RLCLK1p
RLD1n
RLD1p
RLE1n
RLE1p
LVDS Receiver
100Ω
Open
Open
LVDS Receiver
RLA2n
RLA2p
RLB2n
RLB2p
RLC2n
RLC2p
RLCLK2n
RLCLK2p
RLD2n
RLD2p
RLE2n
RLE2p
RLA3n
RLA3p
RLB3n
RLB3p
RLC3n
RLC3p
RLCLK3n
RLCLK3p
RLD3n
RLD3p
RLE3n
RLE3p
COL = H :
8bit Mode (RGB 24-bit per pixel)
DEMUX = L & MODE = L
Dual-in / Dual-out
PRE = L
Pre-emphasis 0%
BET = L :
Normal Mode
PDN = H :
Normal Operation
Open
Open
R/F = H :
Clock’s Rising Edge
CMOS Driver
THCV217
R29-R22
R21-R20
G29-22
G21-20
B29-22
B21-20
CONT21,22
DE, H/VSYNC
COL = L :
8bit Mode (RGB 24-bit per pixel)
MODE2
OPF = H :
LVDS Low Data Output
HTPDN
LOCKN
*4
COL
0.1uF
0.1uF
Rx2n
Rx2p
TX1n
TX1p
Rx3n
Rx3p
TxPDN
R/F
COL
PDN
R/F
COL
DEMUX
MODE
PRE
Reserved0
3.3V
10kΩ
R/F
3.3V
10kΩ
3.3V
COL
VDD
BET_SEL1
VDD
OE
10kΩ
VDD
BET_SEL0
0Ω
VDD
Reserved6 Open
Reserved7 Open
BETOUT
TP
*2
COL
OPF
MODE2
MODE1
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
RxPDN
MAP
10kΩ
VDD
BET_EN
N.C.
*3
0Ω
VDD
RxPDN
10kΩ
VDD
BET_LAT
N.C.
0Ω
VDD
VDD
OPF
10kΩ
MON_EN
N.C.
RS
10kΩ
N.C.
GND
N.C.
0Ω
N.C.
0Ω
VDD
VDD
BET
N.C.
PDN = H:
Normal Operation
N.C.
*3
10kΩ
10kΩ
0Ω
RS = H :
LVDS Output Normal Swing
COL
OPF
MODE2
MODE1
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
PDN
Reserved0
Reserved1
Reserved2
Reserved3
Reserved4
Reserved5
3.3V
TxPDN
MODE1
OE = H :
Normal Operation
MON_EN = L :
Monitoring Mode Disabled
TX0n
TX0p
10kΩ
VDD
MODE2 = H & MODE1 = H & MODE0 = L :
Normal LVDS Output with Distribution Mode 2
CLKIN
10kΩ
VDD
VDD
R19-R12
R11-R10
G19-12
G11-10
B19-12
B11-10
CONT11,12
PRBS
N.C.
0Ω
GND
indicates microstrip lines or cables with their differential characteristic impedance being 100Ω .
*1
*2 Connect GNDs of both Tx and Rx PCB.
*3 Field BET operation. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
*4 No HTPDN connection option. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
Copyright© 2015, THine Electronics, Inc.
10/18
THine Electronics, Inc.
Security E
THAN0146_Rev.1.20_E
Application Diagram (Case8)
HSLVDS with Distribution Mode 2 / 8bit Mode (RGB 24bit per pixel) / Connected with THCV217
CMOS Driver
THCV217
R19-R12
R11-R10
G19-12
G11-10
B19-12
B11-10
CONT11,12
3.3V
10kΩ
TP
DGLOCK
*4 Open HTPDN
LOCKN
*4
HTPDN
LOCKN
R29-R22
R21-R20
G29-22
G21-20
B29-22
B21-20
CONT21,22
100Ω LVDS Receiver
THCV226
RLA0n
RLA0p
RLB0n
RLB0p
RLC0n
RLC0p
RLCLK0n
RLCLK0p
RLD0n
RLD0p
RLE0n
RLE0p
Open
LVDS Receiver
0.1uF
DE, H/VSYNC
0.1uF
TX0n
TX0p
Rx0n
Rx0p
TX1n
TX1p
Rx1n
Rx1p
CLKIN
RLA1n
RLA1p
RLB1n
RLB1p
RLC1n
RLC1p
RLCLK1n
RLCLK1p
RLD1n
RLD1p
RLE1n
RLE1p
Open
LVDS Receiver
TxPDN_0
R/F_0
COL_0
3.3V
10kΩ
TxPDN_0
PDN
R/F
COL
DEMUX
MODE
PRE
Reserved0
DEMUX = L & MODE = L
Dual-in / Dual-out
R/F_0
LVDS Receiver
3.3V
RLA3n
RLA3p
RLB3n
RLB3p
RLC3n
RLC3p
RLCLK3n
RLCLK3p
RLD3n
RLD3p
RLE3n
RLE3p
PDN = H :
Normal Operation
N.C.
COL_0
Open
BET = L :
Normal Mode
3.3V
10kΩ
COL = H :
8bit Mode (RGB 24-bit per pixel)
PRE = L
Pre-emphasis 0%
3.3V
10kΩ
RLA2n
RLA2p
RLB2n
RLB2p
RLC2n
RLC2p
RLCLK2n
RLCLK2p
RLD2n
RLD2p
RLE2n
RLE2p
*3
R/F = H :
Clock’s Rising Edge
BET
0Ω
CMOS Driver
VDD
Open
MODE2
THCV217
R19-R12
R11-R10
G19-12
G11-10
B19-12
B11-10
CONT11,12
R29-R22
R21-R20
G29-22
G21-20
B29-22
B21-20
CONT21,22
DE, H/VSYNC
VDD
VDD
COL = L :
8bit Mode (RGB 24-bit per pixel)
MODE1
OPF = H :
LVDS Low Data Output
MODE0
VDD
MODE2 = H & MODE1 = H & MODE0 = H :
HSLVDS Output with Distribution Mode 2
*4
HTPDN
LOCKN
10kΩ
COL
10kΩ
BET_SEL1
TX0n
TX0p
Rx2n
Rx2p
TX1n
TX1p
Rx3n
Rx3p
N.C.
0Ω
VDD
MON_EN = L :
Monitoring Mode Disabled
0.1uF
10kΩ
VDD
OE = H :
Normal Operation
0.1uF
10kΩ
OE
RS = H :
LVDS Output Normal Swing
10kΩ
VDD
BET_SEL0
N.C.
0Ω
PDN = H:
Normal Operation
VDD
VDD
CLKIN
3.3V
10kΩ
TxPDN_1
TxPDN_1
R/F_1
COL_1
3.3V
10kΩ
COL
OPF
MODE2
MODE1
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
PDN
Reserved0
Reserved1
Reserved2
Reserved3
Reserved4
Reserved5
PDN
R/F
COL
DEMUX
MODE
PRE
Reserved0
R/F_1
3.3V
3.3V
10kΩ
COL_1
N.C.
*3
COL
OPF
MODE2
MODE1
MODE0
OE
BET_SEL1
BET_SEL0
BET_EN
BET_LAT
MON_EN
PRBS
RS
MAP
RxPDN
MAP
10kΩ
BET_EN
VDD
RxPDN
10kΩ
VDD
BET_LAT
VDD
VDD
OPF
10kΩ
MON_EN
N.C.
RS
10kΩ
N.C.
N.C.
0Ω
VDD
VDD
GND
N.C.
0Ω
BET
*2
*3
0Ω
0Ω
Reserved6 Open
Reserved7 Open
BETOUT
TP
N.C.
PRBS
N.C.
0Ω
GND
indicates microstrip lines or cables with their differential characteristic impedance being 100Ω .
*1
*2 Connect GNDs of both Tx and Rx PCB.
*3 Field BET operation. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
*4 No HTPDN connection option. Please refer to the datasheet for details. (THCV226_Rev.*.**_E.pdf)
Recommendations for Power Supply
Copyright© 2015, THine Electronics, Inc.
11/18
THine Electronics, Inc.
Security E
THAN0146_Rev.1.20_E



Separate the power domains into VVDD, LVDD(/LPVDD), CVDD(/IOVDD), and PVDD in order to avoid
unwanted noise coupling between noisy digital and sensitive analog domains.
Use high frequency ceramic capacitors of 10nF or 0.1μF as bypass capacitors between power and ground
pins. Place them as close to each power pin as possible.
Adding 4.7μF capacitors to PLL's power pins including V-by-One® HS power domain, along with the
smaller bypass capacitors, is recommended.
Recommended Power Supply for THCV226
Ferrite bead
10nF
10nF
10nF
10nF
10nF
VVDD
10nF
1.8V
10uF
LVDD
GND
CVDD
GND
LVDD
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
GND
CVDD/IOVDD
10nF
IOVDD
10nF
CVDD
GND
VVDD
10uF
Ferrite bead
GND
LVDD
LVDD/LPVDD
10uF
Ferrite bead
GND
LVDD
CVDD
GND
GND
GND
Ferrite bead
GND
PVDD
10nF
4.7uF
10uF
GND
GND
10nF
VVDD
GND
GND
4.7uF
10nF
10nF
VVDD
GND
CVDD
GND
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
THCV226
TQFP 128Pin
LVDD
GND
LPVDD
GND
LPVDD
GND
LVDD
GND
10nF
4.7uF
10nF
4.7uF
10nF
10nF
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LVDD
GND
CVDD
GND
LVDD
GND
LVDD
GND
LVDD
PVDD
CVDD
IOVDD
GND
10nF
10nF
10nF
10nF
10nF
10nF
4.7uF
10nF
10nF
VVDD
LVDD/LPVDD
CVDD/IOVDD
PVDD
GND
Note
1) LVDS Output Pin Connection
In case that the LVDS Rx of destination device is equipped with pull-up resistors connected to higher than
THCV226’s VDD voltage, this can cause violation of absolute maximum ratings to THCV226. This
phenomenon may be happened at power-on phase and Hi-Z state of the whole system including LVDS Rx
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device.
One solution for this problem is power-down control for LVDS Rx device during no LVDS input or Hi-Z state
period, if its pull-up resistors can be cut off at power-down state. Another solution is to set THCV226’s OPF
option pin to VDD. This setting provides low fixed data output mode at PDN = H, not Hi-Z state mode.
THCV226 LVDS Tx
LVDS Rx
VDD
-
VDD VDD
+
VDD_RxVDD_Rx
Termination
Resistor
100Ω
TXp
RXp
TXn
RXn
+
-
-
+
GND
VDD = 1.62V to 1.98V
GND GND
VDD_Rx > VDD (Ex. 2.5V / 3.3V)
2) Cable Connection and Disconnection
Do Not connect and disconnect the LVDS and CML cable, when the power is supplied to the system.
3) GND Connection
Connect the each GND of the PCB which Transmitter and THCV226 on it.
place GND cable as close to LVDS and CML cable as possible.
It is better for EMI reduction to
4) Multi-drop Connection
Multi-drop connection is not recommended.
RLy0n/p
RLy1n/p
THCV226
LVDS Rx
RLy2n/p
RLy3n/p
LVDS Rx
y = A, B, C, CLK, D, E
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5) Multiple Counterpart Use
Multiple counterpart use such as the following system is not recommended. If it is not avoidable, please check
whether tRISK and tRIJT spec of THCV226 can be kept or not. Furthermore, please contact to
[email protected]
(for FAE mailing list)
CLKOUT
DATA
Tx0n/p
V-by-One® Tx
IC CLKOUT
DATA
Tx1n/p
THCV226
Tx2n/p
V-by-One® Tx
Tx3n/p
6) Multiple Device Connection
HTPDN and LOCKN signals are supposed to be connected properly for their purpose like the following figure.
HTPDN should be from just one THCV226 to multiple Tx devices because its purpose is only ignition of all Tx
devices. LOCKN should be connected so as to indicate that CDR status of all Rx devices becomes ready to
receive normal operation data. LOCKN of Tx side can be simply split to multiple Tx devices. THCV226’s
DGLOCK is appropriate for multiple Rx use.
Also possible time difference of internal processing time (THCV226 tRDC) on multiple data stream must be
accommodated and compensated by the following destination device connected to multiple THCV226 chips,
which may have internal FIFO.
Source
Device
THCV226
clkout.1
HTPDN
HTPDN
clkout.2
LOCKN
LOCKN
clkout.3
DGLOCK
clkout.4
FIFO
clkin
Time diff. comes up
THCV226
Destination
Device
clkout.1
HTPDN
clkout.2
LOCKN
clkout.3
DGLOCK
clkout.4
FIFO
Internal processing time tRDC
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clkin.1
Source
Device 1
THCV226
HTPDN
HTPDN
clkout.2
LOCKN
LOCKN
clkout.3
DGLOCK
clkout.4
Ex. synchronized
Time diff. comes up
Source
Device 2
clkin.2
clkout.1
THCV226
FIFO
Destination
Device
clkout.1
HTPDN
HTPDN
clkout.2
LOCKN
LOCKN
clkout.3
DGLOCK
clkout.4
FIFO
Internal processing time tRDC
7) LVDS Link Skew Consideration
Single Chip Case in use of Only One Clock Signal out of LVDS Channels :
Let tRCOP = 13.47ns (74.25MHz) at normal LVDS mode.
As a result, the total amount of LVDS skew, tROP1, is calculated as +/- 750ps in use of only one clock signal
out of LVDS channels for the connection between THCV226 and destination device.
RLCLK0p/n
THCV226
RLy0p/n
Destination
Device
RLy1p/n
RLy2p/n
RLy3p/n
y = A, B, C, D, E
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tROP1 Min = -250ps
RLCLK0p/n
RLy0p/n
RLy0_2
RLy0_1
RLy0_0
RLy0_6
RLy0_5
RLy0_4
RLy0_3
RLy0_2
RLy0_3
RLCLK1p/n
RLy1p/n
RLy1_3
RLy1_2
RLy1_1
RLy1_0
RLy1_6
RLy1_5
RLy1_4
RLy1_3
RLy1_2
RLy2_3
RLy2_2
RLy2_1
RLy2_0
RLy2_6
RLy2_5
RLy2_4
RLy2_3
RLy2_2
RLCLK2p/n
RLy2p/n
RLCLK3p/n
RLy3p/n
RLy3_3
RLy3_2
RLy3_1
RLy3_0
RLy3_6
RLy3_5
RLy3_4
RLy3_3
RLy3_2
y = A, B, C, D, E
Δ tROSK Max = 500ps
tROP1 Max = +250ps from RLCLK3p/n
tROP1 Max = +750ps from RLCLK1p/n
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PCB Layout Considerations







Use at least four-layer PCBs with signals, ground, power, and signals assigned for each layer. (Refer to
figure below.)
PCB traces for high-speed signals must be single-ended micorstirp lines or coupled microstrip lines whose
differential characteristic impedance is 100Ω.
Minimize the distance between traces of a differential pair (S1) to maximize common mode rejection and
coupling effect which works to reduce EMI(Electro-Magnetic Interference).
Route differential signal traces symmetrically.
Avoid right-angle turns or minimize the number of vias on the high speed traces because they usually cause
impedance discontinuity in the transmission lines and degrade the signal integrity.
Mismatch among impedances of PCB traces, connectors, or cables, also causes reflection, limiting the
bandwidth of the high-speed channels.
Using common-mode filter on differential traces is desirable to reduce EMI. Pay attention on data-rate
driven noise. For example, if data-rate is 1.5Gbps, common mode choke coil of 1.5GHz common mode
impedance is desired to be high, while 1.5GHz differential impedance is low.
PCB Cross-sectional View
for Microstrip Lines
> 3 x S1
S1
GND
> 3 x S1
GND
Layer1: Signals
Layer2: Ground
Layer3: Power
Layer3: Signals
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply
to the customer's design. We are not responsible for possible errors and omissions in this material. Please
note if errors or omissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties
the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we
will be exempted from the responsibility unless it directly relates to the production process or functions of
the product.
5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video
device, office automation device, communication device, consumer electronics, smartphone, feature
phone, and amusement machine device. This product must not be used for applications that require
extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear
power control device, combustion chamber device, medical device related to critical care, or any kind
of safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a
product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in
this data sheet. THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other
than the Specified Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent
that the user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a
certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to
have sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems
necessary to support warranty for performance of this product. Except where mandated by applicable
law or deemed necessary by THine based on the user’s request, testing of all functions and performance
of the product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or
malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a
smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses.
THine Electronics, Inc.
[email protected]
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