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Preliminary
PT6382
Front panel VFD Control/Driver With
Standby Power Management
DESCRIPTION
FEATURES
The PT6382 is designed to integrate the VFD driver,
key-scan matrix, LED driving, infrared (IR) remote
control decoding and into one integrated solution. All
functions are programmable using 3-wire serial or I2C
interface.
In standby operation, the PT6382 provides the standby
power management to the chipset for low power
consumption
The PT6382 is housed in a 44-pin LQFP package. Pin
assignments and application circuit are optimized for
easy PCB layout and cost saving advantages.
APPLICATIONS
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VCR
DVD recorder
Home theater
Set-top box and other application that require a
compact, integrated solution
• HTiB (Home theater in a Box)
• Personal Video recorders (PVRs)
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IC front panel VFD controller driver
Standby power management to the host
3.3V (VDD) and down to -30V (VEE) supply for the IC
IR remote control decoder (Philips, NEC, Thomson,
Sony, Matsushita)
Multiple display modes ( 12 segments and 12 digits to
20 segments and 4 digits )
High voltage outputs (VDD - 33.3V max)
No external resistors necessary for driver outputs
(P-CH. Open drain + pull-down resistor)
Key scanning (up to 12 x 2 matrix = 24 keys)
LED ports ([email protected], [email protected])
3-wire (SPI) serial interface for clock, data
input/output, and strobe
I2C serial interface (SCL, SDA) communication
protocol
Programmable hotkeys for IR remote control
command
Programmable hotkeys for KEYSCAN command
Low power consumption in standby mode
Dimming circuit (8 steps)
Available in LQFP-44 package
BLOCK DIAGRAM
STBY
IR_DATA_IN
READY
Remote control
Decoder
MUTE
VDD
(3.3V)
IRQ_N
VSS
(0V)
VEE
(-30V)
IF_SEL
Command Decoder
DIO/SDA
CLK/SCL
3-wire
Serial
I/F
20
Display Memory
(20 x 12)
STB
12
SG1/KS1
20-bit Output
Latch
Segment
Drivers
SG12/KS12
8
VDD
500KHz
oscillator
Timing Generator
key scan and
Dimming circuit
8
Data
Selector
SG13/GR12
Grid/Segment
Drivers
SG20/GR5
TEST
RSTB
K1
K2
8
2
Key Data Memory
(2 x 12)
12
4
12-bit Shift
Register
GR4
Grid
Drivers
GR1
2
LED1
2-bit
Latch
LED2
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6382
1. TYPICAL APPLICATION CIRCUIT
2. FUNCTION DIAGRAM
PRE1.1
2
MAY 2010
PT6382
3. ORDER INFORMATION
Valid Part Number
PT6382-LQ
Package Type
44 Pins, LQFP
Top Code
PT6382-LQ
PRE1.1
VSS
VDD
READY
STBY
MUTE
IRQ_N
RSTB
GR1
GR2
GR3
GR4
4. PIN CONFIGURATION
44
43
42
41
40
39
38
37
36
35
34
SG18/GR7
TEST
4
30
SG17/GR8
OSC
5
29
SG16/GR9
IF_SEL
6
28
SG15/GR10
DIO/SDA
7
27
SG14/GR11
CLK/SCL
8
26
SG13/GR12
STB
9
25
VEE
K1
10
24
SG12/KS12
K2
11
23
SG11/KS11
12
13
14
15
16
17
18
19
20
21
22
SG10/KS10
31
SG9/KS9
3
SG8/KS8
IR_DATA_IN
SG7/KS7
SG19/GR6
SG6/KS6
32
SG5/KS5
2
SG4/KS4
LED2
SG3/KS3
SG20/GR5
SG2/KS2
33
SG1/KS1
1
VDD
LED1
3
MAY 2010
PT6382
5. PIN DESCRIPTION
Pin Name
I/O
LED1, LED2
O
CMOS Sink outputs (20 mA max.)
Description
Pin No
IR_DATA_IN
I
Remote control input. Connect to IR photodiode
3
TEST
O
TEST pin with an internal pull-down resistor. Customer can’t use this pin
4
OSC
I
Connect to an external resistor of value 33KΩ ± 1%
5
1, 2
IF_SEL
I
DIO/SDA
I/O
CLK/SCL
I
STB
I
K1, K2
I
Serial interface mode setting
2
IF_SEL = "0" I C interface, IF_SEL = "1"  3-wire (SPI) interface
IF_SEL = "0"The data pin of I2C interface. Connect to 3.3V through an external pull-up resistor.
IF_SEL = "1"The data pin of 3-wire interface. Connect to 3.3V through an external pull-up
resistor. Serial data must be ready at the rising edge of CLK. This pin outputs data at the falling
edge of CLK
2
IF_SEL = "0" The clock pin of I C interface. Connect to 3.3V through an external pull-up resistor
IF_SEL = "1" The clock pin of 3-wire interface. Serial data is read at rising edge and output data
is valid at the falling edge
IF_SEL = "0"Unused pin
IF_SEL = "1"The strobe pin of 3-wire interface
Input data to these pins from external keyboard are latched at the end pf the display cycle
(maximum keyboard size is 12 x 2)
6
7
8
9
10, 11
VDD
-
3.3V±10% positive power supply
12, 43
SG1/KS1to
SG12/KS12
O
Segment output pins(dual function as key source)
13~24
VEE
-
VFD outputs high voltage pull_down level. VDD-33.3V max.
SG13/GR12 to
SG20/GR5
O
These pins are selectable for segment or grid driving
26~33
GR4 to GR1
O
Grid output pins
34~37
RSTB
I
Active low reset input pin
38
IRQ_N
O
Interrupt (Open Drain). A pull up resistor of 10KΩ must be connected on this pin
39
MUTE
O
High level means mute status for audio. Low level stands for normal working
40
STBY
O
READY
I
Pin to control power to the main board. High level means stand-by status.
Low level stands for normal working
High level on this pin means that main board chip has been working normally.
Connect an external pull down resistor of 10kΩ on this pin
VSS
-
Connect this pin to system GND
PRE1.1
25
41
42
44
4
MAY 2010
PT6382
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
PRE1.1
5
MAY 2010