M3028 Series Datasheet

M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
FEATURES
APPLICATIONS
LVPECL/LVDS Differential Output
Low RMS jitter performance 12 kHz to 20 MHz
Low Phase Noise
Compliant to RoHS directive
Base station controllers
4G/LTE applications
Ethernet, SyncE
Test and Measurement
Ordering Information:
Product
Family
M3028
Temperature Range
Code
2
6
Stability*
Value
-40 °C to +85 °C
-20 °C to +70 °C
Code
0
Example: M302820BGPN 122.8800 MHz
M3028
2
* Stability is included in the APR specification.
Absolute Pull
Range (APR)
Enable/Disable
Code
B
U
Value
Enable High (pad 2)
No Enable/Disable
0
Code
G
C
F
B
Value
±20 ppm
±25 ppm
±40 ppm
Logic Type
Code
P
L
G
Value
LVPECL
LVDS
Package/Lead
Configuration
Code
N
P
Value
Leadless
N
Frequency
XXX.XXXX MHz
122.8800MHz
LVPECL Electrical Specifications:
Parameter
Frequency of Operation
Symbol
FO
Min.
30
Typ.
Max.
170
Units
MHz
Conditions
Frequency Stability
Frequency Stability
F/F
-5
-3
Aging
See ordering information
+5
+3
ppm
1st year
Per year thereafter
RF Output
Output Type
Output Load
Symmetry (duty cycle)
Logic Level “0”
Logic Level “1”
Rise/Fall Time
Start-up Time
LVPECL Compatible
50 Ω to (Vcc-2.0) VDC
45
VOL
VOH
TR/TF
TSU
55
Vcc-1.63
Vcc-1.085
0.7
10
70% VCC or
N/C
Enable Logic (Pad 2)
Disable Logic (Pad 2)
Control Voltage
Absolute Pull Range
Modulation Bandwidth
Input Impedance
Linearity
APR
fm
Zin
Operating Voltage
Supply Current
VCC
ICC
30% VCC
Frequency Adjustment
0.00
1.65
3.30
See ordering information
10
20
100
10
V
%
V
V
ns
ms
Ref. to 50% of waveform
20% to 80% of waveform
Tambient = +25°C
V
Output Enabled
V
Output Disabled to high-Z
V
Pad 1
kHz
kΩ
%
-3 dB
Pad 1
Supply Voltage & Power Consumption
3.135
3.300
3.465
80
V
mA
Other Parameters
Phase Jitter (RMS)
ΦJ
0.1
ps
12 KHz to 20 MHz
122.88 MHz
Revision 0
10/22/15
Page 1 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.
M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
LVDS Electrical Specifications:
Parameter
Frequency of Operation
Symbol
FO
Min.
30
Typ.
Max.
170
Units
MHz
Conditions
Frequency Stability
Frequency Stability
F/F
See ordering information
+5
+3
-5
-3
Aging
ppm
1st year
Per year thereafter
RF Output
Output Type
Output Load
Symmetry (duty cycle)
Differential Output
Voltage
Output Offset Voltage
Rise/Fall Time
Start-up Time
LVDS Compatible
100 Ω Differential
VOH
45
VDIFF
250
VOS
TR/TF
TSU
1.125
55
V
%
350
450
mV
1.250
0.4
1.375
0.7
10
V
ns
ms
70% VCC or
N/C
Enable Logic (Pad 2)
Disable Logic (Pad 2)
Control Voltage
Absolute Pull Range
Modulation Bandwidth
Input Impedance
Linearity
APR
fm
Zin
Operating Voltage
Supply Current
VCC
ICC
Phase Jitter (RMS)
ΦJ
30% VCC
Frequency Adjustment
0.30
1.65
3.00
See ordering information
10
100
10
Ref. to 50% of waveform
peak-to-peak differential
output voltage
20% to 80% of waveform
Tambient = +25°C
V
Output Enabled
V
Output Disabled to high-Z
V
Pad 1
kHz
kΩ
%
-3 dB
Pad 1
Supply Voltage & Power Consumption
3.135
3.300
3.465
60
Other Parameters
V
mA
0.2
ps
12 KHz to 20 MHz
156.25 MHz
Environmental & Packaging Requirements:
Storage Temperature
Mechanical Shock
Vibration
Aging
Humidity
Thermal Cycle
Hermeticity
Moisture Sensitivity Level
Solderability
Max. Soldering Conditions
Pad Termination
Package Type
-55°C to 125°C
Per MIL-STD-202, Method 213, Condition E
Per MIL-STD-202, Method 204D, Condition D
+85°C ±3°C, 720H (No BIAS)
+40°C ±2°CX90~95%, 96H (NO BIAS)
Per MIL-STD-883, Method 1011, Condition A
Per MIL-STD-202, Method 112 (1 x 10-8 atm cc/s of Helium)
MSL1
Per EIAJ-STD-002, Method 208
See solder profile, Figure 1
Gold, 1 µm maximum thickness
6-pad 5.0 X 7.0 mm leadless ceramic. RoHS compliant.
Page 2 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.
M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
Typical LVPECL Test Circuit & Load Circuit Diagrams:
Typical LVDS Test Circuit & Load Circuit Diagrams:
Page 3 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.
M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
Output Waveform:
LVPECL Phase Noise Plot:
Page 4 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.
M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
Marking, Pin Out:
Pad
1
2
3
4
5
6
Function
Control Voltage
Enable/Disable or N/C
Ground
Output
Complementary Output
+VCC
Line 1
Line 2
Line 3
Part Marking
[part designation]
FFFMFFFF
M yy ww vv
M
F
yy
ww
vv
Dimensions:
Page 5 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.
Legend
MtronPTI
Frequency
Year
Work Week
Factory code
M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
Soldering Conditions:
Figure 1
Figure 1
Tape and Reel Specifications:
Tape and Reel Specifications
A
B
C
D
5.32
7.28
1.5
7.5
E
2.2
F
4
G
8
H
16
J
178
K
13.5
L
24.8
M
80
Page 6 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.