ROHM BD9012KV-E2

TECHNICAL NOTE
Large Current External FET Controller Type Switching Regulator
Dual-output, high voltage,
high-efficiency step-down
switching controller
BD9012KV
●Overview
The BD9012KV is a 2-ch synchronous controller with rectification switching for enhanced power management efficiency. It
supports a wide input range, enabling low power consumption ecodesign for an array of electronics.
●Features
1) Wide input voltage range: 4.5V to 30V
2) Precision voltage references: 0.8V±1%
3) FET direct drive
4) Rectification switching for increased efficiency
5) Variable frequency: 250k to 1200kHz (external synchronization to 1200kHz)
6) Built-in selected auto remove over current protection
7) Built-in independent power up/power down sequencing control
8) Make various application , step-down , step-up and step-up-down
9) Small footprint packages: VQFP48C
●Applications
Car audio and navigation systems, CRTTV，LCDTV，PDPTV，STB，DVD，and PC systems，portable CD and DVD players,
etc.
●Absolute Maximum Ratings (Ta=25℃)
Parameter
Symbol
Limits
Unit
Parameter
Symbol
VCC Voltage
VCC
34 *1
V
VREG33
EXTVCC Voltage
EXTVCC
34 *1
V
SS1,2､FB1,2
VCCCL1,2 Voltage
VCCCL1,2
34
V
VREG33 Voltage
SS1,2､FB1,2
Voltage
COMP1,2 Voltage
CL1,2 Voltage
CL1,2
34
V
DET1,2 Voltage
DET1,2
SW1,2 Voltage
SW1,2
34 *1
V
RT､SYNC Voltage
RT､SYNC
BOOT1,2 Voltage
BOOT1,2-SW1,2
Voltage
BOOT1,2
BOOT1,2
-SW1,2
40 *1
V
7 *1
V
STB, EN1,2 Voltage
STB, EN1,2
VCC
V
VREG5,5A Voltage
VREG5,5A
7 *1
V
Power Dissipation
Operating
Temperature Range
Storage Temperature
Range
Maximum Junction
Temperature
Limits
Unit
VREG5
V
Pd
1.1 *2
W
Topr
-40 to +105
℃
Tstg
-55 to +150
℃
Tj
+150
℃
COMP1,2
*1 Regardless of the listed rating, do not exceed Pd in any circumstances.
*2 Pd de-rated at 7mW/℃ for temperature above Ta=25℃, Mounted on PCB 70mm×70mm×1.6mm.
Apr.2008
●Operating conditions (Ta=25℃)
Parameter
Symbol
Min.
4.5
Typ.
Max.
Unit
*1 *2
12
30
V
Input voltage 1
EXTVCC
Input voltage 2
VCC
4.5 *1 *2
12
30
V
BOOT－SW voltage
BOOT－SW
4.5
5
VREG5
V
Carrier frequency
OSC
250
300
1200
kHz
Synchronous frequency
SYNC
OSC
-
1200*3*4
kHz
Synchronous pulse duty
Duty
40
50
60
％
Min OFF pulse
TMIN
-
150
-
nsec
★This product is not designed to provide resistance against radiation.
*1 After more than 4.5V, voltage range.
*2 In case of using less than 6V, Short to VCC, EXTVCC and VREG5.
*3 Please do not exceed OSC×1.5.
*4 Do not do such things as switching over to internal oscillating frequency while external synchronization frequency is used.
●Electrical characteristics (Unless otherwise specified, Ta=25℃ VCC=12V STB=5V EN1,2=5V)
Limit
Parameter
Symbol
VIN bias current
Shutdown mode current
Unit
Conditions
Min.
Typ.
Max.
IIN
-
6
10
mA
IST
-
0
10
μA
Feedback reference voltage
VOB
0.792
0.800
0.808
V
Feedback reference voltage
(Ta=-40 to 105℃)
VOB+
0.784
0.800
0.816
V
Open circuit voltage gain
Averr
-
46
-
dB
VO input bias current
IVo+
-
-
1
μA
Carrier frequency
FOSC
900
1000
1100
kHz
RT=27 kΩ
Synchronous frequency
Fsync
-
1200
-
kHz
RT=27 kΩ,SYNC=1200kHz
CL threshold voltage
Vswth
70
90
110
ｍV
CL threshold voltage
（Ta=-40 to 105℃）
Vswth+
67
90
113
ｍV
VREG5 output voltage
VREG5
4.8
5
5.2
V
IREF=6mA
VREG33 reference voltage
VREG33
3.0
3.3
3.6
V
IREG=6mA
VREG5 threshold voltage
VREG_UVLO
2.6
2.8
3.0
V
VREG:Sweep down
VREG5 hysteresis voltage
DVREG_UVLO
50
100
200
mV
VREG:Sweep up
ISS
6.5
10
13.5
μA
VSS=1V
14
μA
VSS=1V,Ta=-40 to 105℃
VSTB=0V
［Error Amp Block］
Ta=-40 to 105℃
※
［Oscillator］
［Over Current Protection Block］
Ta=-40 to 105℃
※
［VREG Block］
［Soft start block］
Charge current
Charge current
ISS+
6
10
(Ta=-40 to 105℃)
Note: Not all shipped products are subject to outgoing inspection.
2/16
※
●Reference data (Unless otherwise specified, Ta=25℃)
100
100
5.0V
80
70
70
3.3V
50
40
30
20
5.0V
50
30
-40℃
2
Io=2A
Rt=27kΩ
20
1
10
0
1
2
OUTPUT CURRENT：Io[A]
6
3
9
12
15
18
21
INPUT VOLTAGE ： V IN [V]
0
24
0
10
20
INPUT VOLTAGE：VIN[V]
Fig.2 Efficiency 2
Fig.1 Efficiency 1
0.816
1100
OSILATING FREQUENCY ： FOSC [kHz]
0.812
0.808
0.804
0.800
0.796
0.792
0.788
100
90
80
70
1080
-40 -15 10
35
60
85 110
AMBIENT TEMPERATURE ： Ta[℃]
1040
1020
1000
980
960
940
920
Fig.5 Over current detection vs.
temperature characteristics
Fig.4 Reference voltage vs.
temperature characteristics
5.25
RT=27kΩ
1060
900
-40
60
0.784
-40 -15 10
35
60
85 110
AMBIENT TEMPERATURE ： Ta[℃]
30
Fig.3 Circuit current
110
過電流検出電圧 ： Vswth[mV]
REFERENCE VOLTAGE ： VOB[V]
25℃
3
40
0
0
105℃
4
60
VIN=12V
10
5
3.3V
CIRCUIT　CURRENT[mA]
80
60
6
90
EFFICIENCY[%]
EFFICIENCY[%]
90
-15
10
35
60
85
110
AMBIENT TEMPERATURE ： Ta[℃]
Fig.6 Frequency vs.
temperature characteristics
6
3.0
5.00
5
OUTPUT VOLTAGE ： Vo[V]
OUTPUT VOLTAGE ： Vo[V]
VREG5
4.50
4.25
4.00
3.75
VREG33
3.50
3.25
3.00
-40
-15
10
35
60
85
AMBIENT TEMPERATURE ： Ta[℃]
110
2.5
OUTPUT VOLTAGE ： Vo[V]
4.75
5.0V
4
3
3.3V
2
1
RC L=15mΩ
2.0
1.5
1.0
0.5
0.0
0
0
5
Fig.7 Internal Reg vs.
temperature characteristics
10
15
20
INPUT VOLTAGE ： VIN[V]
25
0
Fig.8 Line regulation
1
2
3
4
5
OUTPUT CURRENT ： Io[A]
6
Fig.9 Load regulation
6
50mV/div
OUTPUT　VOLTAGE ： Vo[V]
5
VOUT
50mV/div
VOUT
4
105℃
3
25℃
2
-40℃
1
IOUT
0
1A/div
0
2
4
INPUT VOLTAGE：VEN[V]
IOUT
1A/div
6
Fig.10 EN threshold voltage
Fig.11 Load transient response 1
3/16
Fig.12 Load transient response 2
●Block diagram
STB VCC
EXTVCC
41
25
SYNC
RT
7
33
34
5V Reg
VREG5
3.3V Reg
44
B.G
TSD
UVLO
VCCCL2
5
CL2
3
BOOT2
2
OUTH2
1
SW2
48
OUTL2
46
47
FB2
SS2
39
COMP2
38
OCP
DRV
Reset
SW
TSD
UVLO
TSD
UVLO
Q
Reset Set
37
Set
Set
DRV
Reset
LOGIC
－
＋
＋
PW M
COMP
35
LLM
Slope
Slope
PW M
COMP
8
VCCCL1
10
CL1
11
BOOT1
12
OUTH1
SW
13
LOGIC
4(17)
Q
OUTL1
2(14)
DGND1
21
UVLO
Ｏ
SW1
VREG5A
3(15)
Set Reset
Err Amp
Err Amp
VREG33
OSC
OCP
VREG5
DGND2
TSD
2.7V
19
SYNC
23
FB1
SS1
22
COMP1
0.8V
0.8V
Q
Q
Set
Reset
Sequence DET
Set
Reset
Sequence DET
0.56V
0.56V
36
31
27
DET2
LOFF
EN2
26
30
29
EN1 (GNDS) GND
Fig-13
4/16
24
DET1
LLM
SYNC
RT
N.C
LOFF
GNDS
GND
N.C
EN2
EN1
STB
●Pin function table
DET2
●Pin configuration
36
35
34
33
32
31
30
29
28
27
26
25
24 DET1
SS2 37
COMP2 38
23 SS1
FB2 39
22 COMP1
N.C 40
21 FB1
EXTVCC 41
20 N.C
N.C 42
19 VREG33
N.C 43
18 N.C
VREG5 44
17 VREG5A
16 N.C
N.C 45
OUTL2 46
15 OUTL1
DGND2 47
14 DGND1
13 SW1
1
2
3
4
5
6
7
8
9
10
11
12
OUTH2
BOOT2
CL2
N.C
VCCCL2
N.C
VCC
VCCCL1
N.C
CL1
BOOT1
OUTH1
SW2 48
Fig-15
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin name
Function
OUTH2
BOOT2
CL2
N.C
VCCCL2
N.C
VCC
VCCCL1
N.C
CL1
BOOT1
OUTH1
SW1
DGND1
OUTL1
N.C
VREG5A
N.C
VREG33
N.C
FB1
COMP1
SS1
DET1
STB
EN1
EN2
N.C
GND
GNDS
LOFF
N.C
RT
SYNC
LLM
DET2
SS2
COMP2
FB2
N.C
EXTVCC
N.C
N.C
VREG5
N.C
OUTL2
DGND2
SW2
High side FET gate drive pin 2
OUTH2 driver power pin
Over current detection pin 2
Non-connect (unused) pin
Over current detection VCC2
Non-connect (unused) pin
Input power pin
Over current detection CC1
Non-connect (unused) pin
Over current detection setting pin 1
OUTH1 driver power pin
High side FET gate drive pin 1
High side FET source pin 1
Low side FET source pin 1
Low side FET gate drive pin 1
Non-connect (unused) pin
FET drive REG input
Non-connect (unused) pin
Reference input REG output
Non-connect (unused) pin
Error amp input 1
Error amp output 1
Soft start setting pin 1
FB detector output 1
Standby ON/OFF pin
Output 1 ON/OFF pin
Output 2 ON/OFF pin
Non-connect (unused) pin
Ground
Sense ground
Test Mode Terminal
Non-connect (unused) pin
Switching frequency setting pin
External synchronous pulse input pin
Built-in pull-down resistor pin
FB detector output 2
Soft start setting pin 2
Error amp output 2
Error amp input 2
Non-connect (unused) pin
External power input pin
Non-connect (unused) pin
Non-connect (unused) pin
FET drive REG output
Non-connect (unused) pin
Low side FET gate drive pin 2
Low side FET source pin 2
High side FET source pin 2
●Block functional descriptions
・Error amp
The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which is
used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage.
・Oscillator (OSC)
Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250kHz and 550kHz.
・ SLOPE
The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator.
・PWM COMP
The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from the
SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum.
・Reference voltage (5Vreg，33Vreg)
This block generates the internal reference voltages: 5V and 3.3V.
・External synchronization (SYNC)
Determines the switching frequency, based on the external pulse applied.
・Over current protection (OCP)
Over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When over current protection is active, Duty is low,
and output voltage also decreases. When LOFF=L, the output voltage has fallen to 70% or below and output is latched OFF. The OFF latch
mode ends when the latch is set to STB, EN.
・Sequence control (Sequence DET)
Compares FB voltage with reference voltage (0.56V) and outputs the result as DET.
・Protection circuits (UVLO/TSD)
The UVLO lock out function is activated when VREG falls to about 2.8V, while TSD turns outputs OFF when the chip temperature reaches or
exceeds 150℃. Output is restored when temperature falls back below the threshold value.
5/16
●Application circuit example (Parentheses indicate VQFP48C pin numbers)
VIN(12V)
100uF
23mΩ
0.33
100Ω
SP8K2
23mΩ
10
Ω
uF
100Ω
15kΩ
30uF
150Ω
(C2012JB
0J106K
：TDK)
34
33
32
31
30
29
28
(10)
(8)
(7)
(5)
(3)
(2)
(1)
VCC
CL2
BOOT2
RB051
L-40
3300pF
35
(11)
VCCCL2
0.1
uF
10uH
36
(12)
CL1
Vo(1.8V/2A)
RB160
VA-40
OUTH1
1(13)
SW1
2(14)
DGND1
3(15)
BOOT1
(SLF10145：TDK)
SP8K2
1nF
VCCCL1
1nF
RB160
VA-40
OUTH2
SW2
27(48)
DGND2
26(47)
OUTL1
OUTL2
25(46)
4(17)
VREG5A
VREG5
24(44)
5(19)
VREG33
6(21)
FB1
7(22)
COMP1
1uF
30uF
23
EXTVCC
22(41)
FB2
21(39)
330pF
10000pF
10uH
1kΩ
8(23)
COMP2
SS1
EN1
EN2
GND
LOFF
RT
SYNC
LLM
9(24)
SS2
DET2
10
11
12
13
14
15
16
17
18
(25)
(26)
(27)
(29)
(31)
(33)
(34)
(35)
(36)
DET1
STB
43
kΩ
(C2012JB
0J106K
：TDK)
1000pF
510Ω
0.33uF
330pF
0.1uF
Vo(2.5V/2A)
RB051
L-40
1uF
1uF
12kΩ
(SLF10145：TDK)
0.1
uF
20kΩ
20(38)
3.3kΩ 3300pF
19(37)
0.1uF
100kΩ
Fig-16B（Step-Down：Cout=Ceramic Capacitor）
There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics.
Please verify and confirm using practical applications.
6/16
●Application component selection
(1) Setting the output L value
The coil value significantly influences the output ripple current.
Thus, as seen in equation (5), the larger the coil, and the higher
the switching frequency, the lower the drop in ripple current.
ΔIL
Fig-17
ΔIL =
（VCC-VOUT）×VOUT
L×VCC×f
[A]・・・
（5）
VCC
IL
The optimal output ripple current setting is 30% of maximum current.
ΔIL = 0.3×IOUTmax.[A]・・・（6）
VOUT
L
Co
L=
Fig-18
（VCC-VOUT）×VOUT
ΔIL×VCC×f
（ΔIL：output ripple current
Output ripple current
[H]・・・
（7）
f：switching frequency）
※Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease
efficiency.
Please establish sufficient margin to ensure that peak current does not exceed the coil current rating.
※Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency.
(2) Setting the output capacitor Co value
Select the output capacitor with the highest value for ripple voltage (VPP) tolerance and maximum drop voltage
(at rapid load change). The following equation is used to determine the output ripple voltage.
ΔIL
Step down
ΔVPP = ΔIL × RESR +
Vo
1
×
Co
×
[V]
Note: f：switching frequency
f
Vcc
Be sure to keep the output Co setting within the allowable ripple voltage range.
※Please allow sufficient output voltage margin in establishing the capacitor rating. Note that low-ESR capacitors enable
lower output ripple voltage.
Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please factor
in the conditions described in the capacitance equation (9) for output capacitors, below.
TSS × (Limit – IOUT)
Tss： soft start time
Co ≦
・・・ （9）
VOUT
ILimit：over current detection value（2/16）reference
Note: less than optimal capacitance values may cause problems at startup.
(3) Input capacitor selection
VIN
Cin
VOUT
L
Co
The input capacitor serves to lower the output impedance of the power
source connected to the input pin (VCC). Increased power supply output
impedance can cause input voltage (VCC) instability, and may negatively
impact oscillation and ripple rejection characteristics. Therefore, be
certain to establish an input capacitor in close proximity to the VCC and
GND pins. Select a low-ESR capacitor with the required ripple current
capacity and the capability to withstand temperature changes without
wide tolerance fluctuations. The ripple current IRMSS is determined
using equation (10).
IRMS = IOUT ×
Fig-19
Input capacitor
VOUT（VCC - VOUT）
[A]・・・
（10）
VCC
Also, be certain to ascertain the operating temperature, load range and
MOSFET conditions for the application in which the capacitor will be used,
since capacitor performance is heavily dependent on the application’s
input power characteristics, substrate wiring and MOSFET gate drain
capacity.
7/16
(4) Feedback resistor design
Please refer to the following equation in determining the proper feedback resistance. The recommended setting is in a range
between 10kΩ and 330kΩ. Resistance less than 10kΩ risks decreased power efficiency, while setting the resistance value
higher than 330kΩ will result in an internal error amp input bias current of 0.2uA increasing the offset voltage. Please use it with
150nsec or more so that there is a possibility that the output becomes unstable when the output pulse width is small.（12）
Vo
Internal ref. 0.8V
R8 +R9
Vo =
R8
× 0.8 [V] ・・・（11）
R9
FB
R9
Vo
×
Vin
Fig-20
1
≧ 150ns ・・・
（12）
f
(5) Setting switching frequency
The triangular wave switching frequency can be set by connecting a resistor to the RT 15(33) pin. The RT sets the frequency
by adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in determining proper
RT resistance, noting that the recommended resistance setting is between 50kΩ and 130kΩ. Settings outside this range
may render the switching function inoperable, and proper operation of the controller overall cannot be guaranteed when
unsupported resistance values are used.
Fig-21 RT vs. switching frequency
(6) Setting the soft start delay
The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup. The figure
below shows the relation between soft start delay time and capacitance, which can be calculated using equation (12) at right.
DELAY TIME[ms]
10
1
0.8V(typ.)×CSS
TSS =
[sec]・・・(12)
ISS(10μA Typ.)
0.1
0.01
0.001
0.01
0.1
SS CAPACITANCE[uF]
Fig-22 SS capacitance vs. delay time
Recommended capacitance values are between 0.01uF and 0.1uF. Capacitance lower than 0.01uF may generate output
overshoots. Please use high accuracy components (such as X5R) when implementing sequential startups involving other
power sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on
input voltage, output voltage and capacitance, coils and other characteristics.
8/16
(7) Setting over current detection values
The current limit value（ILimit）is determined by the resistance of the RCL established between CL and VCCCL.
VIN
Over current detection point
IL
VCCCL
RCL
CL
IL
Vo
ILimit =
L
Fig-23
90m
RCL
[A]・・・(13)
Fig-24
When the current goes beyond the threshold value, the current can be limited by reducing the ON Duty Cycle. When the load
goes back to the normal operation, the output voltage also becomes back on to the specific level.
The current limit value
Vo
Io
Fig-25
(8) Method for determining phase compensation
Conditions for application stability
Feedback stability conditions are as follows:
・When gain is 1 (0dB) and phase shift is 150° or less (i.e., phase margin is at least 30°):
a dual-output high-frequency step-down switching regulator is required
Additionally, in DC/DC applications, sampling is based on the switching frequency; therefore, overall GBW may be set at no
more than 1/10 the switching frequency. In summary, target characteristics for application stability are:
・Phase shift of 150° or less (i.e., phase margin of 30° or more) with gain of 1 (0dB)
・GBW (i.e., gain 0dB frequency) no more than 1/10 the switching frequency.
Stability conditions mandate a relatively higher switching frequency, in order to limit GBW enough to increase response.
The key to achieving successful stabilization using phase compensation is to cancel the secondary phase margin/delay
(-180°) generated by LC resonance, by employing a dual phase lead. In short, adding two phase leads stabilizes the
application.
GBW (the frequency at gain 1) is determined by the phase compensation capacitor connected to the error amp. Thus, a larger
capacitor will serve to lower GBW if desired.
①
General use integrator (low-pass filter)
②
Integrator open loop characteristics
(a)
A
-20dB/decade
18 0
Feedback
COMP
A
R
FB
C
Gain
[dB]
point (a) fa =
GBW(b)
90
0
0
Phase 0
[deg] -90
-9 0
1
2πRCA
point (b)点 fa = GBW
-90°
Phase margin
1.25[Hz]
1
2πRC
[Hz]
-180°
-18 0
-180
Fig-26
Fig-27
The error amp is provided with phase compensation similar to that depicted in figures ① and ② above and thus serves
as the system’s low-pass filter.
In DC/DC converter applications, R is established parallel to the feedback resistance.
9/16
When electrolytic or other high-ESR output capacitors are used:
Phase compensation is relatively simple for applications employing high-ESR output capacitors (on the order of several
Ω). In DC/DC converter applications, where LC resonance circuits are always incorporated, the phase margin at these
locations is -180°. However, wherever ESR is present, a 90° phase lead is generated, limiting the net phase margin to -90°
in the presence of ESR. Since the desired phase margin is in a range less than 150°, this is a highly advantageous
approach in terms of the phase margin. However, it also has the drawback of increasing output voltage ripple components.
③ LC resonance circuit
④ ESR connected
Vcc
Vcc
Vo
Vo
L
L
C
Fig-28
fr =
1
2π√LC
RESR
C
Fig-29
resonance point1
[Hz]：Resonance Point
2π√LC
1
fESR =
[Hz] :Zero
2πRESRC
fr =
[Hz]
Resonance point phase margin -180°
-90°:Pole
Since ESR changes the phase characteristics, only one phase lead need be provided for high-ESR applications. Please choose
one of the following methods to add the phase lead.
⑤
⑥
Add C to feedback resistor
Vo
Add R3 to aggregator
Vo
C2
C1
R3
C2
R1
R1
FB
FB
A
COMP
COMP
A
R2
R2
Fig-30
Phase lead fz =
Fig-31
1
2πC1R1
[Hz]
Phase lead fz =
1
2πC2R3
[Hz]
Set the phase lead frequency close to the LC resonance frequency in order to cancel the LC resonance.
When using ceramic, OS-CON, or other low-ESR capacitors for the output capacitor:
Where low-ESR (on the order of tens of mΩ) output capacitors are employed, a two phase-lead insertion scheme is
required, but this is different from the approach described in figure ③~⑥, since in this case the LC resonance gives rise
to a 180° phase margin/delay. Here, a phase compensation method such as that shown in figure ⑦ below can be
implemented.
⑦
Phase compensation provided by secondary (dual) phase lead
Vo
C1
Phase lead fz1 =
C2
R3
R1
FB
Phase lead fz2 =
A
COMP
R2
1
2πR1C1
1
2πR3C2
LC resonance frequency fr =
[Hz]
[Hz]
1
2π√LC
[Hz]
Fig-32
Once the phase-lead frequency is determined, it should be set close to the LC resonance frequency.
This technique simplifies the phase topology of the DCDC Converter. Therefore, it might need a certain amount
of trial-and-error process. There are many factors(The PCB board layout, Output Current, etc.)that can affect
the DCDC characteristics. Please verify and confirm using practical applications.
10/16
（9）MOSFET selection
VCC
VDS
IL
Vo
VGSM1
VDS
VGSM2
FET uses Nch MOS
・VDS＞Vcc
・VGSM1＞BOOT-SW interval voltage
・VGSM2＞VREG5
・Allowable current＞voltage current + ripple current
※Should be at least the over current protection value
※Select a low ON-resistance MOSFET for highest efficiency
・ The shoot-through may happen when the input parasitic
capacitance of FET is extremely big or the Duty ratio is less
than or equal to 10%. Less than or equal to 1000pF input
parasitic capacitance is recommended. Please confirm
operation on the actual application since this character is
affected by PCB layout and components.
Fig-33
（10）Schottky barrier diode selection
VCC
Vo
・ Reverse voltage VR＞Vcc
・ Allowable current＞voltage current + ripple current
※Should be at least the over current protection value
※Select a low forward voltage, fast recovery diode for highest
efficiency
VR
Fig-34
（11）Sequence function
●Circuit diagram
●Timing chart
When EN1 stays ”H” and EN2 returns to ”H”, DET1 is in
open state; thus SS2 is asserted, and Vo2 output starts.
If Vo2 is 76% of the voltage setting or higher, DET2 goes
open and SS1 is asserted, starting Vo1 output.
With EN1, 2 at ”H” level, when EN1 goes ”L”,
Vo1 turns OFF, but Vo2 output continues.
VREG5
VCC VREG5
EN1
EN2
Vo1
OUTH1 BOOT1 VCC BOOT2 OUTH2
SW1
Vo2
SW2
OUTL1
OUTL2
DGND1
DGND2
DET2
SS1
FB1
0.61V
FB2
FB1
COMP1
COMP2
SS1
DET2
STB
Vo1
over 76%
SS2
DET1
SS2
DET1
EN1
EN2 GND
FB2
Vo2
0.56V
under 70%
With EN1,2 at “H” level, if
Vo1 starts at 76% or more of
voltage setting, DET goes
open and SS1 is asserted,
starting Vo2 output.
Fig-35
A
0.56V
over 70%
over 76%
With EN2 set ”L”, if Vo2
A
goes below 70% the voltage
setting, DET2 shorts and SS1
is asserted, turning Vo1 OFF
Fig-36
11/16
0.61V
Same as “A” at left
●Input/Output equivalent circuits
13，48PIN（SW1，SW2）
2，11PIN（BOOT2，BOOT1）
1，15PIN（OUTH1，OUTH2）
14，47PIN（DGND1，DGND2）
15，46PIN（OUTL1，OUTL2）
44，17PIN（VREG5，VREG5A）
31PIN（LOFF）
VREG5
BOOT
OUTL
OUTH
LOFF
172.2k
100k
DGND
SW
135.8k
300k
34PIN（SYNC）
21，39PIN（FB1，FB2）
23，37PIN（SS1，SS2）
VREG5
/ VREG5A
VREG5
/ VREG5A
VREG5
5k
SYNC
1k
FB
250k
50k
1P
2.5
25，26，27PIN
（STB，EN1，EN2）
100k
24，36PIN（DET1，DET2）
33PIN（RT）
VREG5
/ VREG5A
VCC
STB
EN
2k
SS
172.2k
100k
VREG5
10k
DET
RT
135.8k
3，10PIN（CL2，CL1）
5，8PIN（VCCCL2，VCCCL1）
35PIN（LLM）
22，38PIN（COMP1，COMP2）
VCC
VREG5
/ VREG5A
VREG5A
VCCCL
5k
VCC
LLM
5P
308k
CL
41PIN（EXTVCC）
44PIN（VREG5）
17PIN（VREG5A）
VCC
VCC
VREG5A
VCC
150k
VREG5
VREG5A
VREG33
746.32k
746.32k
255k
469.06k
12/16
5kΩ
5kΩ
19PIN（VREG33）
150k
20Ω
1k
VCC
EXTVCC
COMP
●Operation notes
1）Absolute maximum ratings
Exceeding the absolute maximum ratings for supply voltage, operating temperature or other parameters can damage or
destroy the IC. When this occurs, it is impossible to identify the source of the damage as a short circuit, open circuit, etc.
Therefore, if any special mode is being considered with values expected to exceed absolute maximum ratings, consider
taking physical safety measures to protect the circuits, such as adding fuses.
2）GND electric potential
Keep the GND terminal potential at the lowest (minimum) potential under any operating condition.
3）Thermal design
Be sure that the thermal design allows sufficient margin for power dissipation (Pd) under actual operating conditions.
4）Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed surface boards. Connection errors may result in damage or
destruction of the IC. The IC can also be damaged when foreign substances short output pins together, or cause shorts
between the power supply and GND.
5）Operation in strong electromagnetic fields
Use caution when operating in the presence of strong electromagnetic fields, as this may cause the IC to malfunction.
6）Testing on application boards
Connecting a capacitor to a low impedance pin for testing on an application board may subject the IC to stress. Be sure to
discharge the capacitors after every test process or step. Always turn the IC power supply off before connecting it to or
removing it from any of the apparatus used during the testing process. In addition, ground the IC during all steps in the
assembly process, and take similar antistatic precautions when transporting or storing the IC.
7) The output FET
The shoot-through may happen when the input parasitic capacitance of FET is extremely big or the Duty ratio is less than
or equal to 10%. Less than or equal to 1000pF input parasitic capacitance is recommended. Please confirm operation on
the actual application since this character is affected by PCB layout and components.
8）This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. Relations between each potential may form as shown in the example below, where a resistor and transistor
are connected to a pin:
○
With the resistor, when GND＞ Pin A, and with the transistor (NPN), when GND＞Pin B:
The P-N junction operates as a parasitic diode
○
With the transistor (NPN), when GND＞ Pin B:
The P-N junction operates as a parasitic transistor by interacting with the N layers of elements in proximity to the
parasitic diode described above.
Parasitic diodes inevitably occur in the structure of the IC. Their operation can result in mutual interference between circuits,
and can cause malfunctions, and, in turn, physical damage or destruction. Therefore, do not employ any of the methods
under which parasitic diodes can operate, such as applying a voltage to an input pin lower than the (P substrate) GND.
Resistor
Transistor（NPN）
(PINA)
(PINB)
B
C
E
(PINB)
(PINA)
P
N
P
P
+
P
+
N
P
N
Parasitic element
GND
P
+
N
P
B
+
N
P substrate
E
GND
Parasitic element
GND
Parasitic element or transistor
Fig-37
C
Fig-38
Parasitic element or transistor
Fig-39
Fig-40
9）GND wiring pattern
When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is
recommended, in order to separate the small-signal and high current patterns, and to be sure voltage changes stemming
from the wiring resistance and high current do not cause any voltage change in the small-signal GND. In the same way, care
must be taken to avoid wiring pattern fluctuations in any connected external component GND.
10）In some application and process testing, Vcc and pin potential may be reversed, possibly causing internal circuit or element
damage. For example, when the external capacitor is charged, the electric charge can cause a Vcc short circuit to the GND.
13/16
In order to avoid these problems, limiting output pin capacitance to 100μF or less and inserting a Vcc series countercurrent
prevention diode or bypass diode between the various pins and the Vcc is recommended.
Bypass diode
Countercurrent prevention diode
Vcc
Pin
Fig-41
11）Thermal shutdown (TSD)
This IC is provided with a built-in thermal shutdown (TSD) circuit, which is designed to prevent thermal damage to or
destruction of the IC. Normal operation should be within the power dissipation parameter, but if the IC should run beyond
allowable Pd for a continued period, junction temperature (Tj) will rise, thus activating the TSD circuit, and turning all output
pins OFF. When Tj again falls below the TSD threshold, circuits are automatically restored to normal operation. Note that
the TSD circuit is only asserted beyond the absolute maximum rating. Therefore, under no circumstances should the TSD
be used in set design or for any purpose other than protecting the IC against overheating
12）The SW pin
When the SW pin is connected in an application, its coil counter-electromotive force may give rise to a single electric
potential. When setting up the application, make sure that the SW pin never exceeds the absolute maximum value.
Connecting a resistor of several Ω will reduce the electric potential. (See Fig. 43)
Vcc
BOOT
OUTH
R
SW
Vo
Fig-42
OUTL
DGND
13）Dropout operation
When input voltage falls below approximately output voltage / 0.9 (varying depending on operating frequency) the ON
interval on the OUTL side MOS is lost, making boost applications and wrap operation impossible. If a small differential
between input and output voltage is envisioned for a prospective application, connect the load such that the SW voltage
drops to the GND level. Managing this load requires discharging the SW line capacitance (SW pin capacitance: approx.
500pF; OUTL side MOS D-S capacitance; Schottky capacitance). Supported loads can be calculated using the equation
below.
Output voltage × SW line capacitance
ILOAD =
25n
Note that SW line capacitance is lower with smaller loads, and more stable operation is attained when low voltage bias
circuits are configured as in the example below (Fig. 44). However, the degree to which line capacitance is reduced or
operational stability is attained will vary depending on the board layout and components. Therefore, be certain to confirm
the effectiveness of these design factors in actual operation before entering mass production.
Vcc
VREG
OUT
Vo
SW
OUT
Fig-43
14/16
Vcc
14）Logic of Output
When each function operates, each output is as follows.
Function
Upper side FET
OUTH
Lower side FET
OUTL
EN= L
OFF
L
OFF
L
OCP
OFF
L
ON
H
UVLO
OFF
L
OFF
L
TSD
OFF
L
OFF
L
15/16
●Power dissipation vs. temperature characteristics
VQFP48C
PD(W)
POWER DISSIPATION ：Pd [W]
1.2
1.0
②1.1W
0.8
0.6
①0.75W
0.4
0.2
0.0
0
25
50
75
100 125 150
AMBIENT TEMPERATORE：Ta [℃]
①：Stand-alone IC
②：Mounted on Rohm standard board
（70mm x 70mm x 1.6mm glass-epoxy board ）
●Part order number
B
D
ROHM part
code
9
0
1
2
K
Type/No.
V
－
E
2
Package type
KV ： VQFP48C
VQFP48C
< Packing information >
<Dimension>
Tape
Embossed carrier tape
Quantity
1500pcs
Direction
of feed
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
Reel
（Unit:mm)
1Pin
Direction of feed
※When you order , please order in times the amount of package quantity.
16/16
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level
of reliability and the malfunction of which would directly endanger human life (such as medical
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers
and other safety devices), please be sure to consult with our sales representative in advance.
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM
cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
ROHM Customer Support System
www.rohm.com
Copyright © 2008 ROHM CO.,LTD.
THE AMERICAS / EUROPE / ASIA / JAPAN
Contact us : webmaster@ rohm.co. jp
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Appendix1-Rev2.0