16-Bit, 250 kSPS PulSAR ADC in MSOP/QFN AD7685 FEATURES APPLICATION DIAGRAM APPLICATIONS 0.5 INL (LSB) IN– REF VDD VIO SDI AD7685 1.8V TO VDD SCK 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS) SDO GND CNV Figure 2. Table 1. MSOP, QFN (LFCSP)/SOT-23 14-/16-/18-Bit PulSAR ADC Type 18-Bit True Differential 16-Bit True Differential 16-Bit Pseudo 100 kSPS 250 kSPS AD7691 AD7684 AD7687 AD7680 AD7685 400 kSPS to 500 kSPS AD7690 AD7982 AD7688 AD7693 AD7686 AD7683 AD7940 AD7694 AD7942 AD7946 1000 kSPS AD7982 AD7980 ADC Driver ADA4941 ADA4841 ADA4941 ADA4841 ADA4841 ADA4841 The AD7685 is a 16-bit, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN−. The reference voltage, REF, is applied externally and can be set up to the supply voltage. 1.0 0 Power dissipation scales linearly with throughput. –0.5 –1.0 0 16384 32768 CODE 49152 65536 02968-005 –1.5 –2.0 IN+ 2.5V TO 5V GENERAL DESCRIPTION POSITIVE INL = +0.33LSB NEGATIVE INL = –0.50LSB 1.5 0 TO VREF Differential 14-Bit Pseudo Differential Battery-powered equipment Medical instruments Mobile communications Personal digital assistants (PDAs) Data acquisition Instrumentation Process controls 2.0 0.5V TO VDD 02968-001 16-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR) SINAD: 93.5 dB @ 20 kHz THD: −110 dB @ 20 kHz Pseudo differential analog input range 0 V to VREF with VREF up to VDD No pipeline delay Single-supply operation 2.3 V to 5.5 V with 1.8 V to 5 V logic interface Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Daisy-chain multiple ADCs, BUSY indicator Power dissipation 1.4 μW @ 2.5 V/100 SPS 1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS Standby current: 1 nA 10-lead package: MSOP (MSOP-8 size) and 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) Pin-for-pin-compatible with 10-lead MSOP/QFN PulSAR® ADCs Figure 1. Integral Nonlinearity vs. Code. The SPI-compatible serial interface also features the ability, using the SDI input, to daisy chain several ADCs on a single 3-wire bus or provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate supply VIO. The AD7685 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved. AD7685 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 16 Applications....................................................................................... 1 Voltage Reference Input ............................................................ 16 Application Diagram........................................................................ 1 Power Supply............................................................................... 16 General Description ......................................................................... 1 Supplying the ADC from the Reference.................................. 17 Revision History ............................................................................... 2 Digital Interface.......................................................................... 17 Specifications..................................................................................... 3 CS Mode 3-Wire, No BUSY Indicator..................................... 18 Timing Specifications....................................................................... 5 CS Mode 3-Wire with BUSY Indicator ................................... 19 Absolute Maximum Ratings............................................................ 7 CS Mode 4-Wire, No BUSY Indicator..................................... 20 ESD Caution.................................................................................. 7 CS Mode 4-Wire with BUSY Indicator ................................... 21 Pin Configuration and Function Descriptions............................. 8 Terminology ...................................................................................... 9 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 13 Circuit Information.................................................................... 13 Converter Operation.................................................................. 13 Typical Connection Diagram ................................................... 14 Analog Inputs.............................................................................. 15 Chain Mode, No BUSY Indicator ............................................ 22 Chain Mode with BUSY Indicator........................................... 23 Application Hints ........................................................................... 24 Layout .......................................................................................... 24 Evaluating the Performance of the AD7685............................... 24 True 16-Bit Isolated Application Example .............................. 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 27 REVISION HISTORY 3/07—Rev. A to Rev. B Changes to Features and Table 1 .................................................... 1 Changes to Table 3............................................................................ 4 Moved Figure 3 and Figure 4 to Page............................................. 6 Inserted Figure 6; Renumbered Sequentially................................ 8 Changes to Figure 13 and Figure 14............................................. 11 Changes to Figure 27...................................................................... 14 Changes to Table 9.......................................................................... 16 Changes to Figure 32...................................................................... 17 Changes to Figure 43...................................................................... 22 Changes to Figure 45...................................................................... 23 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 27 12/04—Rev. 0 to Rev. A Changes to Specifications ................................................................ 3 Changes to Figure 17 Captions ..................................................... 11 Changes to Power Supply Section ................................................ 17 Changes to Digital Interface Section............................................ 18 Changes to CS Mode 4-Wire No Busy Indicator Section ......... 21 Changes to CS Mode 4-Wire with Busy Indicator Section ....... 22 Changes to Chain Mode, No Busy Indicator Section ................ 23 Changes to Chain Mode with Busy Indicator Section............... 24 Added True 16-Bit Isolated Application Example Section ....... 26 Added Figure 47.............................................................................. 26 Changes to Ordering Guide .......................................................... 28 4/04—Revision 0: Initial Revision Rev. B | Page 2 of 28 AD7685 SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25°C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error 2 , TMIN to TMAX Gain Error Temperature Drift Offset Error2, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Conditions Min 16 IN+ − IN− IN+ 0 −0.1 IN− fIN = 250 kHz Acquisition phase −0.1 A Grade Typ Max VREF VDD + 0.1 +0.1 −6 REF = VDD = 5 V VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V VDD = 5 V ± 5% fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 5 V, −60 dB input fIN = 20 kHz, VREF = 2.5 V +6 0.5 ±2 ±0.3 ±0.1 ±0.7 ±0.3 ±0.05 0 0 VREF VDD + 0.1 +0.1 −0.1 Min 16 16 −1 −3 ±1.6 ±3.5 ±0.7 ±1 0.5 ±2 ±0.3 ±0.1 ±0.7 ±0.3 ±0.05 0 0 +3 VREF VDD + 0.1 +0.1 −0.1 65 1 See the Analog Inputs section 16 −1 −2 ±30 ±1.6 ±3.5 250 200 1.8 C Grade Typ Max 0 −0.1 65 1 See the Analog Inputs section ±30 250 200 1.8 B Grade Typ Max 0 −0.1 65 1 See the Analog Inputs section 15 VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V Full-scale step Min 16 ±0.5 ±0.6 0.45 ±2 ±0.3 ±0.1 ±0.7 ±0.3 ±0.05 0 0 +1.5 +2 ±15 ±1.6 ±3.5 250 200 1.8 Unit Bits V V V dB nA Bits LSB 1 LSB LSB LSB ppm/°C mV mV ppm/°C LSB kSPS kSPS μs 90 90 92 91.5 93.5 dB 3 86 86 88 87.5 88.5 dB −110 dB −110 93.5 dB dB 33.5 dB 88.5 dB −115 dB −100 −100 89 −106 90 −106 92 91.5 32 86 Intermodulation Distortion 4 85.5 87.5 −110 1 87 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 μV. See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full scale. 2 3 Rev. B | Page 3 of 28 AD7685 VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay Conditions VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation ISINK = +500 μA ISOURCE = −500 μA TEMPERATURE RANGE 3 Specified Performance Min Typ 0.5 Max Unit VDD + 0.3 250 kSPS, REF = 5 V 50 V μA VDD = 5 V 2 2.5 MHz ns –0.3 0.7 × VIO −1 −1 0.3 × VIO VIO + 0.3 +1 +1 Serial 16 bits straight binary Conversion results available immediately after completed conversion 0.4 VIO − 0.3 Specified performance Specified performance 2.3 2.3 1.8 VDD and VIO = 5 V, 25°C VDD = 2.5 V, 100 SPS throughput VDD = 2.5 V, 100 kSPS throughput VDD = 2.5 V, 200 kSPS throughput VDD = 5 V, 100 kSPS throughput VDD = 5 V, 250 kSPS throughput TMIN to TMAX 1 1.4 1.35 2.7 4 10 −40 1 With all digital inputs forced to VIO or GND as required. During acquisition phase. 3 Contact sales for extended temperature range. 2 Rev. B | Page 4 of 28 5.5 VDD + 0.3 VDD + 0.3 50 V V μA μA V V 2.4 4.8 6 15 V V V nA μW mW mW mW mW +85 °C AD7685 TIMING SPECIFICATIONS −40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. Table 4. VDD = 4.5 V to 5.5 V 1 Parameter Conversion Time: CNV Rising Edge To Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 4.5 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with Busy Indicator) VIO Above 4.5 V VIO Above 2.3 V 1 See Figure 3 and Figure 4 for load conditions. Rev. B | Page 5 of 28 Symbol tCONV tACQ tCYC tCNVH tSCK tSCK tSCKL tSCKH tHSDO tDSDO Min 0.5 1.8 4 10 15 Typ Max 2.2 17 18 19 20 7 7 5 Unit μs μs μs ns ns ns ns ns ns ns ns ns 14 15 16 17 ns ns ns ns 15 18 22 25 ns ns ns ns ns ns ns ns ns ns 15 26 ns ns tEN tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 15 0 5 5 3 4 AD7685 −40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. Table 5. VDD = 2.3V to 4.5 V 1 Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 2.7 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with Busy Indicator) tSCKL tSCKH tHSDO tDSDO Min 0.7 1.8 5 10 25 Typ Max 3.2 29 35 40 12 12 5 Unit μs μs μs ns ns ns ns ns ns ns ns 24 30 35 ns ns ns 18 22 25 ns ns ns ns ns ns ns ns ns ns tEN tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 30 0 5 8 5 4 36 See Figure 3 and Figure 4 for load conditions. 70% VIO IOL 30% VIO tDELAY 1.4V TO SDO CL 50pF 500µA IOH tDELAY 2V OR VIO – 0.5V1 0.8V OR 0.5V2 2V OR VIO – 0.5V1 0.8V OR 0.5V2 NOTES 1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 4. Voltage Levels for Timing Figure 3. Load Circuit for Digital Interface Timing Rev. B | Page 6 of 28 02968-003 500µA 02968-002 1 Symbol tCONV tACQ tCYC tCNVH tSCK tSCK AD7685 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Analog Inputs IN+ 1 , IN−1, REF Supply Voltages VDD, VIO to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance θJC Thermal Impedance Lead Temperature Vapor Phase (60 sec) Infrared (15 sec) 1 Rating GND − 0.3 V to VDD + 0.3 V or ±130 mA −0.3 V to +7 V ±7 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 200°C/W (MSOP-10) 44°C/W (MSOP-10) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 215°C 220°C See the Analog Inputs section. Rev. B | Page 7 of 28 AD7685 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN+ 3 IN– 4 9 SDI TOP VIEW (Not to Scale) 8 SCK GND 5 7 SDO 6 CNV REF 1 10 VIO VDD 2 AD7685 9 SDI IN+ 3 TOP VIEW (Not to Scale) 8 SCK IN– 4 GND 5 7 SDO 6 CNV 02968-005 10 VIO AD7685 02968-004 REF 1 VDD 2 Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Figure 5. 10-Lead MSOP Pin Configuration Table 7. Pin Function Descriptions Pin No 1 Mnemonic REF Type 1 AI 2 3 4 5 6 VDD IN+ IN− GND CNV P AI AI P DI 7 8 9 SDO SCK SDI DO DI DI 10 VIO P Description Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. Power Supply. Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to VREF. Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. B | Page 8 of 28 AD7685 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 26). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level ½ LSB above analog ground (38.1 μV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by ENOB = (SINADdB − 1.76)/6.02 and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-(Noise + Distortion), SINAD SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB. Aperture Delay Aperture delay is a measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response The time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. B | Page 9 of 28 AD7685 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 1.0 0.5 0.5 DNL (LSB) 1.0 0 –0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 0 16384 32768 CODE 49152 POSITIVE DNL = +0.21LSB NEGATIVE DNL = –0.30LSB 1.5 65536 –2.0 02968-047 INL (LSB) 2.0 POSITIVE INL = +0.33LSB NEGATIVE INL = –0.50LSB 0 16384 Figure 7. Integral Nonlinearity vs. Code 250000 32768 CODE 49152 65536 02968-008 2.0 Figure 10. Differential Nonlinearity vs. Code 140000 VDD = REF = 5V 125055 204292 VDD = REF = 2.5V 120000 200000 100000 COUNTS COUNTS 150000 100000 80000 60966 59082 60000 40000 0 80E5 0 80E6 12 80E7 20000 20 0 0 0 80E8 80E9 80EA 80EB 80EC 80ED CODE IN HEX Figure 8. Histogram of a DC Input at the Code Center 0 –80 –100 –120 –140 –160 –180 0 20 40 60 80 FREQUENCY (kHz) 100 120 179 0 0 804E 804F 8050 8051 8052 8053 8054 8055 8056 8057 8058 CODE IN HEX 16384 POINT FFT VDD = REF = 2.5V fS = 250kSPS fIN = 20.45kHz SNR = 88.8dB THD = –103.5dB SFDR = –104.5dB SECOND HARMONIC = –112.4dB THIRD HARMONIC = –105.4dB –20 AMPLITUDE (dB OF FULL SCALE) –60 6956 213 0 02968-007 AMPLITUDE (dB OF FULL SCALE) –40 2 Figure 11. Histogram of a DC Input at the Code Center 8192 POINT FFT VDD = REF = 5V fS = 250kSPS fIN = 20.45kHz SNR = 93.3dB THD = –111.6dB SFDR = –113.7dB SECOND HARMONIC = –113.7dB THIRD HARMONIC = –117.6dB –20 8667 0 02968-009 0 27755 Figure 9. FFT Plot –40 –60 –80 –100 –120 –140 –160 –180 0 20 40 60 80 FREQUENCY (kHz) Figure 12. FFT Plot Rev. B | Page 10 of 28 100 120 02968-010 29041 02968-006 50000 AD7685 100 –90 17 –95 SNR –100 16 90 ENOB THD, SFDR (dB) SINAD ENOB (Bits) SINAD (dB) 95 15 14 85 –105 –110 THD –115 SFDR –120 2.7 3.1 3.5 3.9 4.3 4.7 REFERENCE VOLTAGE (V) 5.1 13 5.5 –130 2.3 02968-011 80 2.3 3.1 3.5 3.9 4.3 4.7 REFERENCE VOLTAGE (V) 5.1 5.5 Figure 16. THD, SFDR vs. Reference Voltage Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage 100 –60 95 –70 VREF = 5V, –10dB VREF = 5V, –1dB 90 –80 VREF = 5V, –1dB THD (dB) SINAD (dB) 2.7 02968-014 –125 85 VREF = 2.5V, –1dB VREF = 2.5V, –1dB –90 80 –100 75 –110 0 50 100 FREQUENCY (kHz) 150 200 –120 02968-012 70 0 50 Figure 14. SINAD vs. Frequency 100 FREQUENCY (kHz) 150 200 02968-015 VREF = 5V, –10dB Figure 17. THD vs. Frequency 100 –90 95 VREF = 5V –100 VREF = 2.5V THD (dB) VREF = 2.5V 85 –110 VREF = 5V 80 –120 70 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 Figure 15. SNR vs. Temperature –130 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 Figure 18. THD vs. Temperature Rev. B | Page 11 of 28 105 125 02968-016 75 02968-013 SNR (dB) 90 AD7685 1000 –105 fS = 100kSPS VDD = 5V OPERATING CURRENTS (µA) 94 SNR –110 92 THD (dB) 93 THD –115 91 750 VDD = 2.5V 500 250 –8 –6 –4 INPUT LEVEL (dB) –2 0 –120 0 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 02968-020 VIO 90 –10 02968-017 SNR REFERENCE TO FULL SCALE (dB) 95 Figure 22. Operating Currents vs. Temperature Figure 19. SNR and THD vs. Input Level 6 1000 5 fS = 100kSPS OFFSET, GAIN ERROR (LSB) 750 VDD 500 250 3.5 1 OFFSET ERROR 0 –1 –2 GAIN ERROR –3 –4 3.9 4.3 SUPPLY (V) 4.7 5.1 5.5 –6 –55 –35 –15 85 105 125 Figure 23. Offset and Gain Error vs. Temperature Figure 20. Operating Currents vs. Supply 25 1000 VDD = 2.5V, 85°C 20 tDSDO DELAY (ns) 750 500 250 15 VDD = 2.5V, 25°C 10 VDD = 5V, 85°C VDD = 5V, 25°C 5 VDD = 3.3V, 85°C VDD = 3.3V, 25°C VDD + VIO 0 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 02968-019 POWER-DOWN CURRENTS (nA) 5 25 45 65 TEMPERATURE (°C) 02968-021 3.1 02968-018 2.7 2 –5 VIO 0 2.3 3 0 0 20 40 60 80 SDO CAPACITIVE LOAD (pF) 100 120 Figure 24. tDSDO Delay vs. Capacitance Load and Supply Figure 21. Power-Down Currents vs. Temperature Rev. B | Page 12 of 28 02968-022 OPERATING CURRENTS (µA) 4 AD7685 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB REF 32,768C 16,384C LSB 4C 2C C SW+ C BUSY COMP GND 32,768C 16,384C 4C 2C C MSB CONTROL LOGIC OUTPUT CODE C LSB SW– 02968-023 CNV IN– Figure 25. ADC Simplified Schematic CIRCUIT INFORMATION CONVERTER OPERATION The AD7685 is a fast, low power, single-supply, precise 16-bit ADC using a successive approximation architecture. The AD7685 is a successive approximation ADC based on a charge redistribution DAC. Figure 25 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. The AD7685 is capable of converting 250,000 samples per second (250 kSPS) and powers down between conversions. When operating at 100 SPS, for example, it consumes typically 1.35 μW with a 2.5 V supply, ideal for battery-powered applications. The AD7685 provides the user with on-chip, track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7685 is specified from 2.3 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. It is housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines space savings and allows flexible configurations. It is pin-for-pin-compatible with the AD7686, AD7687, and AD7688. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN− captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part powers down and returns to the acquisition phase, and the control logic generates the ADC output code and a BUSY signal indicator. Because the AD7685 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. B | Page 13 of 28 AD7685 TYPICAL CONNECTION DIAGRAM The ideal transfer characteristic for the AD7685 is shown in Figure 26 and Table 8. Figure 27 shows an example of the recommended connection diagram for the AD7685 when multiple supplies are available. ADC CODE (STRAIGHT BINARY) Transfer Functions 111...111 111...110 111...101 000...010 000...001 –FS + 1 LSB +FS – 1 LSB +FS – 1.5 LSB –FS + 0.5 LSB 02968-024 000...000 –FS ANALOG INPUT Figure 26. ADC Ideal Transfer Function ≥7V REF1 5V 10µF2 100nF 1.8V TO VDD ≥7V 100nF REF VDD IN+ 0 TO VREF 3 ≤–2V AD7685 2.7nF 4 IN– GND VIO SDI SCK SDO 3- OR 4-WIRE INTERFACE5 CNV NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). 3. SEE DRIVER AMPLIFIER CHOICE SECTION. 4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5. SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE. Figure 27. Typical Application Diagram with Multiple Supplies Table 8. Output Codes and Ideal Input Voltages Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 1 2 Analog Input VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 μV 0V Digital Output Code Hexa FFFF 1 8001 8000 7FFF 0001 0000 2 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). This is also the code for an underranged analog input (VIN+ − VIN− below VGND). Rev. B | Page 14 of 28 02968-025 33Ω AD7685 ANALOG INPUTS Figure 28 shows an equivalent circuit of the input structure of the AD7685. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this will cause these diodes to begin to forward-bias and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from VDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. VDD D1 IN+ OR IN– CIN D2 02968-026 CPIN RIN GND During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 3 kΩ and is a lumped component made up of some serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. When the source impedance of the driving circuit is low, the AD7685 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency, as shown in Figure 30. –60 Figure 28. Equivalent Analog Input Circuit –70 –80 –90 RS = 250Ω –100 RS = 100Ω 80 RS = 50Ω RS = 33Ω –110 –120 VDD = 5V 50 40 1 10 100 FREQUENCY (kHz) 0 25 50 FREQUENCY (kHz) 75 100 Figure 30. THD vs. Analog Input Frequency and Source Resistance VDD = 2.5V 60 1000 10000 02968-027 CMRR (dB) 70 02968-028 THD (dB) This analog input structure allows the sampling of the differential signal between IN+ and IN−. By using this differential input, small signals common to both inputs are rejected, as shown in Figure 29, which represents the typical CMRR over frequency. For instance, by using IN− to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. Figure 29. Analog Input CMRR vs. Frequency Rev. B | Page 15 of 28 AD7685 DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT Although the AD7685 is easy to drive, the driver amplifier needs to meet the following requirements: The AD7685 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. • The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7685. Note that the AD7685 has a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. The noise coming from the amplifier is filtered by the AD7685 analog input circuit lowpass filter made by RIN and CIN or by an external filter, if one is used. Because the typical noise of the AD7685 is 35 μV rms, the SNR degradation due to the amplifier is ⎞ ⎟ ⎟ ⎟ ⎟ ⎠ If desired, smaller reference decoupling capacitor values down to 2.2 μF can be used with a minimal impact on performance, especially DNL. POWER SUPPLY • For ac applications, the driver should have a THD performance commensurate with the AD7685. Figure 17 shows the AD7685’s THD vs. frequency. • For multichannel, multiplexed applications, the driver amplifier and the AD7685 analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. Table 9. Recommended Driver Amplifiers The AD7685 is specified over a wide operating range from 2.3 V to 5.5 V. It has, unlike other low voltage converters, a noise low enough to design a 16-bit resolution system with low supply and respectable performance. It uses two power supply pins: a core supply VDD and a digital input/output interface supply VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the number of supplies needed, the VIO and VDD can be tied together. The AD7685 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 31, which represents PSRR over frequency. 110 100 90 VDD = 5V 80 Typical Application Very low noise and low power 5 V single-supply, low power 5 V single-supply, low power Low power, low noise, and low frequency Very low noise and high frequency Very low noise and high frequency Small, low power and low frequency High frequency and low power Rev. B | Page 16 of 28 70 VDD = 2.5V 60 50 40 30 1 10 100 FREQUENCY (kHz) 1000 Figure 31. PSRR vs. Frequency 10000 02968-029 where: f–3dB is the input bandwidth in MHz of the AD7685 (2 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/√Hz. Amplifier ADA4841-x AD8605, AD8615 AD8655 OP184 AD8021 AD8022 AD8519 AD8031 If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. PSRR (dB) SNRLOSS ⎛ ⎜ 35 = 20log ⎜ ⎜ π ⎜ 35 2 + f −3dB (Ne N )2 2 ⎝ When REF is driven by a very low impedance source, for example, a reference buffer using the AD8031 or the AD8605, a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. AD7685 The AD7685 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure 32. This makes the part ideal for low sampling rate (even a few Hz) and low batterypowered applications. 10000 OPERATING CURRENTS (µA) 1000 VDD = 5V VDD = 2.5V 100 10 1 VIO 0.1 1000 10000 SAMPLING RATE (SPS) 100000 02968-030 100 1000000 Figure 32. Operating Currents vs. Sampling Rate SUPPLYING THE ADC FROM THE REFERENCE For simplified applications, the AD7685, with its low operating current, can be supplied directly using the reference circuit, as shown in Figure 33. The reference line can be driven by either: • The system power supply directly. • A reference voltage with enough current output capability, such as the ADR43x. • A reference buffer, such as the AD8031, that can also filter the system power supply, as shown in Figure 33. 5V Though the AD7685 has a reduced number of pins, it offers substantial flexibility in its serial interface modes. The AD7685, when in CS mode, is compatible with SPI, QSPI, digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or ADSP-219x. This interface can use either 3-wire or 4-wire. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections, useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. The AD7685, when in chain mode, provides a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. 0.01 0.001 10 DIGITAL INTERFACE 5V The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. In either the CS mode or the chain mode, the AD7685 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a BUSY indicator, the user must time out the maximum conversion time prior to readback. The BUSY indicator feature is enabled as follows: • In the CS mode, if CNV or SDI is low when the ADC conversion ends (see Figure 37 and Figure 41). • In the chain mode, if SCK is high during the CNV rising edge (see Figure 45). 10Ω 5V 10kΩ 1µF AD8031 10µF 1µF 1 REF VDD VIO 1OPTIONAL REFERENCE BUFFER AND FILTER. 02968-031 AD7685 Figure 33. Example of Application Circuit Rev. B | Page 17 of 28 AD7685 valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE, NO BUSY INDICATOR This mode is usually used when a single AD7685 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 34, and the corresponding timing is given in Figure 35. CONVERT With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. Once a conversion is initiated, it will continue to completion irrespective of the state of CNV. For instance, it could be useful to bring CNV low to select other SPI devices, such as analog multiplexers, but CNV must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When conversion is completed, the AD7685 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is DIGITAL HOST CNV VIO SDI AD7685 DATA IN SDO 02968-032 SCK CLK Figure 34. CS Mode 3-Wire, No BUSY Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 14 tHSDO 16 tSCKH tDSDO tEN SDO 15 D15 D14 D13 tDIS D1 D0 Figure 35. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High) Rev. B | Page 18 of 28 02968-033 SCK AD7685 powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7685 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 36, and the corresponding timing is given in Figure 37. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV could be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7685 then enters the acquisition phase and CONVERT VIO DIGITAL HOST CNV VIO AD7685 DATA IN SDO SCK IRQ 02968-034 SDI 47kΩ CLK Figure 36. CS Mode 3-Wire with BUSY Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 tHSDO 15 16 17 tSCKH tDSDO SDO tDIS D15 D14 D1 D0 Figure 37. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High) Rev. B | Page 19 of 28 02968-035 SCK AD7685 conversion is complete, the AD7685 enters the acquisition phase and powers down. Each ADC result can be read by bringing low its SDI input, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge, or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7685 can be read. CS MODE 4-WIRE, NO BUSY INDICATOR This mode is usually used when multiple AD7685s are connected to an SPI-compatible digital host. A connection diagram example using two AD7685s is shown in Figure 38, and the corresponding timing is given in Figure 39. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the If multiple AD7685s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. CS2 CS1 CONVERT CNV SDI AD7685 DIGITAL HOST CNV SDO SDI AD7685 SCK SDO SCK 02968-036 DATA IN CLK Figure 38. CS Mode 4-Wire, No BUSY Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL SCK 1 2 14 3 tHSDO 16 17 18 D1 D0 D15 D14 30 31 32 D1 D0 tSCKH tDSDO tEN D15 D14 D13 tDIS 02968-037 SDO 15 Figure 39. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing Rev. B | Page 20 of 28 AD7685 as an interrupt signal to initiate the data readback controlled by the digital host. The AD7685 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or SDI going high, whichever is earlier, the SDO returns to high impedance. CS MODE 4-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7685 is connected to an SPI-compatible digital host, which has an interrupt input, and it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 40, and the corresponding timing is given in Figure 41. CS1 CONVERT VIO DIGITAL HOST CNV SDI AD7685 47kΩ DATA IN SDO SCK IRQ 02968-038 With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used CLK Figure 40. CS Mode 4-Wire with BUSY Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI tSCK tHSDICNV tSCKL 1 2 3 tHSDO 15 16 17 tSCKH tDSDO tDIS tEN SDO D15 D14 D1 Figure 41. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing Rev. B | Page 21 of 28 D0 02968-039 SCK AD7685 AD7685 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to readback the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate and, consequently, more AD7685s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. For instance, with a 5 ns digital host setup time and 3 V interface, up to eight AD7685s running at a conversion rate of 220 kSPS can be daisy-chained on a 3-wire port. CHAIN MODE, NO BUSY INDICATOR This mode can be used to daisy-chain multiple AD7685s on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7685s is shown in Figure 42, and the corresponding timing is given in Figure 43. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion and selects the chain mode. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the CONVERT SDI CNV AD7685 SDO DIGITAL HOST AD7685 SDI A B SCK SCK SDO DATA IN 02968-040 CNV CLK Figure 42. Chain Mode Connection Diagram SDIA = 0 tCYC CNV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV SCK 1 tHSCKCNV 2 3 14 15 tSSDISCK 16 17 18 DA15 DA14 30 31 32 DA1 DA0 tSCKH tHSDISCK tEN SDOA = SDIB DA15 DA14 DA13 DA1 DA0 DB15 DB14 DB13 DB1 DB0 tHSDO tDSDO SDOB Figure 43. Chain Mode Serial Interface Timing Rev. B | Page 22 of 28 02968-041 ACQUISITION tCONV AD7685 Figure 44) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host. The AD7685 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are then clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge allows a faster reading rate and, consequently, more AD7685s in the chain, provided the digital host has an acceptable hold time. For instance, with a 5 ns digital host setup time and 3 V interface, up to eight AD7685s running at a conversion rate of 220 kSPS can be daisy-chained to a single 3-wire port. CHAIN MODE WITH BUSY INDICATOR This mode can also be used to daisy chain multiple AD7685s on a 3-wire serial interface while providing a BUSY indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7685s is shown in Figure 44, and the corresponding timing is given in Figure 45. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the BUSY indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the nearend ADC (ADC C in CONVERT SDI AD7685 CNV SDO SDI AD7685 DIGITAL HOST CNV SDO SDI AD7685 A B C SCK SCK SCK DATA IN SDO IRQ 02968-042 CNV CLK Figure 44. Chain Mode with BUSY Indicator Connection Diagram tCYC ACQUISITION tCONV tACQ ACQUISITION CONVERSION tSSCKCNV SCK tHSCKCNV tSCKH 1 tEN SDOA = SDIB SDOB = SDIC 2 tSSDISCK 3 4 15 16 17 18 19 31 32 33 34 35 tSCKL tHSDISCK DA15 DA14 DA13 tDSDOSDI tSCK DA1 48 49 tDSDOSDI DA0 tHSDO tDSDO tDSDOSDI DB15 DB14 DB13 DB1 DB0 DA15 DA14 DA1 DA0 DC15 DC14 DC13 DC1 DC0 DB15 DB14 DB1 DB0 DA15 DA14 tDSDOSDI SDOC 47 tDSDOSDI Figure 45. Chain Mode with BUSY Indicator Serial Interface Timing Rev. B | Page 23 of 28 DA1 DA0 02968-043 CNV = SDIA AD7685 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7685 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7685 with all its analog signals on the left side and all its digital signals on the right side eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7685 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided The AD7685 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and connected with wide, low impedance traces. 02968-044 At least one ground plane should be used. It could be common or split between the digital and analog section. In the latter case, the planes should be joined underneath the AD7685. Figure 46. Example of Layout of the AD7685 (Top Layer) Finally, the power supplies VDD and VIO should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7685 and connected using short and wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. An example layout following these rules is shown in Figure 46 and Figure 47. Other recommended layouts for the AD7690 are outlined in the documentation of the evaluation board (EVAL-AD7685CB). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the universal evaluation control board (EVAL-CONTROL BRD3). Rev. B | Page 24 of 28 02968-045 EVALUATING THE PERFORMANCE OF THE AD7685 Figure 47. Example of Layout of the AD7685 (Bottom Layer) AD7685 TRUE 16-BIT ISOLATED APPLICATION EXAMPLE In applications where high accuracy and isolation are required, for example, power monitoring, motor control, and some medical equipment, the circuit given in Figure 48, using the AD7685 and the ADuM1402C digital isolator, provides a compact and high performance solution. Multiple AD7685s are daisy-chained to reduce the number of signals to isolate. Note that the SCKOUT, which is a readback of the AD7685’s clock, has a very short skew with the DATA signal. This skew is the channel-to-channel matching propagation delay of the digital isolator (tPSKCD). This allows running the serial interface at the maximum speed of the digital isolator (45 Mbits/s for the ADuM1402C), which would have been otherwise limited by the cascade of the propagation delays of the digital isolator. The complete analog chain runs on a 5 V single supply using the ADR391 low dropout reference voltage and the rail-to-rail CMOS AD8618 amplifier while offering true bipolar input range. 5V REF 5V 10µF ±10V INPUT 4kΩ 100nF 1kΩ 5V REF VDD VIO IN+ AD7685 2V REF IN– GND 5V 100nF SDO SCK CNV SDI 1/4 AD8618 5V REF ±10V INPUT VDD2 , VE2 GND1 GND2 VIA VOA VIB VOB VOC VIC VOD VID 2.7V TO 5V 100nF DATA SCKOUT SCKIN 5V 10µF 4kΩ VDD1 , VE1 100nF 1kΩ 5V REF VDD VIO IN+ AD7685 2V REF IN– GND SDO SCK CNV SDI CONVERT ADuM1402C 1/4 AD8618 5V REF 5V 10µF ±10V INPUT 4kΩ 100nF 1kΩ 5V REF VDD VIO IN+ AD7685 2V REF IN– GND SDO SCK CNV SDI 1kΩ 1kΩ 5V 1/4 AD8618 5V REF 5V REF 5V 10µF 1kΩ 5V REF VDD VIO IN+ AD7685 2V REF IN– GND SDO SCK CNV SDI ADR391 5V IN OUT GND 1kΩ 2V REF 4kΩ 10µF 100nF 02968-046 ±10V INPUT 4kΩ 100nF 1/4 AD8618 Figure 48. A True 16-Bit Isolated Simultaneous Sampling Acquisition System Rev. B | Page 25 of 28 AD7685 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 6 1 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.05 0.33 0.17 SEATING PLANE 0.23 0.08 0.80 0.60 0.40 8° 0° COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 49.10-Lead Micro Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.00 BSC SQ PIN 1 INDICATOR 1 10 1.50 BSC SQ 0.50 BSC (BOT TOM VIEW) 6 0.80 0.75 0.70 SEATING PLANE 0.80 MAX 0.55 TYP SIDE VIEW 0.30 0.23 0.18 2.48 2.38 2.23 EXPOSED PAD TOP VIEW 0.50 0.40 0.30 5 1.74 1.64 1.49 0.05 MAX 0.02 NOM PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES 0.20 REF Figure 50. 10-Terminal Quad Flat No Lead Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body (CP-10-9) Dimensions shown in millimeters Rev. B | Page 26 of 28 022207-A INDEX ARE A AD7685 ORDERING GUIDE Model AD7685ACPZRL 1 AD7685ACPZRL71 AD7685ARM AD7685ARMRL7 AD7685ARMZ1 AD7685ARMZRL71 AD7685BCPZRL1 AD7685BCPZRL71 AD7685BRM AD7685BRMRL7 AD7685BRMZ1 AD7685BRMZRL71 AD7685CCPZRL1 AD7685CCPZRL71 AD7685CRM AD7685CRMRL7 AD7685CRMZ1 AD7685CRMZRL71 EVAL-AD7685CB 2 EVAL-AD7685CBZ1, 2 EVAL-CONTROL BRD2 3 EVAL-CONTROL BRD33 1 2 3 Integral Nonlinearity ±6 LSB max ±6 LSB max ±6 LSB max ±6 LSB max ±6 LSB max ±6 LSB max ±3 LSB max ±3 LSB max ±3 LSB max ±3 LSB max ±3 LSB max ±3 LSB max ±2 LSB max ±2 LSB max ±2 LSB max ±2 LSB max ±2 LSB max ±2 LSB max No Missing Code 15 Bits 15 Bits 15 Bits 15 Bits 15 Bits 15 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 10-Lead QFN (LFCSP_WD) 10-Lead QFN (LFCSP_WD) 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead QFN (LFCSP_WD) 10-Lead QFN (LFCSP_WD) 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead QFN (LFCSP_WD) 10-Lead QFN (LFCSP_WD) 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Evaluation Board Controller Board Controller Board Package Option CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 Branding C4H C4H C37 C37 C4H C4H C3D C3D C01 C01 C3D C3D C4J C4J C00 C00 C4J C4J Z = RoHS Compliant Part. This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. Rev. B | Page 27 of 28 Ordering Quantity Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 AD7685 NOTES ©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02968-0-3/07(B) Rev. B | Page 28 of 28