Application Note 19 June 1986 LT1070 Design Manual Carl Nelson INTRODUCTION Three terminal monolithic linear voltage regulators appeared almost 20 years ago, and were almost immediately successful for a variety of reasons. In particular, there were relatively few engineers capable of designing a good linear voltage regulator. The new devices were also easy to use, and inexpensive. In currently popular parlance they were “expert systems,” containing a good deal of their designer’s knowledge in silicon form. Because of these advantages, the regulators quickly eclipsed discrete and earlier monolithic building blocks and dominated the market. More recently, there has been increasing interest in switching-based regulators. Switching regulators, with their high efficiency and small size, are increasingly desirable as overall package sizes have shrunk. Unfortunately, switching regulators are also one of the most difficult linear circuits to design. Mysterious modes, sudden failures, peculiar regulation characteristics and just plain explosions are common occurrences during the design of a switching regulator. Most switching regulator ICs are building blocks. Many discrete components are required, and substantial expertise is assumed on the part of the user. Some newer devices include the power switch on the die, but still require a significant amount of engineering to apply. Finally, there has been a notable lack of comprehensive and practical application literature support from manufacturers. These considerations are reminiscent of the state of linear regulator design when the first three terminal monolithic regulators appeared. Given this historical lesson, the LT®1070 five terminal switching regulator has been designed for ease of use and economy. It does not require the user to be well-schooled in switching regulator design, and is versatile enough to be used in all the popular switching regulator configurations. To obtain maximum user benefit, a significant applications effort has been associated with this part. This note covers both ancillary tutorial material as well as direct operating considerations for the part. It is intended to be used “as required.” For those in a mission-oriented hurry, much of the discussion can be ignored, and breadboards constructed with a high probability of success. The more academically inclined reader may choose to peruse the material more carefully. Either approach is valid and the note is intended to satisfy both. — Jim Williams , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. an19fc AN19-1 Application Note 19 Notes an19fc AN19-2 Application Note 19 TABLE OF CONTENTS PREFACE ............................................................................................................................................... AN19-4 LT1070 OPERATION .............................................................................................................................. AN19-7 BLOCK DIAGRAM .................................................................................................................................. AN19-7 PIN FUNCTIONS .................................................................................................................................... AN19-8 BASIC SWITCHING REGULATOR TOPOLOGIES .................................................................................. AN19-12 APPLICATION CIRCUITS: Boost Mode ..................................................................................................................................... AN19-17 Negative Buck Converter.................................................................................................................. AN19-21 Negative-to-Positive Buck-Boost Converter ..................................................................................... AN19-24 Positive Buck Converter ................................................................................................................... AN19-27 Flyback Converter ............................................................................................................................ AN19-30 Totally Isolated Converter ................................................................................................................ AN19-35 Positive Current-Boosted Buck Converter ........................................................................................ AN19-40 Negative Current-Boosted Buck Converter....................................................................................... AN19-41 Negative Input/Negative Output Flyback Converter .......................................................................... AN19-42 Positive-to-Negative Flyback Converter ........................................................................................... AN19-42 Voltage-Boosted Boost Converter .................................................................................................... AN19-43 Negative Boost Converter ................................................................................................................ AN19-44 Positive-to-Negative Buck Boost Converter ..................................................................................... AN19-44 Current-Boosted Boost Converter .................................................................................................... AN19-44 Forward Converter ........................................................................................................................... AN19-45 FREQUENCY COMPENSATION ............................................................................................................ AN19-48 EXTERNAL CURRENT LIMITING ......................................................................................................... AN19-51 DRIVING EXTERNAL TRANSISTORS ................................................................................................... AN19-53 OUTPUT RECTIFYING DIODE .............................................................................................................. AN19-54 INPUT FILTERS ................................................................................................................................... AN19-56 EFFICIENCY CALCULATIONS ............................................................................................................... AN19-58 OUTPUT FILTERS ................................................................................................................................ AN19-59 INPUT AND OUTPUT CAPACITORS ..................................................................................................... AN19-60 INDUCTOR AND TRANSFORMER BASICS ........................................................................................... AN19-61 HEAT SINKING INFORMATION ............................................................................................................ AN19-70 TROUBLESHOOTING HINTS ................................................................................................................ AN19-70 SUBHARMONIC OSCILLATIONS ......................................................................................................... AN19-72 APPENDICES Absolute Maximum Ratings ............................................................................................................. AN19-74 Package/Order Information .............................................................................................................. AN19-74 Electrical Characteristics .................................................................................................................. AN19-74 Typical Performance Characteristics................................................................................................ AN19-76 Core and Inductor/Transformer Manufacturers ............................................................................... AN19-79 Bibliography .................................................................................................................................... AN19-79 Package Drawings ........................................................................................................................... AN19-80 an19fc AN19-3 Application Note 19 PREFACE Smaller Versions of the LT1070 Since this application note was written, several new versions of the LT1070 have been developed. The LT1071 and LT1072 are identical to the LT1070 except for switch current ratings, 2.5A and 1.25A, respectively. Designs which result in lower switch currents can take advantage of the cost savings of these smaller chips. Design equations for the LT1071 and LT1072 are identical to the LT1070 with the following exceptions: Peak Switch Current (IP) Switch “On” Resistance (R) VC Pin to Switch Current Transconductance = 5A = 2.5A = 1.25A LT 1070 LT1071 LT1072 ≈ 0.2Ω ≈ 0.4Ω ≈ 0.8Ω LT1070 LT1071 LT1072 ≈ 8A/V ≈ 4A/V ≈ 2A/V LT1070 LT1071 LT1072 Also available in the 2nd quarter of 1989 will be 100kHz versions of the LT1070/LT1071/LT1072. Inductance Calculations Feedback from readers of AN19 shows that there is confusion about the use of ΔI to calculate inductance values. ΔI is the change in inductor or primary current during switch “on” time, and the suggested value is approximately 20% of the peak current rating of the LT1070 switch (5A), or in some cases, 20% of the average inductor current. This 20% rule-of-thumb is designed to give near maximum output power for a given switch current rating. If maximum output power is not needed, much smaller inductors/transformers may be used by allowing ΔI to increase. The design approach is to calculate peak inductor/switch current (IP) using the formulas provided in AN19, with L = ∞. This formula assumes continuous mode operation. If ΔI, as calculated by this formula, exceeds IP, it may be possible to go to discontinuous mode operation, with further reductions in inductance. Discontinuous mode requires higher switch currents and not all the AN19 topologies show design equations for this mode, but it should definitely be considered for very low output powers or where inductor/transformer size is critical. All topologies work well in discontinuous mode with the exception of fully isolated flyback. Drawbacks of discontinuous mode include higher output ripple and slightly lower efficiency. Example 1: Negative buck converter with VIN = – 24V, VOUT = – 5V and IOUT = 1.5A, IP(Equation 37) = IOUT + (VIN − VOUT)(VOUT) = IOUT = 1.5A 2 • VIN • f • (L ≈ ∞) ΔIMAX = 2(ISW – IP) = 2(5 – 1.5) = 7A (LT1070) = 2(2.5 – 1.5) = 2A 9(LT1071) = 2(1.25 – 1.5) - N.A. (LT1072) The LT1072 is too small (IP > ISW), so select the LT1071, which yields a maximum ΔI of 2A. A conservative value of actual ΔI is selected at 1A. This allows room for efficiency losses and variations in component values. Using Equation 37: L= (VIN − VOUT)(VOUT) = (24 − 5)(5) = 99μH VIN(ΔI) • f 24(1) • 40k Example 2: Flyback converter with VIN = 6V, VOUT = ±15V at 35mA and 5V at 0.2A, N = 0.4 (primary to 5V secondary). For calculations, the entire output power of 2.05W is referred to the 5V secondary, yielding one value for N(0.4), VOUT (5V) and IOUT = 0.41A. Then compare this current to the peak switch current. The difference is the “room” allowable for ΔI; ΔIMAX = 2(ISWITCH(PEAK) – IP) an19fc AN19-4 Application Note 19 Using Equation 79: ( )( ) )( VIN VOUT ⎛V ⎞ I IP = OUT ⎜ OUT + N⎟ + E ⎝ VIN ⎠ 2 • f VOUT + N VIN L = ∞ ( ) ⎞ 0.41A ⎛ 5V = + 0 . 4 ⎟ = 0.674A 0.75 ⎜⎝ 6V ⎠ The LT1072 is large enough to handle this current, yielding; ΔIMAX = 2(1.25A – 0.674A) = 1.15A Using a conservative value of 0.7A for ΔI (note that this is 56% of the 1.25A Max LT1072 switch current, not 20%), and Equation 77, yields: L= (VIN)(VOUT) = (6)(5) = 145μH ΔI • f(VOUT + N VIN) (0.7)(40k)(5 + 0.4 • 6) Protecting the Magnetics A second problem for LT1070 designers has been protection of the magnetics under overload or short-circuit conditions. Physical size restraints often require inductors or transformers which are not specified to handle the full current limit values of the LT1070. This problem can be handled in several ways. 1. Use an LT1071 or LT1072 if full load current requirements allow it. 2. Take advantage of the fact that the LT1070 current limit drops at higher temperatures. The worst-case current limit values shown on the old data sheets allow for both temperature extremes with one specification. New data sheets will specify a maximum of 10A for the LT1070, 5A for the LT1071 and 2.5A for the LT1072 at temperatures of 25°C or higher. Be aware that the temperature dependence of current limit has been improved considerably on the LT1070 since the origi- nal data sheet was printed. The old value was greater than – 0.3%/°C, while the new figure is under – 0.1%/°C. The current limit graphs on the new data sheets reflect this improved characteristic. 3. Reconsider the necessity of limiting the inductor/ transformer current to the manufacturers’ specification. Maximum current ratings in many cases are determined by core saturation considerations. Allowing the core to saturate does not harm the core. Core or winding damage occurs only if temperatures rise so far that material properties are permanently altered. Core saturation used to be considered a “fatal” condition for conventional switchers because currents would “run away” and destroy switches or diodes. The LT1070 limits current on an instantaneous cycle-by-cycle basis, preventing current “run away” even with grossly overdriven cores. The major consideration then is the heating effect of the winding current (I2R). Under short-circuit conditions, winding currents in inductors are nearly constant at the current limit value of the LT1070. Transformer secondary winding currents are nearly constant at 1/N times the LT1070 current limit. This assumes that the core is not heavily saturated. If the core saturates significantly below the current limit values, RMS winding current will be significantly lower than the current limit. The best way to resolve this complex situation is to actually measure core/winding temperature with a thermocouple under overload conditions. The thermocouple should be “buried” as deeply as possible in the windings and/or core to reflect peak temperatures. The magnetic and electric fields generated by the switching may affect the thermocouple meter. If this occurs, simply check the temperature periodically by turning off power. Consult with the magnetics manufacturer to determine peak allowable temperatures, with permanent damage as the criteria, not performance specifications. The major failure mode is winding shorts caused by insulation melting. High temperature insulation is available from most manufacturers. an19fc AN19-5 Application Note 19 New Switch Current Specification The LT1070 was specified at 5A peak switch current, for duty cycles of 50% or less. At higher duty cycles the peak current was limited to 4A. This abrupt change in specification at 50% duty cycle was bothersome because many designs operate near 50% duty cycle and require maximum possible output power. To solve this problem, switch current limit on new data sheets will be specified as a linearly decreasing function, from 5A at 50% duty cycle to 4A at 80% duty cycle. The LT1071 and LT1072 will also be specified this way. High Supply Voltages It has become apparent that many applications for the LT1070 have maximum input voltages which exceed 40V. The straightforward approach is to use the “HV” devices that are specified at 60V, but in some cases the standard part can be used at lower cost simply by dropping supply voltage with a Zener diode as shown. The LT1070 supply pin (VIN) requires only a few volts to operate, so in most cases the unregulated input voltage range is not compromised with this Zener. Zener dissipation can be calculated from IZ ≈ 6mA + ISW(0.0015 + DC/40): ISW = LT1070 average switch current during “on” time DC = duty cycle For ISW = 4A, DC = 30%; IZ = 42mA A 20V Zener would dissipate (20)(42) = 0.84W. Note that this power would be dissipated anyway in the LT1070, so no loss in efficiency occurs. The resistor, RZ, is necessary for start-up. Without it, a latch-off condition exists where the VIN pin sits more than 16V negative with respect to the switch pin. If the LT1070 is not switching and the FB pin is below 0.5V, the LT1070 is in the “isolated flyback” mode where it is trying to regulate the VIN -to-VSW voltage. When this voltage exceeds 16V, the regulator thinks it should reduce duty cycle to zero, resulting in a permanent “noswitching” state. RZ forces the VIN pin to rise enough to initiate start-up. The user need not be concerned that the VIN-to-ground pin voltage exceeds 40V during this state because RZ is too large to allow harmful currents to flow. Some attention needs to be paid to CZ. The LT1070 is very tolerant of noise and ripple on the VIN pin, but CZ may be necessary in some applications. The problem is that D1 must charge CZ when power is applied. If power comes up very rapidly, D1 might exceed its one cycle surge rating. V+ D1 ≈ 20V RZ 1k 0.5W + CIN VIN VSW CZ (OPTIONAL) LT1070 FB GND AN19 F00 Discontinuous “Oscillations” (Ringing) Many customers have called about oscillations occurring on the switch pin during a portion of the switch “off” time. These are not oscillations. They are a damped ringing caused by the transition to a zero-current state in the inductor or transformer primary. At light loads, or with low inductance values, inductor current will drop to zero during switch off time. This causes the inductor voltage to collapse toward zero. In doing so, however, energy is transferred back to the inductor from the parasitic capacitance of the switch, inductor, and catch diode. The inductor and capacitance form a parallel resonant tank which “rings.” This ringing is not harmful as long as its peak amplitude does not result in a negative voltage on the switch pin. It can be damped, if desired, by paralleling the inductor/primary with a series R/C damper, typically 100Ω to 1kΩ, and 500pF to 5000pF. Typical undamped ringing frequency is 100kHz to 1MHz. an19fc AN19-6 Application Note 19 LT1070 OPERATION The LT1070 is a current mode switcher. This means that switch duty cycle is directly controlled by switch current rather than by output voltage. Referring to the Block Diagram, the switch is turned “on” at the start of each oscillator cycle. It is turned “off” when switch current reaches a predetermined level. Control of output voltage is obtained by using the output of a voltage-sensing error amplifier to set current trip level. This technique has several advantages. First, it has immediate response to input voltage variations, unlike ordinary switchers which have notoriously poor line transient response. Second, it reduces the 90° phase shift at midfrequencies in the energy storage inductor. This greatly simplifies closedloop frequency compensation under widely varying input voltage or output load conditions. Finally, it allows simple pulse-by-pulse current limiting to provide maximum switch protection under output overload or short conditions. A low dropout internal regulator provides a 2.3V supply for all internal circuitry on the LT1070. This low dropout design allows input voltage to vary from 3V to 60V with virtually no change in device performance. A 40kHz oscillator is the basic clock for all internal timing. It turns “on” the output switch via the logic and driver circuitry. Special adaptive antisat circuitry detects onset of saturation in the power switch and adjusts driver current instantaneously to limit switch saturation. This minimizes driver dissipation and provides very rapid turn-off of the switch. A 1.2V bandgap reference biases the positive input of the error amplifier. The negative input is brought out for output voltage sensing. This feedback pin has a second function; when pulled low with an external resistor, it programs the LT1070 to disconnect the main error amplifier output and connects the output of the flyback amplifier to the comparator input. The LT1070 will then regulate the value of the flyback pulse with respect to the supply voltage. This flyback pulse is directly proportional to output voltage in the traditional transformer coupled flyback topology regulator. By regulating the amplitude of the flyback pulse, the output voltage can be regulated with no direct connection between input and output. The output is fully floating up to the breakdown voltage of the transformer windings. Multiple floating outputs are easily obtained with additional windings. A special delay network inside the LT1070 ignores the leakage inductance spike at the leading edge of the flyback pulse to improve output regulation. The error signal developed at the comparator input is brought out externally. This pin (VC) has four different functions. It is used for frequency compensation, current limit adjustment, soft starting and total regulator shutdown. During normal regulator operation this pin sits at a voltage between 0.9V (low output current) and 2V (high output current). The error amplifiers are current output (gm) types, so this voltage can be externally clamped for adjusting current limit. Likewise, a capacitor coupled external clamp will provide soft start. Switch duty cycle goes to zero if the VC pin is pulled to ground through a diode, placing the LT1070 in an idle mode. Pulling the VC pin below 0.15V causes total regulator shutdown, with only 50μA supply current for shutdown circuitry biasing. Block Diagram VIN 16V 2.3V REG SWITCH OUT FLYBACK ERROR AMP 400kHz OSC LOGIC MODE SELECT DRIVER 5A, 75V SWITCH ANTISAT COMP – FB ERROR + AMP VC + SHUTDOWN CIRCUIT 1.24V REF CURRENT AMP – GAIN ≈6 0.02Ω 0.15V AN19 BD an19fc AN19-7 Application Note 19 PIN FUNCTIONS Ground Pin Input Supply (VIN) The ground pin (case) of the LT1070 is important because it acts as both the negative sense point for the internal error amplifier and as the high current path for the 5A switch. This is not normally good design practice, but was necessary in a 5-pin package configuration. To avoid degradation of load regulation, Kelvin connections should be made to the ground pin. This is done on the TO-3 package by tying one end of the package to power ground and the other end to the feedback divider resistor (analog ground). This is illustrated in Figure 2. The LT1070 is designed to operate with input voltages from 3V to 40V (standard) or 60V (HV units). Supply current is essentially flat over this range at about 6mA (with zero output current). With increasing switch current, the supply current (during switch on-time) increases at a rate approximately 1/40 of switch current, corresponding to a forced hFE of 40 for the switch. Undervoltage lockout is incorporated on the LT1070 by sensing saturation of the lateral PNP pass transistor which drives an internal 2.3V regulator. A remote collector on this transistor conducts current and locks out the switch for input voltages below 2.5V. No hysteresis is used to maximize the useful range of input voltage. Operating the regulator right at the 2.5V threshold may result in a “burping” action as the LT1070 turns on and off in response to wobbles in input voltage, but this will not harm the device. External undervoltage lockout can be added if it is desirable to raise the threshold voltage. The circuit shown in Figure 1 is one example of how to implement this. The threshold of this circuit is approximately VZ + 1.5V. Below that voltage, D2 pulls the VC pin low to shut off the regulator. For best load regulation, the resistance in the switch current path must be kept low. 0.01Ω of wire resistance creates 50mV drop at 5A switch current. This is a 1% change in a 5V output, and actually causes the output to increase with increasing load current. With the TO-220 package, (Figure 3) connect the feedback resistor directly to the ground pin with a separate wire if no case connection is made. The case can be used as a second ground pin if desired. Avoid long wire runs to the ground pin to minimize load regulation effects and inductive voltages created by the high di/dt switch current. A ground plane will keep EMI to a minimum VIN LT1070 VZ GND FB PIN VC D2 SWITCH CURRENT PATH—KEEP RESISTANCE TO A MINIMUM 1.5k AN19 F01 –VIN FEEDBACK DIVIDER LOAD CURRENT PATH—KEEP RESISTANCE TO A MINIMUM TO OUTPUT (+) TO OUTPUT GND AN19 F02 Figure 1. External Undervoltage Lockout Figure 2 an19fc AN19-8 Application Note 19 SEPARATE GROUND PATH GND VC FB TO OUTPUT OUTPUT DIVIDER VSW GND VIN VC FB TO OUTPUT SWITCH CURRENT PATH—KEEP RESISTANCE LOW VSW VIN SWITCH CURRENT PATH AN19 F03a AN19 F03b Figure 3 Feedback Pin The feedback pin is the inverting input to a single stage error amplifier. The noninverting input to this amplifier is internally tied to a 1.244V reference as shown in Figure 4. Input bias current of the amplifier is typically 350nA with the output of the amplifier in its linear region. The amplifier is a gm type, meaning that it has high output impedance with controlled voltage-to-current gain (gm ≈ 4400μmhos). DC voltage gain with no load is ≈ 800. 2.3V TO LOGIC STEERING Q53 30Ω – FEEDBACK PIN ERROR AMP + VC PIN ≈ 1V 5.6V 1.244V GND PIN AN19 F04 Figure 4 The feedback pin has a second function; it is used to program the LT1070 for normal or flyback-regulated operation (see description of block diagram). In Figure 4, Q53 is biased with a base voltage approximately 1V. This clamps the feedback pin to about 0.4V when current is drawn out of the pin. A current of ≈10μA or higher through Q53 forces the regulator to switch from normal operation to flyback mode, but this threshold current can vary from 3μA to 30μA. The LT1070 is in flyback mode during normal start-up until the feedback pin rises above 0.45V. The resistor divider used to set output voltage will draw current out of the feedback pin until the output voltage is up to about 33% of its regulated value. If it is desired to run the LT1070 in the fully isolated flyback mode, a single resistor is tied from the feedback pin to ground. The feedback pin then sits at a voltage of ≈ 0.4V for R = 8.2k. The actual voltage depends on resistor value since the feedback pin has about 200Ω output impedance in this mode. 500μA in the resistor will drop the feedback pin voltage from 0.4V to 0.3V. Minimum current through the resistor to guarantee flyback operation is 50μA. Actual resistor value is chosen to fine-trim flyback regulated voltage. (See discussion of isolated flyback mode operation and graphs of feedback pin characteristics.) an19fc AN19-9 Application Note 19 An internal 30Ω resistor and 5.6V Zener protect the feedback pin from overvoltage stress. Maximum transient voltage is ±15V. This high transient condition most commonly occurs during fast fall time output shorts if a feedforward capacitor is used around the feedback divider. If a feedforward capacitor is used for DC output voltages greater than 15V, a resistor equal to VOUT/20mA should be used between the divider node and the feedback pin as shown in Figure 5. Keep in mind when using the LT1070 that the feedback pin reference voltage is referred to the ground pin of the regulator, and the ground pin can have switch currents exceeding 5A. Any resistance in the ground pin connection will degrade load regulation. Best regulation is obtained by tying the grounded end of the feedback divider directly to the ground pin of the LT1070, as a separate connection from the power ground. This limits output voltage errors to just the drop across the ground pin resistance instead of multiplying it by the feedback divider ratio. See discussion of ground pin. VOUT *R = TO LT1070 FEEDBACK PIN C VOUT 20mA 1.24k *REQUIRED FOR VOUT > 15V FEEDFORWARD CAPACITOR USED FOR IMPROVED LOOP TRANSIENT RESPONSE OR SOFT START AN19 F05 Figure 5 Compensation Pin (VC) The VC pin is used for frequency compensation, current limiting, soft start and shutdown. It is the output of the error amplifier and the input of the current comparator. The error amplifier circuit is shown in Figure 6. Q57 and Q58 form a differential input stage whose collector currents are inverted and multiplied times four by Q55 and Q56. Q55 current is further inverted by Q60 and Q61 to generate a current fed balanced output which can swing from the 2.3V rail down to a clamp level of ≈0.4V as set by 2.3V S1 30μA Q55 Q56 1.244V Q57 Q58 FB PIN Q62 TO SHUTDOWN CIRCUIT FROM FLYBACK AMPLIFIER S2 Q18 VC PIN R21 3k Q45 60μA Q60 Q61 Q32 Q24 S3 AN19 F06 Figure 6. Error Amplifier R21 and Q62. The 60μA tail current of the input transistors sets the gm of the error amplifier at 4400μmhos. Voltage gain with no load is limited by transistor output impedance at ≈800. Maximum source and sink current is ≈220μA. The voltage on the VC pin determines the current level at which the output switch will turn off. For VC voltage below 0.9V (at 25°C), the output switch will be totally off (duty cycle = 0). Above 0.9V, the switch will turn on at each oscillator cycle, then turn off when switch current reaches a trip level set by VC voltage. This trip level is zero at VC = 0.9V, and increases to about 9A when VC reaches its upper clamp level of 2V. These numbers are based on a duty cycle of 10%. Above 10%, switch turn-off is a function of both switch current and time. The time dependence is caused by a small ramp fed into the current amplifier input. This ramp starts at ≈ 40% duty cycle, and is the source of the bend in the VC vs duty cycle graph shown in Figure 7. This ramp is used to prevent a phenomenon peculiar to “current mode” switching regulators known as subharmonic oscillation. See section on Subharmonic Oscillations for further details. A second amplifier output is also tied to the VC pin. This “flyback mode” amplifier is turned on only when current is drawn out of the feedback pin. This condition occurs during start-up in the normal mode until the feedback divider has raised the voltage at the feedback pin above 0.45V. an19fc AN19-10 Application Note 19 100 Output Pin TJ = 25°C The VSW pin of the LT1070 is the collector of the internal NPN power switch. This NPN has a typical on-resistance of 0.15Ω and a breakdown voltage (BVCBO) of 85V. Very fast switching times and high efficiency are obtained by using a special driver loop which automatically adapts base drive current to the minimum required to keep the switch in a quasi-saturation state. This loop is shown in Figure 8. DUTY CYCLE (%) 80 1A 2A 5A 60 ISWITCH = 0 40 20 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VC VOLTAGE (V) 2.0 2.2 LTXXXX • AN19 F07 Figure 7. Duty Cycle vs VC Voltage It is a permanent condition when the LT1070 is programmed for isolated flyback mode by tying a single resistor from the feedback pin to ground. In the isolated flyback mode, S1 is closed and the feedback pin is low, totally disabling the main amplifier. S2 and S3 are turned on only during the “off” state of the output power transistor and then, only after a 1.5μs delay following output transistor turn-off. This prevents transient flyback spikes from causing poor regulation. S2 current is fixed at 30μA. S3 current can rise to a maximum of ≈ 70μA, allowing the VC pin to source 30μA and sink 40μA in the flyback mode. gm of the flyback amplifier is typically 300μmho. When the VC pin is externally pulled below 0.15V, a shutdown circuit is activated. Q24 and Q18 perform this function. Q24 is a special “high VBE” diode whose forward voltage is about 150mV higher than Q18 VBE. Pulling current out of Q18 activates shutdown and turn off all internal regulator functions except for a 50μA to 100μA trickle current needed to bias Q18 and Q24. See characteristic curves for details of the V/I properties of the VC pin in shutdown. Q104 is the power switch. Its base is driven by Q101, whose collector is returned to VIN. Q101 is turned on and off by Q102. In parallel with Q102 is a second, larger transistor (Q103) which pulls high reverse base current out of Q104 for rapid switch turn-off. The key element in the loop is the extra emitter on Q104. This emitter carries no current when Q104 collector is high (unsaturated). In this condition, the driver, Q101, can deliver very high base drive to the switch for fast turn-on. When the switch saturates, the extra emitter acts as a collector and pulls base current away from the driver. This linear feedback loop servos itself to keep the switch just at the edge of saturation. Very low switch currents result in near-zero driver current, and high switch currents automatically increase driver current as necessary. The ratio of switch current to driver current is approximately 40:1. This ratio is determined by the sizing of the extra emitter and the value of I1. The quasi-saturation state of the switch permits rapid turn-off without the need for reverse baseemitter voltage drive. VIN I1 ≈2mA Q101 Q104 Q102 Loop frequency compensation can be performed with an RC network connected from the VC pin to ground. An optional compensation is to connect the RC network between the VC pin and the feedback pin. See Loop Frequency Compensation section. VSW Q103 GROUND PIN AN19 F08 Figure 8 an19fc AN19-11 Application Note 19 Also tied to the VSW pin is the input circuitry for the flyback mode error amplifier as shown in Figure 9. This circuitry draws no current from the VSW pin when the switch pin is less than 16V above VIN because the diodes block current. When VSW is more than 16V above VIN, ≈ 500μA is drawn out of the switch pin because the reference diodes (D1 and D2) and Q10 turn on. This 500μA current level is set by the ratio of collector areas on the 2-collector lateral PNP Q10 and the value of I2. Q9 is reverse biased in this state. The 16V transition point sets the flyback mode reference voltage. The flyback reference voltage can be increased above 16V by drawing additional current through R1 via Q52. The amplitude of this current is determined by the size of the resistor tied to the feedback pin. See discussion in Isolated Flyback Mode Operation. D1 7V VIN D2 7V Q7 VSW Buck Converter Figure 10a shows the basic buck topology. S1 and S2 open and close alternately so that the voltage applied to L1 is either VIN or zero. DC output voltage is then the average voltage applied to L1. If t1 is the time S1 is closed, and t2 is the time it is open, VOUT is equal to: VOUT = VIN ( )( ) t1 = VIN DC t1 + t2 (1) where, by convention, duty cycle (DC) is defined as the ratio of t1 to t1 + t2; DC = t1 t1 + t2 (2) Note that the definition of duty cycle allows only for values between 0 and 1. The formula for VOUT therefore shows a basic property of buck converters; the output voltage is always less than the input voltage. R1 7k Q9 Q10 TO Q52 I2 Q104 TO REMAINDER OF FLYBACK MODE CIRCUITRY DRIVING VC PIN this covers nearly all the low to medium power DC/DC conversion requirements. AN19 F09 Figure 9 BASIC SWITCHING REGULATOR TOPOLOGIES There are many possible switching regulator configurations, or “topologies.” In any particular regulator requirement, the possible choices are narrowed somewhat by constraints of polarity, voltage ratio, and fault conditions (simple boost regulators cannot be current limited), but this may still leave the designer with several choices. To convert 28V to 5V, for instance, the list of possible topologies includes buck, flyback, forward and current boosted buck. The following discussion of topologies is limited to those which can be realized with the LT1070, but This simple formula also tells much about switching regulators in general. The most important point is what is not in the equation, and that includes L1, C1, frequency and load current. To a first approximation, the output voltage of a switching regulator depends only on the duty cycle of the switching network and input voltage. This is a very important point which must be kept firmly in mind when analyzing switching regulators. Diodes may be used to replace switches when unidirectional current flow exists. In Figures 10b and 10c, singleswitch buck regulators are shown with diodes used to replace S2. Diodes cause some loss in efficiency, but simplify the design and reduce cost. Notice that when S1 is closed, D1 is reverse biased (off) and that when S1 opens, the current flow through L1 forces the diode to become forward biased (on). This duplicates the alternate switching action of two switches. There is an exception to this condition, however. If the load current is low enough, the current through L1 will drop to zero sometime during S1 off-time. This is known as discontinuous mode operaan19fc AN19-12 Application Note 19 tion. Buck regulators will be in discontinuous mode for any load current less than; IOUT ≤ ⎛ V ⎞ VOUT ⎜ 1 − OUT ⎟ VIN ⎠ ⎝ (2)(f)(L1) L1 S1 VOUT VIN S2 AN19 F10a a. Basic Topology (3) S1 L1 VOUT VIN Discontinuous mode alters the original statement that output voltage depends only on input voltage and switch duty cycle because a third state of the switches now exists with diodes replacing S2; namely both switches off. Waveforms for voltage and current of S1, D1, L1, C1 and the input source are shown for both continuous and discontinuous modes of operation. Normally it is not important to avoid discontinuous mode operation at light load currents. A possible exception to this would be when the “on” time of S1 cannot be reduced to a low enough value to prevent the lightly loaded output from drifting unregulated high. If this occurs, most switching regulators will begin “dropping cycles” wherein S1 does not turn on at all for one or more cycles. This mode of operation maintains control of the output, but the subharmonic frequencies generated may be unacceptable in certain situations. A general property of “perfect” switching regulators is that they do not dissipate power in the process of converting one voltage or current to another; in other words, they are 100% efficient. This is to be expected from an inspection of Figure 10a: there are no components which dissipate power; only switches, inductors and capacitors. The following formula can then be stated; AN19 F10b b. Positive Buck Using One Switch S1 L1 –VOUT –VIN D1 C1 AN19 F10c c. Negative Buck Using One Switch CONTINUOUS MODE CURRENT VOLTAGE VIN IOUT 0 VIN 0 IOUT 0 0 S1 D1 IOUT L1 0 0 C1 VOUT 0 0 VIN IOUT IIN (AVG) 0 VIN 0 DISCONTINUOUS MODE S1 D1 (4) and ⎛V ⎞ IIN = IOUT ⎜ OUT ⎟ ⎝ VIN ⎠ C1 D1 where f = switching frequency. POUT = PIN or, (IOUT)(VOUT) = (IIN)(VIN) C1 L1 VIN 0 VIN VOUT 0 0 IOUT 0 (5) This shows that the average current drawn by the input of a switching regulator can be much higher or lower than the load current, depending on the ratio of output-to-input C1 VOUT 0 0 VIN VIN 0 IOUT IIN (AVG) AN19 F10 Figure 10. Buck Converter an19fc AN19-13 Application Note 19 voltage. If this simple fact is ignored, the designer may realize too late that his low voltage to high voltage converter will draw more current from the low voltage supply than it is capable of handling. S2 L1 L1 VOUT VIN C1 S1 a. Boost Regulators D1 VOUT VIN C1 S1 b. CONTINUOUS MODE The basic boost regulator shown in Figure 11a has an output voltage given by; CURRENT VOLTAGE VOUT IIN V VOUT = IN (continuous mode) 1 − DC S1 (6) DC is duty cycle, the ratio of S1 “on” time to “off” time, assuming that S1 and S2 open and close alternately. Duty cycle can take on values only between 0 and 1; therefore, the output voltage of a boost regulator is always higher than the input voltage. VIN 0 VOUT 0 IOUT 0 D1 0 VIN 0 L1 VIN – VOUT VOUT C1 In Figure 11b, a diode has replaced S2 to realize a boost regulator with a single switch. The voltage and current waveforms for all the components including the source are shown, both for continuous and discontinuous mode. Note that the current drawn from the input and delivered in pulses to the load is significantly higher than the output load current. The amplitude of input current and peak switch and diode current is equal to; VOUT S1 (7) Average diode current is equal to IOUT and average switch current is IOUT(VOUT – VIN) / VIN, both of which are significantly less than peak current. The switch, diode and output capacitor must be specified to handle the peak currents as well as average currents. Discontinuous mode requires even higher ratios of switch current to output current. One drawback of boost regulators is that they cannot be current limited for output shorts because the current steering diode, D1, makes a direct connection between input and output. IOUT 0 0 DISCONTINUOUS MODE D1 V IP = IOUT OUT (continuous mode) VIN 0 IOUT 0 vIN IOUT 0 L1 VIN 0 VOUT VIN II/O IOUT 0 VIN 0 (–)VOUT – VIN IOUT 0 VOUT 0 C1 0 AN19 F11 Figure 11. Boost Regulators Combined Buck-Boost Regulator Buck-boost regulators (Figure 12) are used to generate an output with the reverse polarity of the input. They look similar to a boost regulator except that the load is referred to the inductor side of the input instead of the switch side. Buck-boost regulators have an output voltage given by; VOUT = − VIN⎛ DC ⎞ ⎜ ⎟ ⎝ 1−DC ⎠ (8) an19fc AN19-14 Application Note 19 exact 1:1 turns ratio. With slight adjustments to L1 or L2, either input ripple current or output ripple current can be forced to zero. An impvoved version even exists which results in both ripple currents going to zero. This considerably eases the requirements on size and quality of input and output capacitors without requiring filters. D1 VOUT VIN S1 C1 L1 L1 The switch must handle the sum of input and output current; C1 S1 D1 –VOUT –VIN ⎛ V ⎞ IPEAK(S1) = IIN + I OUT = I OUT ⎜ 1 + OUT ⎟ VIN ⎠ ⎝ AN119 F12 Figure 12. Inverting Topology With duty cycle varying between 0 and 1, the output voltage can vary between zero and an infinitely high value. The current and voltage waveforms show that, like boost regulators, the peak switch, diode, and output capacitor currents can be significantly higher than output currents and these components must be sized accordingly. (10) The ripple current in C2 is equal to IOUT, so this capacitor must be large. It can be electrolytic, however, so physical size is not normally a problem. Flyback Regulator Maximum switch voltage is equal to the sum of input plus output voltage. The forward turn-on time of D1 is therefore very important in higher voltage applications to prevent additional switch stress. Flyback regulators (Figure 14) use a transformer to transfer energy from input to output. During S1 “on” time, energy builds up in the core due to increasing current in the primary winding. At this time, the polarity of the output winding is such that D1 is reverse biased. When S1 opens, the total stored energy is transferred to the secondary winding and current is delivered to the load. The turns ratio (N) of the transformer can be adjusted for optimum power transfer from input to output. ’Cuk Converter Peak switch current in a flyback regulator is equal to: ( )( VOUT + VIN I IPEAK = OUT = IOUT continuous mode VIN 1 − DC ) (9) The ’Cuk converter in Figure 13 is named after Slobodan ’Cuk, a professor at Cal Tech. It is like a buck-boost converter in that input and output polarities are reversed, but it has the advantage of low ripple current at both input and output. The optimum topology version of the ’Cuk converter eliminates the disadvantage of needing two inductors by winding them both on the same core, with IPEAK(S1) = ( 1:N C2 + L1 ) Notice that peak switch current can be reduced to a minimum by using a very small value for N. This has two + VIN )( IOUT N VIN + VOUT continuous mode VIN + VOUT –VOUT L2 S1 C1 – S1 AN19 F13 Figure 13. ’Cuk Converter VIN AN19 F14 – Figure 14. Flyback Converter an19fc AN19-15 Application Note 19 negative consequences however; the switch voltage and diode current become very large during switch off time. For a given maximum switch voltage, optimum power transfer occurs at VIN = 1/2VMAX. Both input ripple current and output ripple current are high in a flyback regulator, but this disadvantage is more than offset in many cases by the ability to achieve current or voltage gain and the inherent isolation afforded by the transformer. Output voltage is given by: DC (11) 1 − DC With any value of N, a duty cycle between 0 and 1 can be found which generates the required output. Flyback regulators can have an output voltage which is higher or lower than the input voltage. A disadvantage of flyback regulators is the high energy which must be stored in the transformer in the form of DC current in the windings. This requires larger cores than would be necessary with pure AC in the windings. VOUT = VIN • N • Forward Converter A forward converter (Figure 15) avoids the problem of large stored energy in the transformer core. It does this, however, at the expense of an extra winding on the transformer, two more diodes, and an additional output filter inductor. Power is transferred from input to the load through D1 during switch “on” time. When the switch turns “off,” D1 reverse biases and L1 current flows through D2. Output voltage is equal to: VOUT = VIN • N • DC 1 (12) N D1 VIN Current-Boosted Boost Converter This topology in Figure 16 is an extension of the standard boost converter. A tapped inductor is used to decrease the switch current for a given load current. This allows higher load currents at the expense of higher switch voltage. The increase in maximum output power over a standard boost converter is equal to: ( )( ) N + 1 VOUT POUT = PBOOST N VOUT − VIN + VOUT ( ) (13) Analysis of this equation shows that significant increases in power are possible when the input-output differential is low. Care must be used, however, to ensure that maximum switch voltage is not exceeded. + T1 S1 D3 Output voltage ripple of forward converters tends to be low because of L1, but input ripple current is high due to the low duty cycles normally used. A smaller core can be used for T1 compared to flyback regulators because there is no net DC current to saturate the core. L1 D2 + The additional winding and D3 are required to define switch voltage during switch “off” time. Without this clamp, switch voltage would jump all the way to breakdown at the moment the switch is opened due to the magnetizing current flowing in the primary. This “reset” winding normally has a 1:1 turns ratio to the primary which limits switch duty cycle to 50% maximum. Above this duty cycle, switch current rises uncontrolled even with no load because the primary winding cannot maintain zero DC voltage. Reducing the number of turns on the reset winding will allow higher switch duty cycles at the expense of higher switch voltage. VOUT 1 + – N VOUT VIN AN19 F15 S1 AN19 F16 Figure 15. Forward Converter Figure 16. Current-Boosted Boost Converter an19fc AN19-16 Application Note 19 Current-Boosted Buck Converter The current boosted buck converter in Figure 17 uses a transformer to increase output current above the maximum current rating of the switch. It accomplishes this at the expense of increased switch voltage during switch “off” time. The increase in maximum output current over a standard buck converter is equal to: IOUT VIN = IBUCK VOUT + N VIN − VOUT ( ) (16) In a 15V to 5V converter, for instance, with N = 1/4, ) * This formula assumes that L1→∞ IP = maximum switch current R - switch “on” resistance With VIN = 5V, VOUT = 12V, IP = 5A, R = 0.2Ω ⎡ POUT(MAX ) = 5 • 5 ⎢1 − 5 0.2 ⎢⎣ ⎞⎤ ⎛ ( ) ⎜⎝51 − 121 ⎟⎠⎥⎥ = 22W ⎦ ( ( ) Maximum switch voltage for a current-boosted buck converter is increased from VIN to: (17) D1 T1 ( )( 2 ⎤ ⎡ ⎛ 12 ⎞ 12 ⎥ 1 12 − 5 ⎢ + PIC = 1 • 0.2 ⎜ ⎟ − ⎢⎝ 5 ⎠ 5⎥ 40 ⎥⎦ ⎢⎣ = 0.672 + 0.175 = 0.85W () ( ) + VIN VOUT L2 10μH AN19 F17 D1 VIN APPLICATION CIRCUITS The LT1070 will operate in the boost mode with input voltages as low as 3V and output voltages over 50V. Figure 18 shows the basic boost configuration for positive voltages. This circuit is capable of output power levels that depend mainly on input voltage. VSW LT1070 C3* 100μF + GND C3 100μF L1 150μH 5V VC + ) OUTPUT FILTER + Figure 17. Current-Boosted Buck Converter Boost Mode (Output Voltage Higher Than Input) (18) The first term of this equation is the power loss due to the “on” resistance of the switch (R). The second term is the loss from the switch driver. For the circuit in Figure 18, with IOUT = 1A: 2 N ) 2 ⎤ ⎡ ⎛ VOUT ⎞ VOUT ⎥ IOUT VOUT − VIN ⎢ + PIC ≈ IOUT • R ⎜ − ⎢⎝ V ⎟⎠ VIN ⎥ 40 IN ⎢⎣ ⎦⎥ 2 This is a 100% increase in output current. VSWITCH = VIN + VOUT/N (17) With higher input voltages, output power levels can exceed 100W. Power loss internal to the LT1070 in a boost regulator is approximately equal to: 15 IOUT = =2 IBUCK 5 + 1/ 4 15 − 5 ( ⎡ ⎛ 1 1 ⎞⎤ POUT(MAX )* ≈ VIN • IP ⎢1 − IP • R ⎜ − ⎟⎥ ⎝ VIN VOUT ⎠ ⎥⎦ ⎢⎣ × C2 1000μF R1 10.7k 1% 12V 1A FB R3 1k C1 1μF *REQUIRED IF INPUT LEADS ≥ 2" R2 1.24k 1% AN19 F18 Figure 18. Boost Converter an19fc AN19-17 Application Note 19 The only other significant power loss in a boost regulator is in the diode, D1, as given by: PD = VF • IOUT (19) VF is the forward voltage of the diode at a current equal to IOUT • VOUT/VIN. In the example shown, with IOUT = 1A and VF = 0.8V: PD = 08 • 1 = 0.8W Total power loss in the regulator is the sum of PIC + PD, and this can be used to calculate efficiency (E): (20) L= ( ) VIN VOUT − VIN ΔI • f • VOUT (22) Example: let ΔI = 0.5A, VIN = 5V, VOUT = 12V, f = 40kHz With higher input voltages, efficiencies can exceed 90%. Maximum output voltage in the boost mode is limited by the breakdown of the switch to 65V (standard part) or 75V (HV part). It may also be limited by maximum duty cycle if input voltage is low. The 90% maximum duty cycle of the LT1070 limits output voltage to ten times the input voltage. For the simple boost mode, higher ratios of output to input voltage require a tapped inductor. Design procedure for a boost regulator is straightforward. R1 and R2 set the regulated output voltage. The feedback pin voltage is internally trimmed to 1.244V, so output voltage is equal to 1.244 (R1 + R2)/R2. R2 is normally set to 1.24k and R1 is found from: ⎛V ⎞ R1 = R2 ⎜ OUT − 1⎟ ⎝ 1.244 ⎠ Next, L1 is selected. The trade-offs are size, maximum output power, transient response, input filtering, and in some cases, loop stability. Higher inductor values provide maximum output power and low input ripple current, but are physically larger and degrade transient response. Low inductor values have high magnetizing current which reduces maximum output power and increases input current ripple. Low inductance can also cause a subharmonic oscillation problem if duty cycle is above 50%. With the aforementioned considerations in mind, a simple formula can be derived to calculate L1 based on the maximum ripple current (ΔI) to be allowed in L1. P POUT E = OUT = PIN POUT + PIC + PD (1A)(12V) = 88% E= (1)(12) + 0.85 + 0.8 Inductor (21) The 1.24k value for R2 is chosen to set divider current at 1mA, but this value can vary from 300Ω to 10k with negligible effect on regulator performance. For proper load regulation, R2 must be returned directly to the ground pin of the LT1070, while R1 is connected directly to the load. For further details, see Pin Description section. L= ( 5 5 − 12 ( ) ) ( ) 0.5 ⎛ 40 • 103 ⎞ 12 ⎝ ⎠ = 146μH A second formula will allow a calculation of maximum power output with this size inductor: ( ) ⎤⎥⎡⎢1− IP • R + IP • R ⎤⎥ ⎡ VIN VOUT − VIN PMAX = VIN ⎢IP − ⎢ 2 • L • f • VOUT ⎣ ⎥⎣ ⎦ VIN VOUT ⎦ (23) IP = maximum switch current Using the values from the previous example, with IP = 5A, R = 0.2Ω, ⎡ ⎤ 5 12 − 5 ⎢ ⎥ POUT(MAX ) = 5 ⎢5 − ⎥× ⎢ 2⎛ 146 • 10−6 ⎞ ⎛ 40 • 103 ⎞ 12 ⎥ ⎝ ⎠⎝ ⎠ ⎣ ⎦ ⎡ ⎛ 1 1 ⎞⎤ ⎢1 − 5 • 0.2 ⎜ − ⎟⎥ ⎝ 5 12 ⎠⎥⎦ ⎢⎣ ( ) ( ) ( ) = 5 (5 − 0.25)(0.88) = 21W an19fc AN19-18 Application Note 19 Note that the second term in the first set of brackets is the only one which contains “L,” and that this term drops out of the equation for large values of L. In this example, that term is equal to 0.25A, showing that maximum effective switch current, and therefore maximum output power is reduced by one-half the inductor ripple current in a boost regulator. In this example, peak effective switch current is reduced from 5A to 4.75A with 0.5A ripple current, a 5% loss. An additional 12% reduction of maximum available power is caused by switch “on” resistance. At higher input voltages, this switch loss is significantly reduced. When continuous inductor current is desired, the value of L1 cannot be decreased below a certain limit if duty cycle of the switch exceeds 50%. Duty cycle can be calculated from: V −V DC = OUT IN VOUT is discontinuous. The critical inductor size for continuous inductor current is: LCRIT = VIN2 (VOUT − VIN ) 2 • f • IOUT (VOUT ) 2 5) (12 − 5) ( = = 15.2μH 2 2(40 • 103 )(1)(12) (24) LMIN(discontinuous) = ( ) 2 IOUT VOUT − VIN (27) 2 IP • f Example: let VIN = 5V, VOUT = 12V, IOUT = 0.5A, IP = 5A 12 − 5 = 58.3% 12 The reason for a lower limit on the value of L for duty cycles greater than 50% is a subharmonic oscillation which can occur in current mode switching regulators. For further details of this phenomenon, see Subharmonic Oscillation section of this application section. The minimum value of L1 to ensure no subharmonic oscillations in a boost regulator is: V − 2VIN L1( MIN) = OUT 2 • 105 12 − 2(5) = = 10μH 5 2 • 10 (26) Discontinuous mode operation is sometimes chosen because it results in the smallest physical size for the inductor. The maximum power output is considerably reduced, however, and can never exceed 2.5(VIN) watts with the LT1070. The minimum inductor size required to provide a given output power in the discontinuous mode is given by: In this example, DC = 2 LMIN(discontinuous) = (2 • 0.5)(12 − 5) = 7μH 2 (5) • ⎛⎝ 40 • 103⎞⎠ This formula does not take into account efficiency losses, so the minimum value of L should probably be increased by at least 50% for worst-case conditions. Efficiency is degraded when using minimum inductor sizes because of higher switch and diode peak currents. In summation, to choose a value for L1: 1. Decide on continuous or discontinuous mode. (25) 2. If continuous mode, calculate C1 based on ripple current and check maximum power and subharmonic limits. Note that for VOUT ≤ 2VIN, there is no restriction on inductor size. The minimum value of 10μH obtained in this example is below the value which would yield continuous inductor current, so it is an artificial restriction. Subharmonic oscillations do not occur if inductor current 3. If discontinuous mode, calculate L1 based on power output requirements and check to see that output power does not exceed limit for discontinuous mode (PMAX = 2.5VIN) L1 must not saturate at the peak operating current. This value of current can be calculated from: an19fc AN19-19 Application Note 19 ( VOUT + VF ) − (IOUT • VOUT • R / VIN) ( VIN − IOUT • VOUT • R / VIN) VIN ( VOUT − VIN ) + ESR( MAX) = IL(PEAK ) = IOUT (27) 2L1• f • VOUT In this example, with VIN = 5V, VOUT = 12V, VF = 0.8V, IOUT = 1A, R = 0.2Ω, L1 = 150μH, f = 40kHz; + ( ) 1 12 + 0.8 − 1• 12 • (0.2) / 5 5 − 1• 12 • (0.2) / 5 ( ) 5 12 − 5 ( ) 2⎛ 150 • 10−6 ⎞ ⎛ 40 • 103 ⎞ 12 ⎝ ⎠⎝ ⎠ A core must be selected for L1 which does not saturate with 3A peak inductor current. Output Capacitor The main criteria for selecting C2 is low ESR (effective series resistance), to minimize output voltage ripple. A reasonable design procedure is to let the reactance of the output capacitor contribute no more than 1/3 of the total peak-to-peak output voltage ripple (VP-P), yielding: ( VOUT • IOUT )( f VIN + VOUT 0.33VP-P ) (28) Using VOUT = 12V, IOUT = 1A, VIN = 5V, f = 40kHz and VP-P =200mV, C2 ≥ ( 12 • 1 )( ) ⎛40 • 103 ⎞ 5 + 12 0.33 • 0.2 ⎝ ⎠ 0.67 • 0.2 • 5 ( ) 1 5 + 12 ) = 0.04Ω (29) ⎛V +V ⎞ VOUT VP-P = IOUT ⎜ IN OUT • ESR + VIN ( VIN + VOUT )( f)(C2) ⎟⎠ ⎝ (30) If lower output ripple is required, a larger output capacitor must be used with lower ESR. It is often necessary to use capacitor values much higher than calculated to obtain the required ESR. In the example shown, capacitors with guaranteed ESR less than 0.04Ω with a working voltage of 15V generally fall in the 1000μF to 2000μF range. Higher voltage units have lower capacitance for the same ESR. = 2.73 + 0.24 = 3A C2 ≥ ( IOUT VIN + VOUT After C2 has been selected, output voltage ripple may be calculated from: VF = forward voltage of D1 R = “on” resistance of LT1070 switch IL(PEAK) = = 0.67 • VP-P • VIN = 268μF This leaves 67% of the ripple attributable to ESR, giving: A second option to reduce output ripple is to add a small LC output filter. If the LC product of the filter is much smaller than L1 • C2, it will not affect loop phase margin. Dramatic reduction in output ripple can be achieved with this filter, often at lower cost and less board space than simply increasing C2. See section on Output Filters for details. Frequency Compensation Loop frequency compensation is performed by R3 and C1. Refer to the frequency compensation part of this application section for R3 and C1 selection procedure. Current Steering Diode D1 should be a fast turn-off diode. Schottky diodes are best in this regard and offer better efficiency in the forward mode. With higher output voltages, the efficiency aspect is minimal and silicon fast turn-off diodes are a more economical choice. Turn-on time is important also with output voltages above 40V. Diodes with slow turn-on time will have a very high forward voltage for a short time after forward current starts to flow. This transient forward voltage can be anywhere from volts to tens of volts. It must an19fc AN19-20 Application Note 19 be summed with output voltage to calculate worst-case switch voltage. To minimize switch transient voltage, the wiring of C2 and D1 should be short and close to the LT1070 as shown below. VIN = 5V, yielding: Short-Circuit Conditions A 4A fast-blow fuse would be a reasonable choice in this design. L1 VIN + VIN D1 VSW LT1070 GND C2 AN19 F18a Boost regulators are not short-circuit protected because the current steering diode (D1) connects the input to the output. The LT1070 will not be harmed for overloads up to 5A. Beyond that point, D1 can be permanently “on” and the LT1070 switch will be effectively shorted to the output. A fuse in series with the input voltage is the only simple means of protecting the circuit. Fuse sizing can be calculated from: I •V IIN ≈ OUT OUT VIN The circuit in Figure 19 is a negative “buck” regulator. It converts a higher negative input voltage to a lower negative output voltage. Buck regulators are characterized by low output voltage ripple, but high input current ripple. The feedback path in this design must include a PNP transistor to level shift the output voltage sense signal to the feedback pin of the LT1070, which is referenced to the negative input voltage. Output Divider R1 and R2 set output voltage; R1 = The circuit in Figure 18 has IOUT = 1A, VOUT = 12V, + VIN VSW GND R1 4.64k LOAD × –5.2V 4.5A 12k Q1 2N3906 VC FB OPTIONAL OUTPUT FILTER C1 R3 VIN –20V C2 1000μF L1** 200μH LT1070 OPTIONAL INPUT FILTER L3 (34) VREF R2 is nominally set to 1.24k. With the 5.2V output shown, D1 + (VOUT − VBE)(R2) VREF = LT1070 reference voltage = 1.244V VBE = base-emitter voltage of Q1 (33) C3* 100μF 1• 12 = 2.4A 5 NEGATIVE BUCK CONVERTER VOUT KEEP THIS PATH SHORT IIN ≈ × R2 1.24k *REQUIRED IF INPUT LEADS ≥ 2" **PULSE ENGINEERING 92113 L2 4μH + C4 200μF AN19 F19 Figure 19. Negative Buck Regulator an19fc AN19-21 Application Note 19 supplying up to 5A in the buck mode, so a reasonable upper limit on ripple current is 0.5A, or 10% of full load. This sets the value of L1 at: and letting VBE = 0.6V, R1 is: R1 = (5.2 − 0.6)(1.24) = 4.585kΩ 1.244 The nearest 1% value is 4.64kΩ. It will be apparent to experienced analog designers that the output voltage will have a temperature drift of 2mV/°C caused by the temperature coefficient of VBE. If this drift is too high, it can be compensated by a resistor/diode network in parallel with R2 as shown. For zero output drift, RP is made equal to R1 and R1 is now R1 L1= (VIN − VOUT)(VOUT) VIN(ΔI)(f) With circuit in Figure 19, VIN = 20V, VOUT = 5.2V, f = 40kHz, ΔI = 0.5A, giving: L1 = (20 − 5.2)(5.2) = 192μH 20 (0.5)⎛ 40 • 103 ⎞ ⎝ ⎠ The inductor current will go discontinuous (= zero for part of the cycle) when output current is one-half the ripple current. If continuous inductor current is desired for lower load currents, L1 will have to be increased. Q1 RP = R1 R2 Peak inductor and switch current is equal to output current plus one-half the peak-to-peak ripple current; D2 AN19 F19a IL(PEAK) = IOUT + calculated from: ⎛V ⎞ R1 = RP = ⎜ OUT − 1⎟ R2 ⎝ VREF ⎠ ( ) (37) (36) Duty Cycle Duty cycle of buck converters in the continuous mode is given by: V +V DC = OUT F VIN (VIN − VOUT)(VOUT) 2 (VIN)(L)(f) (37) With the example shown, letting IOUT = 4.5A, L1 = 200μH; IL(PEAK) = 4.5 + ( ) (20 − 5)(5) 2 20 ⎛ 200 • 10−6 ⎞ ⎛ 40 • 103 ⎞ ⎝ ⎠⎝ ⎠ = 4 • 5 + 0.23 = 4.73A Inductor The core used for L1 must be sized so that it does not saturate at 4.73A in this example. For lower output current applications, a much smaller core can be used. The core need not be sized for peak current limit conditions (6A to 10A) in most situations because the LT1070 pulse-bypulse current limit functions even with saturated cores. The inductor, L1, is chosen as a trade-off between maximum output power with minimum output voltage ripple, versus small physical size and faster transient response. A good starting point for higher power designs is to choose a ripple current (ΔI). The LT1070 is capable of Lower values of L1 can be used if maximum output power and low ripple are not as important as physical size or fast transient response. Pure discontinuous mode operation yields the lowest value for L1, and L1 is chosen on the basis of required output current. Maximum output current VF = forward voltage of D1 an19fc AN19-22 Application Note 19 in the discontinuous mode is one-half maximum switch current and L1 is found from: ⎛ V ⎞ 2VOUT IOUT ⎜ 1 − OUT ⎟ VIN ⎠ ⎝ L1( MIN) ⎛ 2⎞ ⎜IP ⎟ f ⎝ ⎠ ( ) () (38) no more than two-thirds of the maximum value. In this example, ESR is selected at 0.035Ω. C2 may now be found: C2 ≥ where IP = maximum switch current. Example: let VOUT = 5.2V, IOUT = 2A, VIN = 20V, IP = 5A, ⎛ 5.2 ⎞ 2 5.2 2 ⎜ 1 − 20 ⎟⎠ ⎝ L1( MIN) = 15.4μH 52⎛ 40 • 103 ⎞ ⎝ ⎠ ( )( )( ) ≥ It is suggested that, in discontinuous mode, this calculated value be increased by approximately 50% in practice to account for variations in cores, input voltage and frequency. The core must be sized to not saturate at a peak current of 5A for maximum output in discontinuous mode. Output Capacitor C2 is chosen for output ripple considerations. ESR of the capacitor may limit ripple voltage, so this parameter should be checked first. Maximum ESR allowed for a given peak-to-peak output ripple (VP-P), assuming C2 → ∞, is given by: ESR( MAX) = ( )( ) VP-P L1 f ⎛ V ⎞ VOUT ⎜ 1− OUT ⎟ VIN ⎠ ⎝ (39) with VP-P = 25mV, L1 = 200μH, f = 40kHz, VIN = 20V, VOUT = 5.2V; ( ) 3 0.025⎛ 200 • 10−6 ⎞ 40 • 10 ⎝ ⎠ ESR( MAX) = = 0.052Ω ⎛ 5.2 ⎞ 5.2 ⎜ 1 − ⎟ ⎝ 20 ⎠ To obtain a reasonable value for C2, actual ESR should be 1/⎛ 8Lf2⎞ ⎝ ⎠ (40) ⎤ ⎡ ⎥ ⎢ VP-P ESR ⎥ ⎢ − ⎢ ⎛ VOUT ⎞ Lf ⎥ ⎥ ⎢ VOUT ⎜ 1 − VIN ⎟⎠ ⎝ ⎥⎦ ⎢⎣ 2⎤ ⎡ 1/ ⎢8 ⎛ 200 • 10−6 ⎞ ⎛ 40 • 103 ⎞ ⎥ ⎠⎝ ⎠ ⎥ ⎢⎣ ⎝ ⎦ ⎤ ⎡ ⎥ ⎢ 0.025 ⎥ ⎢ 0.025 − ⎢ ⎛ 5.2 ⎞ ⎛ 3⎞ ⎥ −6 ⎞ ⎛ 200 • 10 40 • 10 ⎥ ⎢ 5.2⎜ 1 − ⎝ ⎠⎝ ⎠ 20 ⎟⎠ ⎥⎦ ⎢⎣ ⎝ ≥ 184μF It is very likely that a 184μF capacitor of the right operating voltage cannot be found with an ESR of 0.035Ω maximum. C2 will have to be increased in value significantly to achieve the required ESR. Output Filter If low output ripple is required, C2 may acquire unreasonably large values. A second option is to add an output filter as shown. Exact calculations for the values of L2 and C4 in this filter are beyond the scope of this note, but a rough approximation can be made by assuming that the ESR of C2 and C4 are the limiting factors. This leads to a value for L2 independent of the actual capacitance of C4. L2 ≈ (ESR2)(ESR4)(VIN − VOUT)(VOUT) 2 (VP-P)(2π)(f) (L1)(VIN) (41) ESR2 = ESR of C2 and ESR4 = ESR of C4 and VP-P = desired output ripple peak-to-peak. If we assume ESR2 = ESR4 = 0.1Ω, and require VP-P = 5mVP-P; an19fc AN19-23 Application Note 19 L2 = (0.1)(0.1)(20 − 5.2)(5.2) = 3.8μH 2 3⎞ ⎛ −6 ⎞ ⎛ (0.005)(2π)⎝ 40 • 10 ⎠ ⎝ 200 • 10 ⎠ (20) L2 may be increased above this value, but the L2 C4 product should be kept at least ten times smaller than L1 C2. Input Filter Buck regulators have high ripple current fed back into the input voltage supply. Peak-to-peak value of this current is equal to output current. This can cause intolerable EMI conditions in some systems. An input filter formed by L3 and C3 will greatly reduce this ripple current. The major considerations for this filter are its attenuation ratio and the possible effect it has on the regulator loop stability. See discussion of Input Filters elsewhere in this application section for more details. Frequency Compensation R3 and C1 provide frequency compensation. See Frequency Compensation section for details of selecting these components. NEGATIVE-TO-POSITIVE BUCK-BOOST CONVERTER The circuit in Figure 20 looks similar to a positive boost regulator except that the output load is referred to the inductor termination (ground) instead of the switch. A transistor (Q1) is used to level shift the output voltage signal down to the feedback pin of the LT1070 which is referred to the negative input voltage. Unlike buck or boost converters, inverting converters do not have any inherent limitation on input voltage relative to output voltage. Input levels may be either higher or lower than output voltage. The sum of input voltage plus output voltage of the LT1070 switch. Output voltage is given by: ⎛ DC ⎞ VOUT = − VIN ⎜ ⎟ ⎝ 1 − DC ⎠ DC = switch duty cycle (0 to 1) With DC = 0, output voltage is zero, and as DC Æ 1, output voltage increases without limit. Duty cycle of an inverting buck-boost converter is given by: Catch Diode D1 is the current steering diode. During switch off-time, it provides a path for L1 current. This diode should be a high speed switching type with fast turn-on and turn-off. A Schottky type is suggested for lower output voltage applications to improve efficiency. Formulas for average and peak diode current plus diode power dissipation are shown below. These equations assume continuous inductor current with fairly low ripple. IPEAK ≈ IOUT ⎛ V ⎞ IAV = IOUT ⎜1 − OUT ⎟ VIN ⎠ ⎝ ⎛ V ⎞ PDIODE = VF • IOUT ⎜ 1 − OUT ⎟ VIN ⎠ ⎝ where VF is diode forward voltage at I = IPEAK. VOUT DC = VIN + VOUT L2 L1 150μH C4* 100μF OPTIONAL INPUT FILTER L3 (44) OPTIONAL OUTPUT FILTER D1 VIN (42) (43) (45) VIN –12V × + VSW + LT1070 C3 × C2 1000μF R1 11.3k VOUT 12V 2A Q1 GND VC FB R3 1.24k 2.2k C1 0.22μF AN19 F20 *REQUIRED IF INPUT LEADS ≥ 2" Figure 20. Negative-to-Positive Buck-Boost Converter an19fc AN19-24 Application Note 19 Maximum power output of a buck-boost converter is equal to: (IP )(VOUT)(VIN) − (IP) (R)(VOUT) 2 VOUT + VIN POUT(MAX ) = VOUT + VIN (46) 1 + VF / VOUT IP = peak switch current —1/2 L1 p-p ripple current R = switch “on” resistance VF = forward voltage of D1 The first term on the top of the equation is the theoretical output power with no switch or diode (D1) losses. The second top term is the switch loss. The term on bottom accounts for diode losses. With the circuit shown, VIN = –12V, VOUT = 12V, ripple current in L1 = 0.5AP-P, peak switch current = 5A, R = 0.2Ω, VF = 0.8V, POUT(MAX ) = 12 + 12 4.75 2 0.2 12 12 + 12 1 + 0.8 / 12 = 24.6W Setting Output Voltage R1 and R2 determine output voltage; R1 = ( ) R2 VOUT − VBE VREF (52) VREF = LT1070 reference voltage = 1.244V VBE = base-emitter voltage of Q1 In this example, R2 = 1.24k, VOUT = 12V, and the VBE of Q1 is ≈ 0.6V, giving: R1 = ( 1.24 12 − 0.6 ) = 11.36kΩ The inductor is normally calculated on the basis of maximum allowed ripple current, because high ripple currents reduce the maximum available output power and degrade efficiency. For a peak-to-peak ripple current (ΔIL), L1 is equal to: L1= (VIN)(VOUT) (ΔIL)(VIN + VOUT)(f) (53) f = LT1070 operating frequency= 40kHz In this example, with ΔI chosen at 20% of maximum LT1070 switch current (ΔI = 1.0A), L1 = (12)(12) = 150μH 3⎞ ⎛ (1.0)(12 + 12)⎝ 40 • 10 ⎠ Larger values for L1 will not raise power levels appreciably, will increase size and cost and will degrade transient response. L1 is not acting as a ripple filter for either the input or the output, so large values will not improve ripple either. ( )( )( ) − ( ) ( )( ) 4.75 12 12 Inductor 1.244 The output voltage will have a –2mV/°C drift due to the temperature drift of VBE. If this is undesirable, a resistor diode combination can be added in parallel with R2 to correct drift. See section on Negative Buck Converters for details. If L1 is reduced in value, maximum power output will be degraded. Equation 46 defines IP as the maximum allowed switch current minus 1/2ΔIL. Therefore IP would have to be reduced from 5A to 2.5A if L1 were reduced to the point where the ripple current equaled 5A. This is a 2:1 reduction in maximum output power. Further reductions in L1 result in discontinuous current flow and equation 46 is invalid. The poor efficiency obtained with discontinuous current flow recommends it only for low power outputs when the physical size of L1 is critical. With discontinuous current flow, the minimum recommended size for L1 is: L1MIN (discontinuous) = 2(VOUT )(IOUT ) ( f)(0.7IP)2 (54) The (0.7) coefficient in form of IP is a “fudge” factor to account for variations in f and L1, and switching losses. an19fc AN19-25 Application Note 19 Example, VOUT = 12V, IOUT = 0.5A, f = 40kHz, IP = 5A L1 = Example, let L1 = 20μH, IOUT = 0.25A, VF = 0.8V ( )( ) = 24.5μH ⎛ 40 • 103 ⎞ 0.7 • 5 2 ) ⎝ ⎠( 2 12 0.5 IL(PEAK) = Once L1 has been selected, peak inductor current in continuous mode can be calculated from: ⎤ ⎡ ⎥ ⎢ VOUT + VF ⎥ ⎢ IL(PEAK) = IOUT 1 + ⎢ VIN + VOUT ⎥ ⎥ ⎢ VIN − IOUT • R VIN ⎦ ⎣ ( + ) (55) (VIN)(VOUT ) 2(L1)(VIN + VOUT )(f) With the circuit in Figure 20 with L1 = 150μH, VF = 0.8V, IOUT = 1.5A and R = 0.2Ω, ⎤ ⎡ ⎥ ⎢ 12 + 0.8 ⎥ IL(PEAK) = 1.5 ⎢1 + 12 + 12 ⎥ ⎢ ⎢⎣ 12 − 1.5 • 0.2 12 ⎥⎦ = 2.83A The core size for this discontinuous application can be considerably smaller than in the previous example. Core volume is approximately proportional to IL2 • L. With L1 = 100μH, and IL = 3.93A, IL2 • L = 1.5 • 10–3. The 20μH inductor with IL = 2.83A has IL2 • L = 0.16 • 10–3. The core can be nearly ten times smaller. This size difference is not free—the discontinuous circuit will supply much less current and have somewhat poorer efficiency. ) (VP-P)(VIN)(2 / 3) IOUT(VIN + VOUT ) (57) VP-P = peak-to-peak output voltage ripple With VP-P selected at 100mV, and VIN = 12V, VOUT = 12V, IOUT = 1.5A, ESR is: ESR( MAX) = IL(PEAK) = 3.18 + 0.5 = 3.68A 3.18A is the average current through L1 and 0.5A is the peak AC ripple current. The core used for L1 must be large enough so that it does not saturate at IL = 3.68A. Peak inductor current for discontinuous mode operation is found from: (IOUT)(VOUT + VF)(2) (L1)(f) C2 must be a high quality (low ESR) switching capacitor because it does all the output filtering. L1 simply functions as an energy transfer element. A reasonable starting point for selecting C2 is to assume that the ESR (effective series resistance) of C2 contributes 2/3 of the output ripple and that the reactance of C2 contributes 1/3. With this in mind, a formula can be derived for ESR: ESR( MAX ) = (12)(12) + 2 ⎛ 150 • 10− 6⎞ (12 + 12)⎛ 40 • 103 ⎞ ⎝ ⎠ ⎝ ⎠ IL(PEAK) = (discontinuous mode) ⎛ 20 • 10− 6⎞ ⎛ 40 • 103 ⎞ ⎝ ⎠⎝ ⎠ Output Capacitor VF = forward voltage of D1 R = LT1070 switch “on” resistance ( (0.25)(12 + 0.8)(2) With ESR found, the value of C2 may now be computed: C2 = (IOUT)(VOUT) ⎡ ⎛ V + V ⎞⎤ ⎢VP-P − (IOUT )(ESR)⎜ IN OUT ⎟ ⎥(VOUT + VIN)(f) VIN ⎠ ⎥ ⎝ ⎢ ⎣ (56) (0.1)(12)(2 / 3) = 0.0185Ω 1.5 (12 + 12) (58) ⎦ If we specify C2 ESR at 0.015Ω max, C2 is: an19fc AN19-26 Application Note 19 C2 = (1.5)(12) ⎡ ⎛ 12 + 12 ⎞ ⎤ 3⎞ ⎛ ⎢0.1 − 1.5 0.015 ⎜ ⎟ ⎥ 12 + 12 ⎝ 40 • 10 ⎠ ⎝ 12 ⎠ ⎥⎦ ⎢⎣ (59) ( )( ) ( ) Breakdown voltage of D1 must be at least VIN + VOUT. Turnon time should be short to minimize the voltage spike across the LT1070 switch following switch turn-off. POSITIVE BUCK CONVERTER = 341μF It is most likely that to find a capacitor with a maximum ESR of 0.015Ω, the capacitance will have to be much larger than 341μF. If lower output ripple is desired, the value of C2 may become very large just to meet ESR requirements. A second solution to the output ripple problem is to add an output filter at the point indicated in Figure 20. This filter can provide a large reduction in ripple with almost no effect on loop transient response, phase margin or efficiency. See section on Output Filters for further details. Current Steering Diode D1 must be a fast recovery diode with an average current rating equal to I0UT and peak repetitive rating of IOUT (VOUT + VIN)/VIN. If continuous output shorts can occur, D1 must be rated for 10A and heat sunk accordingly unless the LT1070 current limit is externally reduced. Power dissipation of D1 under normal load conditions is: ( )( ) P( D1) = IOUT VF VF is D1 forward voltage at ID = IOUT ⎛ VOUT + VIN ⎞ ⎜ ⎝ VIN ⎟ ⎠ (60) Positive buck converters (Figure 21) using the LT1070 require a novel design approach because the negative side of the LT1070 switch is committed to the ground of the chip. This negative switch terminal is the inductor drive point in a positive buck converter. The ground pin of the LT1070 must therefore switch back and forth between the input voltage and converter ground. This is accomplished by tying the positive side of the switch (VSW) to the input supply, and using a peak-detected (C3, D3), bootstrapped supply voltage to operate the chip. As long as the LT1070 is switching, C3 will maintain the chip input-to-ground pin voltage at a voltage equal to the input supply voltage. It is important to keep the value of C3 to a minimum to ensure proper start-up of this topology. The 2.2μF value shown should not be increased unless careful tests are done to ensure proper start-up under worst-case light loads. If the LT1070 does not start, the lightly loaded output will go unregulated high. The minimum recommended load current in any case is 100mA. The most unusual aspect of this design is the manner in which output voltage information is delivered to the LT1070 feedback pin. This pin is switching along with the LT1070 ground pin to which it is referenced, so the feedback circuit must float on the switching ground pin and at the same L2, 4μH VIN D3 VSW VIN LT1070 C3 2.2μF VC D2 1N914 R1 3.74k + GND C5 200μF OPTIONAL OUTPUT FILTER FB R3 470Ω C1 1μF D1 R2 1.24k r + C2 1μF R4 10Ω L1 100μH C4 1000μF + × 5V 100mA MINIMUM AN19 F21 Figure 21. Positive Buck Converter an19fc AN19-27 Application Note 19 time be proportional to the DC value of the output voltage. This is accomplished by peak detecting the output voltage with D2 during the “off” time of the LT1070 switch. The voltage on the ground pin of the chip at this time is one diode drop (D1) negative with respect to system ground, because D1 is forward biased by load current flowing through L1. D2 also forward biases, giving a voltage across C2 of: VC2 = VOUT – VD2 + VD1 (61) VD1 = forward voltage of D1 VD2 = forward voltage of D2 The feedback network, R1/R2, is therefore biased with a voltage very nearly equal to output voltage, and the LT1070 will regulate output voltage according to: VOUT = VC2 + VD2 − VD1 = ( ) + VD2 − VD1 VREF R1 + R2 R2 (62) VREF = reference voltage of LT1070 = 1.244V If VD1 is exactly equal to VD2, output regulation will be perfect, but the forward voltage of D1 is load current dependent, while D2 operates at a fixed average current of 1mA. This can cause output voltage variations of 100mV to 400mV if load current varies over a wide range. To minimize this effect, D1 should be conservatively rated with respect to operating current so that the effect of parasitic series resistance is minimized. The unit shown is rated at 10A average current. D1 should also be a fast turnon type. (See diode discussion elsewhere in this application section.) A long turn-on time for D1 allows C2 to charge to a voltage higher than VOUT, creating an abnormally low output voltage. R4 is added to minimize this effect. A Schottky diode is recommended for D1 because these diodes have very fast switching times and their low forward voltage improves efficiency, especially for low output voltage. Load regulation can be significantly improved in this application by inserting a small resistor (r, shown in dashed box) between D1 and L1. The voltage across r will be equal to (r)(IOUT).This voltage increases the voltage across R2, forcing the output voltage to rise under load. Perfect load regulation will result if the output rise created by r just cancels the output drop caused by the increased forward voltage of D1. The required value for r is found from: V r = rd REF VOUT (63) rd = forward series resistance of D1 VREF = LT1070 reference voltage = 1.244V Load regulation will never be perfect because rd varies slightly from unit to unit and it is not constant with load current, but regulation better than 2% with VOUT = 5V is easily achieved even with load current varying over a 5:1 range. For higher output voltages, load regulation is even better. For the circuit shown, with rd = 0.05Ω, r is: r= (0.05)(1.244) = 0.0124Ω 5 This is most easily obtained by using 9 inches of #22 hookup wire. Output voltage is determined by R1 and R2: V −V R1 = R2 OUT REF VREF (64) R2 is normally fixed at 1.24k to set divider current to 1mA. This equation assumes that VD1 = VD2. A slight adjustment in R1 will be required if VD1 ≠ VD2. Duty Cycle Limitations Maximum duty cycle for the LT1070 is 90%. This limits the minimum input voltage in buck regulators. Duty cycle can be calculated from: DC = VOUT + VF ( ) (65) VIN − IOUT • R + VF VF = forward voltage of D1 R = “on” resistance of LT1070 switch Rearranging this formula for VIN yields: VIN(MIN) = VOUT + VF DC ( ) + IOUT • R − VF (66) With a maximum duty cycle of 90%, (0.9) and VOUT = 5V, VF = 0.6V, R = 0.2Ω, IOUT = 4A: an19fc AN19-28 Application Note 19 VIN(MIN) = ( With L1 = 10μH, for instance, and IP = 5A: ) 5 + 0.6 + 0.2 • 4 − 0.6 = 6.4V 0.9 (5) ⎛⎝10 • 10−6⎞⎠ ⎛⎝ 40 • 103⎞⎠ ⎛ 16 ⎞ IOUT(MAX ) = ⎜ 16 − 5 ⎟ = 1.4A ⎝ ⎠ 2(5) 2 Inductor The energy storage inductor in a buck regulator functions as both an energy conversion element and as an output ripple filter. This double duty often saves the cost of an additional output filter, but it complicates the process of finding a good compromise for the value of the inductor. Large values give maximum power output and low output ripple voltage, but they also can be bulky and give poor transient response. A reasonable starting point is to select a maximum peak-to-peak ripple current, (ΔI). This yields a value for L1 of: L1= (VIN − VOUT)(VOUT) (VIN)(ΔI)(f) (67) f = LT1070 operating frequency ≈ 40kHz ΔI = peak-to-peak inductor ripple current With the circuit shown, VIN = 16V, VOUT = 5V and ΔI set at 20% of 3.5A = 0.7A: L1 = (16 − 5)(5) = 122μH (16)(0.8)⎛⎝ 40 • 103⎞⎠ ( ) ( )( ) 2 IP = LT1070 peak switch current The load current where a buck regulator changes from continuous to discontinuous operation is: ICRIT = (VIN − VOUT)(VOUT) 2(VIN)(f)(L1) (69) With a 100μH value of L1, inductor current will go discontinuous at: ICRIT = (16 − 5)(5) ( ) 2 16 ⎛ 40 • 103 ⎞ ⎛ 100 • 10−6 ⎞ ⎝ ⎠⎝ ⎠ = 0.43A (70) ICRIT can never exceed 2.5A (one half maximum LT1070 switch current). Peak inductor current in a buck regulator with continuous mode operation is: IL(PEAK) = IOUT + The ripple current in L1 reduces the maximum output current by one-half ΔI. For lower output currents this is no problem, but for maximum output power, L1 may be raised by a factor of two to three. For lower output powers, L1 can be reduced to save on size and cost. Discontinuous mode operation will occur even near full load if L1 is reduced far enough. The LT1070 is not affected by discontinuous operation per se, but maximum output power is significantly reduced in discontinuous mode designs: IP L f ⎛ VIN ⎞ IOUT(MAX ) = ⎜ 2VOUT ⎝ VIN − VOUT ⎟⎠ (discontinuous) Efficiency is also reduced with discontinuous operation because of increased switch dissipation. (VIN − VOUT)(VOUT) 2(VIN)(L1)(f ) (71) With IOUT = 3.5A and L1 = 100μH: IL(PEAK) = 3.5 + ( ) (16 − 5)(5) 2 16 ⎛100 • 10−6 ⎞ ⎛40 • 103 ⎞ ⎝ ⎠⎝ ⎠ = 3.93A The core used for L1 must be able to handle 3.93A peak current without saturating. Peak inductor currents in discontinuous mode are much higher than output current: (68) IL(PEAK) = (discontinuous) ( )( )( (VIN)(L1)(f) 2 VOUT IOUT VIN − VOUT ) (72) an19fc AN19-29 Application Note 19 FLYBACK CONVERTER For L1 = 10μH, IOUT = 1A: ( )( )( 2 5 1 16 − 5 IL(PEAK) = (discontinuous) ( ) ) Flyback converters (Figure 22) are able to regulate an output voltage either higher or lower than the input voltage by shuttling stored energy back and forth between the windings of a transformer. During switch “on” time, all energy is stored in the primary winding according to: E = (IPRI)2(LPRI)/2. When the switch turns off, this energy is transferred to the output winding. The current in the secondary just after switch opening is equal to the reciprocal of turns ratio (1/N) times the current in the primary just prior to switch opening. Output voltage of a flyback converter is not constrained by input voltage as in buck or boost converters. = 4.15A 16 ⎛ 10 • 10−6 ⎞ ⎛ 40 • 103 ⎞ ⎝ ⎠⎝ ⎠ The 10μH inductor, at 1A output current, must be sized to handle 4.14A peak current. Output Voltage Ripple See Negative Buck Regulator section for calculation of output ripple. Output Capacitor VOUT = C4 is chosen for output voltage ripple considerations. Its ESR (effective series resistance) is the most important parameter. For details, see Negative Buck Regulators section. ( ) DC N • VIN 1 − DC DC = switch duty cycle = Output Filter VOUT ( ) VOUT + N • VIN (74) N = transformer turns ratio For very low output voltage ripple, the value of C4 may become prohibitively high. An output filter, L2 and C5, may be used to reduce output ripple. See Output Filter section for details. CLAMP TURN-ON SPIKE VSNUB VIN OPTIONAL FILTER b 0V C4 200μF VOUT + VF c D1 VIN 20V TO 30V R4 C3 0.47μF × 1 N* + VOUT 5V 6A VIN d ΔI PRIMARY CURRENT N*=1/3 R1 3.74k IPRI N 0 VC R3 1.5k C2 0.15μF R2 1.24k SECONDARY CURRENT IPRI FB GND IPRI 0 VSW LT1070 SECONDARY VOLTAGE AREA “c”= AREA “d” TO MAINTAIN ZERO DC VOLTS ACROSS SECONDARY N • VIN 0V C1 2000μF D2 + VOUT + VF PRIMARY FLYBACK VOLTAGE = N LT1070 SWITCH VOLTAGE AREA “a” = AREA “b” TO MAINTAIN ZERO DC VOLTS ACROSS PRIMARY a L2 10μH C4* 100μF (73) LT1070 SWITCH CURRENT 0 IPRI SNUBBER DIODE CURRENT 0 *REQUIRED IF INPUT LEADS ≥ 2" I •L t = PRI L VSNUB AN19 F22 Figure 22. Flyback Converter an19fc AN19-30 Application Note 19 By varying duty cycle between 0 and 1, output voltage can theoretically be set anywhere from 0 to ∞. Practically, however, output voltage is constrained by switch breakdown voltage and the maximum output voltage is limited to: ( ) VOUT(MAX ) = N VM − VSNUB − VIN (75) LPRI = (VIN)(VOUT ) (ΔI)( f)(VOUT + N • VIN) (77) With VIN = 24V, VOUT = 5V, ΔI = 1A, N = 1/3: LPRI = (24)(5) = 231μH (1)(40 • 103 )(5 + 1/ 3 • 24) VSNUB = snubber voltage (see snubber details in this section) VM = maximum allowed switch voltage Values of LPRI higher than this will raise maximum output current only slightly and will require larger core size. Lower primary inductance may be used for lower output currents to reduce core size. This still allows the LT1070 to regulate output voltages of hundreds or even thousands of volts by using large values of N. Maximum output current is a function of peak allowed switch current (IP): In many applications, N can vary over a wide range without degrading performance. If maximum output power is desired however, N can be optimized: N( OPT) = VOUT + VF VM − VIN(MAX ) − VSNUB (76) IOUT(MAX) N( OPT) = 5 + 0.7 = 0.38 60 − 30 − 15 A turns ratio of 1:3 (0.33) was used in this circuit. A second important transformer parameter which must be determined is primary inductance (LPRI). For maximum output power, LPRI should be high to minimize magnetizing current, but this can lead to unacceptably large core sizes. A reasonable design approach is to reduce the value of LPRI to the point where primary magnetizing current (ΔI) is about 20% of peak switch current. The LT1070 is rated for 5A peak switch current, so for full power applications, ΔI can be set to 1A peak-to-peak. Maximum output current is reduced by one-half of the ratio of ΔI to peak switch current, or ≈10% in this case. (78) IP = maximum LT1070 switch current E = overall efficiency ≈ 75% With VIN = 24V, VOUT = 5V, IP = 5A, ΔI = 1A, N = 1/3: VF = forward voltage of D1 In Figure 22, with VOUT = 5V, VF = 0.7V (Schottky), VIN(MAX) = 30V, VM = 60V, VSNUB = 15V; ΔI⎞ ⎛ E ⎜ IP − ⎟ (VIN) ⎝ 2⎠ = (N • VIN ) + VOUT IOUT(MAX) 1⎞ ⎛ 0.75⎜ 5 − ⎟ (24) ⎝ 2⎠ = 6.2A = (1/ 3 • 24) + 5 The 75% efficiency number comes from losses in the snubber network (≈ 6%), LT1070 switch (≈ 4%), LT1070 driver (≈ 3%), output diode (≈ 8%) and transformer (≈ 4%). Although this efficiency is not as impressive as the 85% to 95% obtainable with simple buck or boost designs, it is more than justified in many cases by the ability to use the variable N to generate high output currents or high output voltages and the option to add extra windings for multiple outputs. Peak primary current is used to determine core sizing for the transformer: ( )( ( )( )( ) VIN VOUT ⎛V ⎞ I IPRI = OUT ⎜ OUT + N⎟ + E ⎝ VIN ⎠ 2 f LPRI VOUT + N • VIN ) (79) With this design approach, LPRI is found from: an19fc AN19-31 Application Note 19 For an output current of 6A, with VIN = 24V, VOUT = 5V, E = 75%, LPRI = 231μH, N = 1/3: IPRI = + C3 R4 R5 LPRI VOUT – ⎞ 6 ⎛ 5 + 1/ 3⎟ ⎜ 0.75 ⎝ 24 ⎠ (24)(6) + VIN AN19 F23 C4 CLAMP EITHER ZENER OR R/C ( ) 2⎛ 40 • 103 ⎞ ⎛ 231• 10−6 ⎞ 5 + 1/ 3 • 24 ⎝ ⎠⎝ ⎠ Figure 23. Snubber Clamping = 4.33 + 0.5 = 4.83A The core must be able to handle 4.83A peak current in the 231μH primary winding without saturating. (See section on inductors and transformers for further details.) Output Divider During switch “on” time, a current is established in LL equal to peak primary current (IPRI). When the switch turns off, the energy stored in LL, (E = I2 • LL/2) will cause the switch voltage to fly up to breakdown if the voltage is not clamped. If a Zener diode is used for clamping, Zener clamp voltage is selected by assigning a maximum switch voltage and maximum input voltage: R1 and R2 set output voltage: V −V R1 = OUT REF • R2 VREF LL (80) VREF = feedback reference voltage of the LT1070 = 1.244V R1 and R2 can vary over a wide range, but a convenient value for R2 is 1.24k, a standard 1% value. For a 5V output, (5 − 1.244)(1.24) = 3.756kΩ R1 = VZENER = VM – VIN(MAX) VM = maximum allowed switch voltage The standard LT1070 maximum switch voltage is 65V, so VM is typically set at 60V to allow a margin of 5V. If we assume VIN(MAX) = 30V for this circuit: VZENER = 60 – 30 = 30V Peak Zener current is equal to peak primary current (IPRI) and average power dissipation is equal to: 1.244 (VZ)(IPRI) (LL)(f) 2 Frequency Compensation R3 and C2 provide a pole-zero frequency compensation. For details, see the section on frequency compensation elsewhere in this application note. Snubber Design Flyback converters using transformers require a clamp to protect the switch from overvoltage spikes. These spikes are created by leakage inductance in the transformer. Leakage inductance (LL) is modeled as an inductor in series with the primary winding which is not coupled to the secondary as shown in Figure 23. PZENER = ⎛ V +V ⎞ 2 ⎜ VZ − OUT F ⎟ N ⎝ ⎠ (81) An important part of this equation is the term [VZ – (VOUT + VF)/N] in the denominator. This voltage is defined as snubber voltage (VSNUB) and is the difference between the Zener voltage and the normal flyback voltage of the primary. (See waveforms with Figure 22.) If VSNUB is too low, Zener dissipation rises rapidly. A reasonable minimum for VSNUB is 10V, so this should be checked before proceeding further: an19fc AN19-32 Application Note 19 V +V 5 + 0.7 VSNUB = VZ − OUT F = 30 − = 12.9V N 1/ 3 (82) Leakage inductance in a transformer can be minimized by bifilar winding or by interleaving the primary and secondary. If this is done correctly, leakage inductance is usually less than 1% of primary inductance. If we wind T1 for LPRI = 230μH, LL should be less than 2.3μH. Using this value, power dissipation in the Zener at full load current is: (30)(4.83) ⎛⎝ 2.3 • 10−6⎞⎠ ⎛⎝ 40 • 103⎞⎠ 2 PZENER = ⎛ 5 + 0.7 ⎞ 2⎜ 30 − 1/ 3 ⎟⎠ ⎝ = 2.5W (30)(9) ⎛⎝ 3.5 • 10−6⎞⎠ ⎛⎝ 40 • 103⎞⎠ 2 ⎛ 0.7 ⎞ 2⎜ 30 − 1/ 3 ⎟⎠ ⎝ (output shorted) R SNUB = ⎛ 5 ⎞ 2 2 ( 30 ) − 2 ( 30 ) ⎜ ⎝ 1 / 3 ⎟⎠ ( 4.83) = 4W 2 (2.3 • 10 )(40 • 10 ) −6 3 = 419 Ω Power dissipation in the snubber at full load is equal to: (VR) = (30) PR = 2 2 R Zener dissipation under short-circuit conditions is calculated from the same equation (81) by assuming that VOUT = 0V and IPRI is the current limit value of the LT1070. If we let IPRI = 9A: PZENER = conditions of IPRI = 4.83A: 419 = 2.15W At very light loads, the voltage across the snubber resistor drops to the flyback voltage of the primary, VR = (VOUT + VF)/N. In this example, flyback voltage is 16.8V, resulting in a snubber dissipation of 16.82/419Ω = 0.67W. This may be a consideration where high efficiency is necessary even with near-zero output loads. Short circuit power dissipation in the snubber resistor is approximately equal to: (IPRI) (f)(LL) PR ≈ 2 The waveform of LT1070 switch voltage shows a narrow spike extending above the snubber clamp voltage. This spike is caused by the turn-on time of the clamp circuit, in particular the diode in series with the Zener. This diode should be a Schottky or a very fast turn-on type to minimize the height of this spike. It must be rated for peak currents equal to IPRI. The reverse voltage rating of the diode must be at least VIN(MAX). An alternative to Zener clamping is an R/C clamp. This is less expensive, but has the disadvantage of a less welldefined clamping level. The RC snubber also dissipates power even with no-load conditions. A value for R4 is found from: 2 ( VR ) − 2 ( VR ) ( VOUT / N) (84) 2 (output shorted) IPRI in short circuit is the current limit of the LT1070. For IPRI = 9A, snubber dissipation with the output shorted is ≈ 3.7W in this example. The value of C3 is not critical, but it should be large enough to keep the ripple voltage across the snubber to only a few volts. This yields a capacitor value of: C3 = VR (R)(f)(VS) (85) VS = voltage ripple across C3 For VS = 3V, VR = 30V, R = 419Ω: 2 R SNUB = (IPRI) (LL )( f ) 2 (83) VR = voltage across snubber resistor If we set VR = 30V (same as VZENER) and use full load C3 = ( ) 30 () 419 ⎛ 40 • 103 ⎞ 3 ⎝ ⎠ = 0.6μF C3 should be a very low ESR (effective series resistance) an19fc AN19-33 Application Note 19 film or ceramic type to keep spike voltage to a minimum. C4 and R5 (shown in dashed lines) form an optional damper, which eliminates primary ringing for light output load conditions when secondary current drops to zero during switch-off time (discontinuous operation). Typical values are R = 300Ω to 1.5k, C = 500pF to 5000pF. Output Diode (D1) The output diode has an average forward current equal to output current, but the current flows in pulses with an amplitude equal to: ⎛ ⎞ VOUT + VF ID1(PEAK) = IOUT ⎜ 1 + ⎟ ⎜ ⎟ N V IN ⎝ ⎠ ( ) (86) For the circuit in Figure 22, with IOUT = 6A: ⎛ ⎞ 5 + 0.7 ID1(PEAK) = 6 ⎜ 1 + ⎟ = 10.3A ⎜ 1/ 3 24 ⎟ ⎝ ⎠ ( ) To calculate diode power dissipation, use the forward voltage at this peak current multiplied times output current; PD1=(VF)(IOUT) VF = D1 forward voltage at peak current With VF = 0.55V and IOUT = 6A, D1 power dissipation is 3.3W. output (VOUT = 0V): ID1 = ( )( ) = 20A 1/ 3(24 ) + 0 + 0.8 0.8 9 24 Peak diode current will be only slightly higher because the duty cycle of the diode is approaching 100% with VOUT = 0V. Output short-circuit current can be reduced, if desired, by clamping the VC pin of the LT1070. The best way to do this and still be assured of maximum full-load current is to clamp the VC pin to a portion of output voltage. This generates a foldback current limit that will reduce shortcircuit current without affecting normal load current. The clamp network in Figure 24 will reduce shorted output current of the circuit in Figure 22 to ≈ 5A. The clamp point is generated by splitting R1 into two resistors such that the tap point voltage is ≈1.75V at normal output voltage. This ensures that D4 will not turn on until the output voltage begins to drop. When VOUT = 0V, the voltage at the FB pin is clamped to approximately 0.35V by the internal mode select circuitry and the voltage at the R1 tap point will be approximately the same. The current through the diodes will be maximum available VC pin current. This sets the clamp voltage on the VC pin at ≈1.55V, reducing output short-circuit current to ≈ 5A. Full-load current can be reduced, if desired, by moving the tap point on R1 down, even to the point where it becomes part of R2. During start-up and overload conditions, D1 current will increase significantly. Average diode current through D1 when the LT1070 is in current limit is equal to: ID1 = ( )( ) N(VIN) + VOUT + VF TO VOUT 3.2k R1 α ILIM VIN LT1070 (87) (during LT1070 current limit) α is an empirical multiplier slightly less than unity. It is very complex to calculate, but it takes into account such things as switch resistance, leakage inductance, snubber losses, and transformer losses. If we assume α = 0.8, ILIM = 9A, VIN = 24V, N = 1/3, VF = 0.55V and a shorted GND VC 500Ω FB R3 D5 1N914 D4 R2 1.24k C2 AN19 F24 Figure 24. Foldback Current Limiting an19fc AN19-34 Application Note 19 Output Capacitor (C1) Flyback converters do not use the inductance of the transformer as a filter, so the output capacitor must do all the filtering work. The output peak-to-peak voltage ripple is equal to: VP-P = ⎛ ⎞ IOUT V + ESR IOUT ⎜ 1 + OUT ⎟ ⎜ N VIN ⎟ ⎛ N VIN ⎞ ⎝ ⎠ (88) f C1 ⎜ 1 + ⎟ ⎜ ⎟ VOUT ⎠ ⎝ ( )( ) ( ) ( )( ) ( ) This formula again assumes that the ESR of C4 dominates its total impedance. For ESR4 = 0.1Ω, L1 = 10μH, VOUT = 5V, N = 1/3, VIN = 24V, r= (0.1)(5)(1/ 3 • 24) = 0.059 ⎛ 10 • 10−6 ⎞ ⎛ 40 • 103 ⎞ 5 + 1/ 3 • 24 2 ) ⎝ ⎠⎝ ⎠( This is a 16:1 reduction in ripple, greatly easing the requirements on C1. Total output ripple, with a filter, is given by: ESR = effective series resistance of C1 The first term is the ripple due to the capacitance of C1; the second term is ripple due solely to the ESR of the capacitor. As it turns out, commercially available capacitors in the range required for this application (100μF to 10,000μF) have ESR high enough to dominate the ripple voltage. A 2,000μF capacitor for instance, might have a guaranteed ESR of 0.02Ω. For IOUT = 6A, VOUT = 5V, VIN = 24V, N = 1/3, this gives: VP-P = 6 ( )⎞⎟ ⎛ ⎛ 40 • 103 ⎞ ⎛ 2000 • 10− 6⎞ ⎜ 1 + 1/ 3 24 ⎝ ⎠⎝ ⎠⎜ 5 ⎝ ⎛ 5 + 0.02 6 ⎜ 1 + ⎜ 1/ 3 24 ⎝ ( )( ) ⎟ ⎠ ⎞ ⎟ ⎟ ⎠ ( ) An alternative to brute force output capacitance (to obtain low ESR) is to add an LC output filter (shown as L1 and C4 in Figure 22). A relatively small inductor and capacitor can greatly reduce output ripple. If we assume the ripple across C1 is due solely to ESR, and therefore rectangular, the ratio of filter output ripple to input ripple is: VIN(P-P ) ( )( ) 2 (L1)(f)(VOUT + N • VIN) ESR4 VOUT N • VIN ESR4 = effective series resistance of C4 (90) For ESR1 = 0.05Ω, ESR4 = 0.1Ω, VOUT = 5V, VIN = 24V, N = 1/3, IOUT = 6A, L1 = 10μH, output ripple (P-P) is: VP-P = (0.05)(0.01)(5)(6) = 28.8mV ⎛ 10 • 10−6 ⎞ ⎛ 40 • 103 ⎞ 5 + 1/ 3 • 24 ) ⎝ ⎠⎝ ⎠( The LT1070 has a second operating mode called “isolated flyback,” as shown in Figure 25 (see Note 1 with figure). While in this mode, it does not use the feedback pin to sense output voltage; instead, it senses and regulates the transformer primary voltage during switch “off” time (tOFF). This voltage is related to VOUT by: The ESR term dominates and will be the main criteria for selecting the size of the output capacitor. =r = (ESR1)(ESR4)(VOUT)(IOUT) (L1)(f)(VOUT + N • VIN) TOTALLY ISOLATED CONVERTER = 28.8mV + 195mV = 224mV VOUT(P-P ) VP-P = (89) ( )( ) VOUT = N VPRI − VF (during tOFF) (90) N = turns ratio of transformer VF = forward voltage of output diode VPRI = primary voltage during switch “off” time The secondary output voltage will be regulated if VPRI is regulated. The LT1070 switches from normal mode to regulated primary mode when the current out of the feedback pin exceeds ≈10μA. An internal clamp holds the voltage (VFB) on this pin at ≈400mV. R2 is used to put the LT1070 in isolated flyback mode. It also doubles as an adjustment in the regulated output. VPRI is regulated to 16V + 7k (VFB/R2), where VFB/R2 is equal to the current an19fc AN19-35 Application Note 19 through R2, and the 7k is an internal resistor. VOUT is therefore equal to: ⎡ ⎛ V ⎞⎤ VOUT = N ⎢16 + 7k ⎜ FB ⎟ ⎥ − VF ⎝ R2 ⎠ ⎦ ⎣ The smallest integer ratio with N close to 0.872 is 7:8 = 0.875. T1 is to be wound with this turns ratio for each output. The total number of turns is determined by the required primary inductance (LPRI). This inductance has no optimum value; it is a trade-off between core size, regulation requirements and leakage inductance effects. A reasonable starting value is found by assigning a maximum magnetizing current (ΔI) of 10% of the peak switch current of the LT1070. Magnetizing current is the difference between the primary current at the start of switch “on” time and the current at the end of switch “on” time. This gives a value for LPRI of: (91) and the required transformer turns ratio is: N= VOUT + VF ⎛V ⎞ 16 + 7k ⎜ FB ⎟ ⎝ R2 ⎠ (92) The term, 7k (VFB/R2) is normally set to ≈2V to allow some adjustment range in VOUT. Solving for N in Figure 25, with VOUT = 15V: N= LPRI = 15 + 0.7 = 0.872 16 + 2 VIN ⎛ V ⎞ ΔI f ⎜ 1 + IN ⎟ ⎝ VPRI⎠ (93) ( )( ) ΔI = primary magnetizing current VPRI = regulated primary flyback voltage OPTIONAL OUTPUT FILTER R4 1.5k L1 10μH D1 1: N + C3 0.47μF N N + VIN C1 500μF C4 500μF 15V + C0M + L2 10μH VSW VIN 5V C5* 100μF + –15V FB VC 500Ω C2 0.01μF R2 5k * REQUIRED IF INPUT LEADS ≥ 2" NOTE: ANY NUMBER OF OUTPUTS CAN BE USED WITH THIS CONFIGURATION. TRANSFER THE SUM OF ALL OUTPUT POWERS TO A SINGLE OUTPUT WHEN USING THE FORMULAS: IOUT = ≈16V VIN 0 C6 200μF N = 0.875 = 7:8 FOR VOUT = 15V LT1070 GND C5 200μF tON ∑POUT VOUT SWITCH VOLTAGE tOFF VOUT + VF (VF = DIODE FORWARD VOLTAGE) SECONDARY VOLTAGE 0V AN19 F25 N • VIN Figure 25. Totally Isolated Converter an19fc AN19-36 Application Note 19 For VIN = 5V, ΔI = 0.5A, VPRI = 18V: LPRI = ( ) 5 ( ) 0.5 ⎛ 40 • 103 ⎞ 1 + 5 / 18 ⎝ ⎠ tL = = 196μH Again, this value is not an optimum figure, it is simply a compromise between maximum output current and core size. A second consideration on primary inductance is the transition from continuous mode to discontinuous mode. At light output loads, the flyback pulse across the primary will drop toward zero before the end of switch “off” time. The LT1070 interprets this as a drop in output voltage and raises duty cycle to compensate. This results in an abnormally high output voltage. To avoid this situation, the output should have a minimum load equal to: (VPRI • VIN) IOUT(MIN) = 2 (VPRI + VIN) (2VOUT)(f)(LPRI) 2 (94) with VPRI = 18V, VIN = 5V, VOUT = 15V, LPRI = 200μH: (18 • 5) IOUT(MIN) = 2 (18 + 5) (2 • 15)⎛⎝ 40 • 103⎞⎠ ⎛⎝ 200 • 10−6⎞⎠ 2 = 64mA This current may be shared equally on each output at 32mA per output. If a lighter minimum load is desired, primary inductance must be increased. This also increases leakage inductance, so some care must be used. Leakage inductance is a portion of the primary which is not coupled to the secondary. This leakage inductance will create a flyback spike following switch opening. The height of this spike must be clamped with a snubber (R4, C3, D2) to avoid overvoltage on the switch. (Please read snubber details in the section on normal mode flyback regulators). The width of the leakage inductance spike is equal to: (IPRI)(LL) (95) VM − VPRI − VIN LL = leakage inductance IPRI = peak primary current VM = peak switch voltage This spike width is important because it must be less than 1.5μs wide. The LT1070 has internal blanking for ≈1.5μs following switch turn-off. This blanking time ensures that the flyback error amplifier will not interpret the leakage inductance spike as the actual flyback voltage to be regulated. To avoid poor regulation, the spike must be less than the blanking time. If transformer T1 is trifilar wound for minimum leakage inductance, LL may have a typical value of 1.5% of LPRI. Assuming LPRI = 200μH, LL would be 3μH. To calculate tL, we still need to assign a value to VM. In this case, with VIN = 5V, a conservative value for maximum switch voltage would be VM = 50V. If we assume a maximum primary current of 5A for maximum output current, spike width is: 5⎛ 3 • 10−6 ⎞ ⎝ ⎠ tL = = 0.56μs 50 − 18 − 5 This is well within the maximum value of 1.5μs. Note, however, that the pulse width grows rapidly as the sum of VPRI + VIN approaches maximum switch voltage. The following formula will allow one to calculate the maximum ratio of leakage inductance to primary inductance in a given situation. LL (MAX) = LP ⎛ tL VM − VP − VIN ΔI f ⎜ 1 + ⎝ ( )( )( ) IPRI (VIN) VIN⎞ VP ⎟⎠ (96) With a fairly large VIN (36V), even if we use a less conservative value of 60V for VM, with tL = 1.5μs, VP = 18V, ΔI = 0.5A and IPRI = 5A: LL (MAX) = LP ⎛ 1.5 • 10−6 ⎞ 60 − 18 − 36 0.5 ⎛ 40 • 103 ⎞ ⎛ 1 + 36 ⎞ ⎝ ⎠ ⎜⎝ 18 ⎟⎠ ⎝ ⎠ ( )( ) 5(36) = 0.003 = 0.3% an19fc AN19-37 Application Note 19 This low ratio of leakage inductance to primary inductance would be nearly impossible to wind, so some compromises must be made. If maximum output current is not required, IPRI will be less than 5A, (see formula 99). Ripple current (ΔI) can also be increased. Finally, an LT1070HV (high voltage) part can be used, with a switch rating of 75V. Substituting IPRI = 2.5A, ΔI = 1A, VM = 70V into the above calculation yields LL/LPRI = 3%, which is easily achievable. Maximum output power with an isolated flyback converter is less than an ordinary flyback converter because transformer turns ratio is fixed by output voltage. This fixes duty cycle at: DC = VPRI VPRI + VIN (97) and maximum power is limited to: POUT(MAX ) = This formula is actually a quadratic, but rather than solve it explicitly, a much simpler technique, for the range of IPRI involved, is to calculate the first two terms on the right, then use this value of IPRI to calculate the last term. For the circuit in Figure 25 with IOUT = 0.25A on each output, VPRI = 18V, VIN = 5V, ΔI = 0.5A, R = 0.2Ω: (15)(0.5)(18 + 5) + 0.5 + (2.64) (0.2) = 2.92A IPRI = 2 5 0.8 (18)(5) 2 2.64A The transformer must be sized so that the core does not saturate with 2.92A in the primary winding. Note that there is plenty of margin on 5A maximum switch current. A smaller core could be used if ΔI were increased to 1A, cutting primary inductance in half. (See section on inductors and transformers.) Output Capacitors ⎛ VPRI ⎞ ⎡ ⎛ 2 ⎤ ΔI⎞ V I I − − ⎢ ⎜ V + V ⎟ IN⎜ P 2 ⎟ P R⎥ 0.8 ⎝ PRI IN⎠ ⎢⎣ ⎝ ⎠ ⎥⎦ () ( ) (98) R = LT1070 Switch “on” resistance IP = maximum switch current 0.8 = fudge factor to account for losses in addition to R With VPRI at a nominal 18V, VIN = 5V, IP = 5A, ΔI = 0.5A, duty cycle is 78% and maximum output power is: Flyback regulators do not utilize the inductance of the transformer as a filter, so all filtering must be done by the output capacitors, C1 and C4. They should be low ESR types to minimize output ripple. In general, output ripple is limited by the ESR of the capacitor, not the actual capacitance. Output ripple in peak-to-peak volts is given by: VP-P = POUT(MAX ) = (100) *This factor of 2 is used because of dual outputs ⎤ ⎛ 18 ⎞ ⎡ ⎛ 0.5 ⎞ 2 5 5 5 0 . 2 − − ⎢ ⎥ 0.8 = 11.74W ⎜ 18 + 5⎟ ⎜ 2 ⎟⎠ ⎝ ⎠ ⎢⎣ ⎝ ⎥⎦ ( )( )( ) With IPRI = 2.92A, N = 0.872 and assigning an ESR of 0.1Ω, output ripple is: An analysis of the power formula shows that at low VIN, maximum output power is proportional to VIN, and at high VIN, maximum power approaches 50W. Peak primary current for loads less than the maximum is found from: (VOUT )(IOUT)(VPRI + VIN) + ΔI + (IPRI) R IPRI = VIN 2 0.8 (VPRI)(VIN) IPRI (ESR) 2 *N 2 (99) VP-P = (2.92)(0.1) = 167mV at full load P-P (2)(0.872) Had we based the output ripple formula on the actual output capacitance, rather than its ESR, the result would have been ≈10mV, showing that ESR effects do dominate. The 0.1Ω value chosen for ESR is probably higher than an19fc AN19-38 Application Note 19 typical for a good 500μF capacitor, but less than guaranteed maximum. Note that one reason for high output ripple in this circuit is that the converter is operating at a rather high duty cycle of 78% because of the low input voltage. This leaves only 22% of the time for the secondary to be delivering current to the load. As a consequence, secondary peak currents, and therefore output ripple, are high. RW is inserted in series with the ground pin. When a load is applied to the output, input current flowing through RW causes the voltage drop across R2 to increase. This increases regulated primary voltage and thereby output voltage, cancelling the open-loop load regulation effects mentioned earlier. Line regulation is also significantly improved at full load. If low output ripple is required, an output filter may be a better choice than simply using huge output capacitors. See Output Filters section. The value of RW is found from: RW = Load and Line Regulation Load and line regulation are affected by many “open loop” factors in this circuit because the actual output voltage is not sensed—only the primary. Some of these factors are core nonlinearities, diode resistance, leakage inductance, winding resistance, (including skin effect) capacitor ESR and secondary inductance. A typical load regulation for this circuit with a load variation from 20% to 100% is ≈3%. Line regulation at light loads is better than 0.3% for VIN = 4.5V to 5.5V, but degrades to ≈1% for full loads. With multiple output supplies obtained from a single switching loop, the problem of cross regulation appears. In this supply, and increase in load current from 50mA to 200mA on one output, with a constant 50mA load on the second output, will cause the loaded output to drop 280mV and the constant load output to rise 100mV. If improved line and load regulation are necessary, a modification can be made to the basic circuit as shown below: R2 is split into two resistors with the center tap coupled to the ground pin of the LT1070 through CW. A small resistor +VIN VIN RO = output resistance without compensation = ΔVOUT/ΔIOUT E = efficiency ≈ 0.75 *Multiply N by two for dual outputs For the circuit in Figure 25, RO is found by loading both outputs simultaneously and summing the changes of the two outputs. With 3% load regulation, at ΔIOUT = 200mA, this is a total output change of 900mV. RO is then 900mV divided by a current change of 200mA, or 4.5Ω. VOUT is the sum of the two outputs, = 30V, N is (0.875)(2) = 1.75 and R2 is ≈1.2k: RW = (4.5)(5)(0.75)(1, 200) = 0.055Ω (30)(7k)(1.75) This low value of resistance preserves the efficiency of the converter, but is sometimes hard to find “off the shelf.” A 15" length of #26 hookup wire was used for the breadboard. To minimize inductance, the wire is folded in half before winding around a form. LT1070 + FB GND 5k VC C2 0.01μF RW ≈0.055Ω –VIN (101) CW must be made large enough to prevent loop oscillation problems. The product of CW times the parallel resistance of the two halves of R2 should be several times larger than the basic regulator settling time constant. Load Current Compensation INPUT BYPASS CAPACITOR TIE TO TOP OF RW (RO )(VIN)(E)(R2) (VOUT )(7k)(N) * CW 10μF R2 + 270Ω With load regulation compensation, the effects of cross regulation are worse than with no compensation. Multiple output supplies should be carefully evaluated for all expected conditions of output loading. AN19 TA01 an19fc AN19-39 Application Note 19 A1 is an LM308 selected because its output goes low when both its inputs are equal to the op amp negative supply voltage. This condition occurs at VOUT = 0V during start-up. If the op amp output went high during this condition, the LT1070 would never start up. R1 and R2 set output voltage, with the bottom of R1 returned directly to the load for “low” sensing. R4 and R5 force Kelvin sensing between the output and the ground pin of the LT1070. It appears that these resistors are shorted out, but the voltage drop across the wire from the ground pin of the LT1070 to the output will cause load regulation problems unless it is “sensed” by R4 and R5. These resistors can be eliminated if that wire is heavy gauge and less than 2" long. Frequency Compensation The frequency compensation capacitor C2, is much lower in this design than in others because the gm of the LT1070 is much lower in the isolated mode than in the normal mode. See Frequency Compensation section for details. POSITIVE CURRENT-BOOSTED BUCK CONVERTER A current-boosted buck converter is shown in Figure 26. It can supply more output current than a standard buck converter or a flyback converter for larger input-output differentials because current flows to the output both when the switch is on and when it is off. The “on” cycle can supply up to 5A to the load. The off cycle will deliver 1/N times that much current. With N = 1/3, current delivered to the load during switch off time will be 15A. Total available load current will depend on switch duty cycle, which in turn is fixed by input voltage. The following equations should be helpful in designing variations of this circuit. R5 = An operational amplifier must be added to generate a feedback signal which floats on top of the regulated output because that is where the ground pin of the LT1070 is tied. (VOUT)(R1) = (VOUT)(1.24k) 1.244V VREF R5 R1 = R4 R2 (102) (103) VIN 28V C3 0.47μF 470Ω 2W R6 470Ω C6 0.002μF D2 VIN 1:N VSW LT1070 N = 0.25 R7 1k R2 1.24k FB VC C1 0.33μF 6 C4 0.01μF + C5* 100μF 2 V+ LM308 V– 3 4 COMP 8 7 R3 680Ω + D1 VIN – GND 200pF R5 5k R4 1.24k R8 100Ω MINIMUM LOAD = 5mA *REQUIRED IF INPUT LEADS ≥ 2" R1 5k + VOUT 5V 10A C2 5000μF AN19 F26 Figure 26. Positive Current Boosted Buck Converter an19fc AN19-40 Application Note 19 N(MIN) = DC = VOUT + VF VM − VIN − VSNUB VOUT + VF ( VOUT + VF + N VIN − VOUT LPRI = ⎛ VOUT N = turns ratio VM = LT1070 maximum switch voltage VSNUB = snubber voltage (see Flyback section) VF = forward voltage of D1 DC = switch duty cycle ΔI = peak-to-peak primary ripple current ESR = effective series resistance of C2 IPRI = average primary current during switch-on time VP-P = peak-to-peak output ripple voltage IP = maximum rated switch current for LT1070 (104) ) (105) ⎞ (ΔI)(f)⎜⎝N + VINV−OUTVOUT ⎟⎠ (106) ⎛ VOUT ⎞ ⎜ N + VIN − VOUT⎟ 1 − N ⎝ ⎠ VP-P = ESR IOUT VIN ( ) ( )( ) The value for NMIN is based on switch breakdown. Low values give higher output current, but also higher switch voltage. ΔI is normally chosen at 20% to 40% of IPRI. Note that the ripple equation contains the term (1 – N) in the numerator, implying that output ripple current and voltage will be zero for N = 1. This is because of the simplifying assumption that ripple current into the output capacitor is the difference between primary and secondary current. This difference is zero for N = 1 and the equation is no longer valid. (107) IOUT(MAX ) = ⎡ ⎛ VIN ΔI⎞ ⎢ I − ⎜ P 2 ⎟⎢ ⎝ ⎠ VOUT + VF + N VIN − VOUT ⎣ ( [ ( I IPRI = OUT VOUT + N VIN − VOUT VIN ⎤ ⎥ 0.8 ⎥ ⎦ )( ) (108) NEGATIVE CURRENT-BOOSTED BUCK CONVERTER )] The negative buck converter in Figure 27 is capable of much higher output current that the standard buck converter upper limit of 5A. For design details, see Positive Current-Boosted Buck Converter and standard Negative Buck Converter sections. (109) (Add ΔI/2 for peak primary current) + C1 R1 MINIMUM LOAD = 10mA –VOUT R5 C3 T1 R4 12k D1 VIN + 1:N VSW Q1 2N3906 – 0.6V V R1 = OUT 1mA LT1070 FB GND VC R3 R2 1.24k C2 AN19 F27 –VIN Figure 27. Negative Current Boosted Buck Converter an19fc AN19-41 Application Note 19 NEGATIVE INPUT/NEGATIVE OUTPUT FLYBACK CONVERTER shown for proper output sensing. Further design details may be taken from Positive Flyback Converter section. This circuit in Figure 28 is normally used for negative output voltages higher than the negative input. If voltages lower than the input are required, see Negative Buck Converter or Negative Current-Boosted Buck Converter and standard Negative Buck Converter sections. POSITIVE-TO-NEGATIVE FLYBACK CONVERTER The voltage divider, R1 and R2, is required to prevent forward bias on Q1. Connect R1, R2 and R3 exactly as C3 The positive input-negative output flyback converter in Figure 29 requires an external op amp to generate the feedback signal for the LT1070. R1 and R2 set output voltage with R1 scaled at 1kΩ/V. The bottom of R1 goes directly to the output for sensing. R3 and R4 provide the T1 R6 R2 5k R3 1k + 1:N VIN C1 Q1 2N3906 R1* VSW + LT1070 –VOUT FB GND – 1.6V V R1 = OUT 200μA VC R4 1.24k R5 C2 AN19 F28 –VIN Figure 28. Negative Input-Negative Output Flyback Converter VIN R7 C4 1/2 T1 D2 VIN VSW + LT1070 R2 1.24k R5 1k FB VIN VC C3 0.01μF LM308 R1 = 1k (VOUT) + R6 – GND C2 200pF R3 1.24k R4 = R1 + C1 1/2 T1 D1 –VOUT AN19 F29 Figure 29. Positive Input-Negative Output Flyback Converter an19fc AN19-42 Application Note 19 ground (low) sense. Any voltage drop between the ground pin of the LT1070 and the actual ground (+) output can cause load regulation problems. These are eliminated if R3 and R4 are connected exactly as shown. R3 and R4 can be eliminated if the LT1070 ground pin is connected directly to output ground with a very short heavy wire. For design details, see Positive Flyback Converter. VOLTAGE-BOOSTED BOOST CONVERTER The standard boost converter has a maximum output voltage slightly less than the maximum switch voltage of the LT1070. If higher voltages are desired, the inductor can be tapped as shown in Figure 30. The effect of the tap is to reduce peak switch voltage by: ⎛ ⎞ (VOUT − VIN)⎜⎝ 1+NN⎟⎠ N( MIN) = DC = VOUT − VM + VSNUB VM − VIN − VSNUB ( ) (111) VOUT + N VIN ( ) ( ) ΔI VIN 2 IOUT(MAX ) = VOUT + N VIN IP IPRI = [ ( )] Average during switch-on time. For peak, add ΔI/2. volts ( ) (ΔI)(f)[VOUT + N(VIN)] VIN VOUT − VIN ΔI ≈ 20% to 40% of IPRI VP-P = C3 0.68μF D2 1 L1 N=5 VSW + LT1070 D1 R1 98k FB GND VC R3 10k R2 1.24k (113) VIN A snubber is needed now to handle leakage inductance of the tap point. The following formulas will be helpful for variations on this design. VIN 15V (112) IOUT VOUT + N VIN LPRI = VIN (110) VOUT − VIN A large value for N will allow high output voltages to be regulated without exceeding maximum switch voltage. R4 680Ω 1W (use max VIN) + TOTAL INDUCTANCE = 4mH INTERLEAVE PRIMARY AND SECONDARY FOR LOW LEAKAGE INDUCTANCE VOUT 100V 300mA C1 200μF C2 0.047μF AN19 F30 Figure 30. Voltage-Boosted Boost Converter (114) (IOUT)(ESR)[VOUT + N(VIN)] VIN (N + 1) (115) DC = switch duty cycle VSNUB = snubber voltage (see Flyback section for details) VM = maximum allowed LT1070 switch voltage IP = maximum LT1070 switch current ΔI = peak-to-peak primary current ripple ESR = effective series resistance of C VP-P = peak-to-peak output voltage ripple L1 should be wound for minimum leakage inductance by using bifilar winding or interleaved windings. R3 and C2 are selected using the technique described in the frequency compensation section. For snubber details see Flyback description section. This regulator is not shortcircuit proof because L1 and D1 short input to ground when output is shorted. an19fc AN19-43 Application Note 19 NEGATIVE BOOST CONVERTER The LT1070 can be used as a negative boost regulator as shown in Figure 31 by using the same diode-coupled feedback technique used in the positive buck mode. Basically, D2 and C3 create a peak detector which gives a voltage across C3 equal to the output voltage. R1 and R2 act as a voltage divider to set output voltage at: (VREF)(R1 + R2)/R2 C3 also acts as a floating power supply for the LT1070. The ground pin of the LT1070 switches back and forth between the output voltage and ground to drive the inductor, L1. For proper circuit operation, a minimum preload of 10mA is required on the output (shown as RO). For further design information, see Positive Boost Converter section for details on L1, C1, D1 and output filters. The feedback scheme used here is discussed in more detail in the Positive Buck section. A refinement in the feedback is that the power transistor driver current flowing into the VIN pin must come from D2 and C3. This tends to compensate for the series resistance of D1 as it affects load regulation. is set by the ratio of R1 to R2. R4 is used to limit the effect of turn-on spikes across the main catch diode, D1. Without this resistor, D1 turn-on spikes would cause C3 to charge to an abnormally high voltage and the output voltage would sag down at high load currents. D3 and C4 are used to generate a floating supply for the LT1070. The voltage across C4 will peak detect to (VOUT) volts. R5 is added to ensure start-up. R6 is a preload, required only if the normal load can drop to zero current. For further design details on this circuit, the basic formulas from the Negative-to-Positive Buck/Boost Converter may be used, along with the feedback explanation from the Positive Buck Converter. Positive-to-Negative Buck Boost Converter D3 1N4001 R5 470Ω, 1W VIN C4 5μF VSW + FB GND R1 27k C1 1000μF LT1070 C4* 470μF VIN –15V FB + GND R3 3.3k L1 200μH + VC R2 1.24k C2 0.22μF VC R3 R2 5k 1.24k C2 0.1μF VIN + RO (MINIMUM LOAD) D2 R4 1N914 47Ω R1 10.7k LT1070 D2 VSW VIN C5* 10V TO 30V 100μF *REQUIRED IF INPUT LEADS ≥2" + C3 2μF + D1 L1 200μH C1 1000μF R6 470Ω VOUT –12V 2A AN19 TA02 C3 10μF D1 *REQUIRED IF INPUT LEADS ≥2" CURRENT-BOOSTED BOOST CONVERTER VOUT –28V 1A AN19 F31 Figure 31. Negative Boost Regulator POSITIVE-TO-NEGATIVE BUCK BOOST CONVERTER This positive-to-negative converter uses the same feedback technique as the positive buck converter. Normal feedback cannot be used because the ground pin of LT1070 is switching back and forth between +VIN and – VOUT. To generate a floating feedback signal, D2 peak detects the output voltage during the LT1070 switch-off time. This voltage appears across C3 as a floating DC level which is used as feedback to the LT1070. Output voltage This tapped inductor version of the boost converter can offer significant increases in output power when the inputoutput voltage differential is not too high. The ratio of output current for this converter compared to a standard boost converter is: IOUT IBOOST = N+1 ⎛ V ⎞ N ⎜ 1 − IN ⎟ + 1 ⎝ VOUT ⎠ If VOUT → VIN, the increase in output current approaches N + 1. Maximum N, however, is limited by switch breakdown voltage; an19fc AN19-44 Application Note 19 V −V −V N( MAX) = M OUT SNUB VOUT − VMIN VOUT − VMIN ⎛V N ⎞ f ΔI ⎜ OUT − ⎟ ⎝ VMIN N + 1⎠ 28 − 16 = = 277μH ⎛ 40 • 103 ⎞ 1 ⎛ 28 − 2 ⎞ ⎝ ⎠ ⎜⎝ 16 3 ⎟⎠ L TOTAL = VM = maximum LT1070 switch voltage VSNUB = snubber voltage (see Flyback section) VMIN = minimum input voltage () For VM = 60V, VOUT = 28V, VSNUB = 8V, VMIN = 16V, N( MAX) = 60 − 28 − 8 =2 28 − 16 The increase in output current is: IOUT IBOOST = 2+1 = 1.62 = 62% ⎛ 16 ⎞ 2 ⎜ 1− ⎟ + 1 ⎝ 28 ⎠ ( )( ) Snubber values are empirically selected to limit snubber voltage to the value chosen (≈8V). For lowest snubber losses, the “1” and “N” sections of the inductor should be wound for maximum coupling (consult manufacturers). Current-Boosted Boost Converter R4 C3 D1 I Actual maximum output current is: VOUT 28V 4A N D2 IOUT(MAX ) = VIN 5 − 0.5 IP − ΔI / 2 = = 4.15A 28 2 VOUT N − − VMIN N + 1 16 3 IP = maximum LT1070 switch current ΔI = increase in inductor current during switch-on time VOUT − VIN ΔI = ⎛V N ⎞ L f ⎜ OUT − ⎟ ⎝ VIN N + 1⎠ ( )( ) L = total inductance Operating duty cycle is given by: DC = VOUT − VIN ⎛ N ⎞ VOUT − ⎜ ⎟ VIN ⎝ N + 1⎠ ( ) A reasonable value for total inductance is found by assuming that this circuit is used near peak switch current of 5A and allowing a 20% increase in switch current during switch on time→ΔI = 1A: VSW VIN 16V TO 24V R1 27k LT1070 FB GND VC + C1 R2 1.24k R3 C2 AN19 TA03 FORWARD CONVERTER Forward converters can use smaller cores than flyback converters because they do not need to store energy in the core. Energy is transferred directly to the output during switch “on” time. The output secondary (N) is positive and delivering current through D1 when the LT1070 switch is on (VSW low). At switch turn-off, the output winding goes negative and output current flows through D2 as in a buck regulator. A third winding (M) is needed in a single switch forward converter to define switch voltage during switchoff time. This “reset” winding, however, limits the maximum duty cycle allowed for the switch. The voltage across the switch during its off state is: an19fc AN19-45 Application Note 19 V VSW = VIN + IN + VSNUB M For maximum output current, N should be as small as possible. Smaller values of N, however, require larger duty cycles, so N is limited to a minimum of: VSNUB = snubber voltage spike caused by leakage inductance N( MIN) = By rearranging this formula, a minimum value for M can be found: M( MIN) = VM − VIN(MAX ) − VSNUB For the circuit shown, with VF = 0.6V, VIN(LOW) = 20V: N( MIN) = For the circuit shown, with VIN(MAX) = 30V, and selecting VSNUB = 5V and VM = 60V: (1.2 + 1)(5 + 0.6) = 0.62 20 To avoid core saturation during normal operation, primary inductance must be a minimum value determined by core volume and core flux density: 30 = 1.2 60 − 30 − 5 2⎡ ⎤ ⎡ ⎤ ⎢ 0.4π μe ⎥ V + V LPRI ≥ ⎢ OUT F ⎥ ⎢ ⎥ ⎢ N BM f ⎥ ⎢ V ⎛ 10−8 ⎞ ⎥ e ⎣ ⎦ ⎝ ⎠⎦ ⎣ ( )( ) ( )( )( ) ( ) The value of M will define maximum switch duty cycle. If the LT1070 attempts to operate at a duty cycle above this limit, the core will saturate because the volt-second product across the primary in the switch-off state will not be enough to keep flux balance. Duty cycle is limited to: DC(MAX) VIN(LOW ) VF = D1 and D2 forward voltage VIN(LOW) = minimum input voltage VIN(MAX ) VM = maximum LT1070 switch voltage VIN(MAX) = maximum input voltage M( MIN) = (M + 1)(VOUT + VF) BM = maximum operating flux density f = LT1070 operating frequency (40kHz) Ve = core volume μe = effective core permeability 1 1 = = 45% 1 + M 1 + 1.2 Forward Converter D1 R4 C2 I L1 70μH T1 M N + D2 VOUT 5V 6A C1 2000μF D3 VIN VSW VIN 20V TO 30V D4 LT1070 R1 3.74k FB GND VC Q1 R3 R6 330Ω C4 R2 1.24k R5 1Ω C3 AN19 TA04 an19fc AN19-46 Application Note 19 For BM = 2000 gauss (typical for ferrites), Ve = 6cm3, and μe = 1500, VOUT + VF = 5.6V, N = 0.62: 2 ⎡ ⎤ ⎢ ⎥ 5.6 LPRI ≥ ⎢ ⎥ ⎢ 0.62 2000 ⎛ 40 • 103 ⎞ ⎥ ⎝ ⎠⎦ ⎣ = 400μH ( )( ) ⎡ ⎤ ⎢ 0.4π 1500 ⎥ ⎢ ⎥ ⎢ 6 ⎛ 10−8 ⎞ ⎥ ⎝ ⎠ ⎦ ⎣ ( )( () ) The operating flux density of forward converters is often limited by temperature rise rather than saturation. At 2000 gauss, the core loss of a typical ferrite is 0.25W/cm3. Total core loss at Ve = 6cm3 ≈ 1.5W. When this is combined with copper winding losses, there may be excess core temperatures. Larger cores will allow more space for copper, or can be operated at lower flux density with the same copper loss. See Transformer Design guide for further details. Conventional forward converters use a flip-flop to limit maximum duty cycle to 50% and set M = 1. The LT1070 will let duty cycle go to ≈95% during start-up and low input voltage conditions. This would cause core saturation and subsequent primary and switch currents of up to 10A. To avoid this, Q1 and R5 have been added. Onset of core saturation will cause a voltage drop across R5 high enough to turn on Q1 at each cycle. This pulls down on the VC pin, reducing duty cycle and maintaining normal switch currents. R6 and C4 filter out spikes. Operating duty cycle is given by: V +V DC = OUT F N VIN [( )( ) ] = 70μH [(0.2)(6)]⎡⎢⎣(0.62)(25)⎛⎝40 • 10 ⎞⎠ ⎤⎥⎦ 5 0.62 25 − 5 3 Larger values of L1 will increase maximum output current only slightly. Output ripple voltage will go down inversely with larger L1, but physical size will quickly become a problem for large values because the inductor must handle large DC currents. Peak inductor current is equal to IOUT + ΔIL/2. Maximum output current for this forward converter is given by: ⎛I ΔI ΔI ⎞ IOUT(MAX ) = ⎜ P − L − PRI ⎟ 0.9 N ⎠ 2 ⎝N ( ) IP = maximum LT1070 switch current ΔIPRI = peak primary magnetizing current = VOUT/(f)(N)(LPRI) ΔIL = peak-to-peak output inductor current 0.9 = fudge factor for losses For IP = 5A, N = 0.62, ΔIL = 1.2A, ΔIPRI = 0.5A; 1.2 0.5 ⎞ ⎛ 5 IOUT (MAX) = ⎜ − − ⎟ (0.9) = 6A ⎝ 0.62 2 0.62⎠ Output voltage ripple (P-P) is assumed to be set by L1 and the ESR of C1: VP-P = ΔIL ESR1 = The output filter inductor (L1) is chosen as a trade-off between maximum output power, output ripple, physical size and loop transient response. A reasonable value is one which gives a peak-to-peak inductor ripple current (ΔIL) of ≈ 20% of IOUT. This leads to a value for L1 of: [( )( ) ] [(0.2)(I )][(N)(V )(f)] VOUT N VIN − VOUT OUT L1 = ( )( ) ( )( ) L1 = for IOUT = 6A, VIN = 25V, VOUT = 5V, N = 0.62: IN ( )[ ( ) (L1)(f)(N)(VIN) ESR1 VOUT N VIN − VOUT ] ESR1 = effective series resistance of C1 If we assume 0.02Ω for ESR1, and VIN = 25V, VP-P = (0.02)(5)[(0.62)(25) − 5] ⎛ 70 • 10− 6⎞ ⎛ 40 • 103⎞ 0.62 25 )( ) ⎝ ⎠⎝ ⎠( = 24mVP-P an19fc AN19-47 Application Note 19 If less output ripple is desired, the most effective method may be to add an LC filter. See section on Output Filters. FREQUENCY COMPENSATION Although the architecture of the LT1070 is simple enough to lend itself to a mathematical approach to frequency compensation, the added complication of input and/or output filters, unknown capacitor ESR, and gross operating point changes with input voltage and load current variations all suggest a more practical empirical method. Many hours spent on breadboards have shown that the simplest way to optimize the frequency compensation of the LT1070 is to use transient response techniques and an “R/C box” to quickly iterate toward the final compensation network. There are many ways to inject a transient signal into a switching regulator, but the suggested method is to use an AC coupled output load variation. This technique avoids problems of injection point loading and is general to all switching topologies. The only variation required may be an amplitude adjustment to maintain small signal conditions with adequate signal strength. Figure 32 shows the setup. A function generator with 50Ω output impedance is coupled through a 50Ω/1000μF series RC network to the regulator output. Generator frequency is noncritical. A good starting point is ≈ 50Hz. Lower frequencies may cause a blinking scope display which is annoying to work with. Higher frequencies may not allow sufficient settling time for the output transient. Amplitude of the generator output is typically set at 5VP-P to generate a 100mAP-P load variation. For lightly loaded outputs (IOUT < 100mA), this level may be too high for small signal response. If the positive and negative transition settling waveforms are significantly different, amplitude should be reduced. Actual amplitude is not particularly important because it is the shape of the resulting regulator output waveform which indicates loop stability. A 2-pole oscilloscope filter with f = 100kHz is used to block switching frequencies. Regulators without added LC output filters have switching frequency signals at their outputs which may be much higher amplitude than the low frequency settling waveform to be studied. The filter frequency is high enough to pass the settling waveform with no distortion. Oscilloscope and generator connections should be made exactly as shown to prevent ground loop errors. The oscilloscope is sync’d by connecting channel “B” probe to the generator output, with the ground clip of the second probe connected to exactly the same place as channel “A” ground. The standard 50Ω BNC sync output of the generator should not be used because of ground loop errors. It may also be necessary to isolate either the generator or oscilloscope from its third wire (earth ground) connection in the power plug to prevent ground loop errors in the ’scope display. These ground loop errors are checked by connecting channel “A” probe tip to exactly the same point as the probe ground clip. Any reading on channel “A” indicates a ground loop problem. Once the proper setup is made, finding the optimum values for the frequency compensation network is fairly straightforward. Initially, C2 is made large (≥ 2μF) and R3 is made small (≈ 1k). This nearly always ensures that the regulator will be stable enough to start iteration. Now, if the regulator output waveform is single-pole overdamped, (see the waveforms in Figure 33) the value of C2 is reduced in steps of about 2:1 until the response becomes slightly underdamped. Next, R3 is increased in steps of 2:1 to introduce a loop “zero.” This will normally improve damping and allow the value of C2 to be further reduced. Shifting back and forth between R3 and C2 variations will now allow one to quickly find optimum values. If the regulator response is underdamped with the initial large value of C, R should be increased immediately before larger values of C are tried. This will normally bring about the overdamped starting condition for further iteration. Just what is meant by “optimum values” for R3 and C2? This normally means the smallest value for C2 and the largest value for R3 which still guarantee no loop oscillations, and which result in loop settling that is as rapid as possible. The reason for this approach is that it minimizes the variations in output voltage caused by input ripple voltage and output load transients. A switching regulator which is grossly overdamped will never oscillate, but it may have unacceptably large output transients following sudden changes in input voltage or output loading. It may an19fc AN19-48 Application Note 19 also suffer from excessive overshoot problems on startup or short circuit recovery. To guarantee acceptable loop stability under all conditions, the initial values chosen for R3 and C2 should be checked under all conditions of input voltage and load current. The simplest way of accomplishing this is to apply load currents of minimum, maximum and several points in between. At each load current, input voltage is varied from minimum to maximum while observing the settling waveform. The additional time spent “worst-casing” in this manner is definitely necessary. Switching regulators, unlike linear regulators, have large shifts in loop gain and phase with operating conditions. If large temperature variations are expected for the regulator, stability checks should also be done at the temperature extremes. There can be significant temperature varia- SCOPE FILTER SWITCHING REGULATOR* GND VC OUTPUT 1k 0.015μF 50Ω 1W R3 VIN IOUT C2 10k A B 1500pF 1000μF (OBSERVE POLARITY) SCOPE GROUND CLIP 50Ω GENERATOR f ≈ 50Hz AN19 F32 *ALL INPUT AND OUTPUT FILTERS MUST BE IN PLACE. INPUT SOURCE (VIN) MUST BE ACTUAL SOURCE USED IN FINAL DESIGN TO ACCOUNT FOR FINITE SOURCE IMPEDANCE Figure 32. Testing Loop Stability GENERATOR OUTPUT REGULATOR OUTPUT WITH LARGE C, SMALL R WITH REDUCED C AND SMALL R EFFECT OF INCREASED R FURTHER REDUCTIONS IN C MAY BE POSSIBLE IMPROPER VALUES WILL CAUSE OSCILLATIONS Figure 33. Output Transient Response an19fc AN19-49 Application Note 19 tions in several key component parameters which affect stability; in particular, input and output capacitor value and their ESR and inductor permeability. LT1070 parametric variations also need some consideration. Those which affect loop stability are error amplifier gm and the transfer function of VC pin voltage versus switch current (listed as a transconductance under electrical specifications). For modest temperature variations, conservative overdamping under worst-case room temperature conditions is usually sufficient to guarantee adequate stability at all temperatures. This is potentially more dangerous than a dip because a large overshoot may destroy loads still connected to the regulator output. Eliminating Start-Up Overshoot Another transient condition to be checked is start-up overshoot. When input voltage is first applied to a switching regulator, the regulator dumps full short-circuit current into the output capacitor attempting to bring the output up to its regulated value. The output can then overshoot well beyond its design value before the control loop is able to idle back the output current. The amplitude of the overshoot can be anywhere from millivolts to tens of volts depending on topology, line and load conditions and component values. This same overshoot possibility exists for output recovery from output shorts. Again, larger output capacitors, smaller inductors and faster loop response help reduce overshoot. There are also several ways to force slow start-up to eliminate the overshoot. The first is to put a capacitor across the output voltage divider. This creates a time-dependent output voltage setting during start-up and usually eliminates overshoot. This capacitor also has an effect on feedback loop characteristics during normal operation and it can create unacceptably large negative transients on the feedback pin if the output voltage is high and a sudden output short occurs. The transient problem is eliminated by inserting a resistor in series with the feedback pin (see Feedback Pin part of Pin Description section). If undesirable loop characteristics are created by the capacitor, they can be eliminated by diode coupling the capacitor as shown in Figure 34. Check Margins One measure of stability “margin” is to vary the selected values of both R and C by 2:1 in all possible combinations. If the regulator response remains reasonably well damped under all line and load conditions, the regulator can be considered fairly tolerant of parametric variations. Any tendency towards an underdamped (ringing) response indicates that a more conservative compensation may be needed. There are several large signal dynamic tests which should also be done on a completed regulator design. The first is to check response to the worst-case large amplitude load variation. A sudden change from light load to full load current may cause the regulator to have an unacceptably large transient dip in output voltage. The simplest cure for this is to increase the size of the output capacitor. Lower inductor values and less conservative frequency compensation also help. A second consideration is the output overshoot created when a large load is suddenly removed. R1 R4 LT1070 GND RFB CX ≈1μF R1 CX DIODES DISCONNECT CX DURING NORMAL OPERATION AND ELIMINATE NEED FOR RFB. FB VC R2 C4 ≈1μF VOUT VOUT VIN R2 RZ 20k AN19 F34 THIS RESISTOR REQUIRED FOR HIGH OUTPUT VOLTAGES (VOUT ≥ 15V) Figure 34. Eliminating Start-Up Overshoot an19fc AN19-50 Application Note 19 Another general technique for forcing slow start-up is to clamp the VC pin to a capacitor, C4. The value of R4 is chosen to give a voltage across RZ of 2V at worst-case low input voltage (IR4 = 100μA). C4 is then selected to ramp VC slow enough to eliminate start-up overshoot. C4 should be made no larger than necessary to prevent long reset times. A momentary drop to zero volts at the input may not allow enough time for C4 to discharge fully. If input dropouts of less than 5R4C4 seconds are anticipated, R4 should be paralleled with a diode (cathode to input) for fast reset. output conditions and at the point where output voltage just begins to fall below its regulated value. EXTERNAL CURRENT LIMITING The LT1070 is externally current limited by clamping the VC pin. The techniques shown in Figures 35 to 39 are just a few of the ways this can be accomplished. The LT1070 has internal switch current limiting which operates on a cycle-by-cycle basis and limits peak switch current to ≈ 9A at low duty cycles and ≈ 6A at high duty cycles. The actual output current limit value may be much higher or lower depending on topology, input voltage and output voltage. The following formulas give an approximate value for output current limit under short-circuit OVERLOAD CURRENT (AMPS) SHORT CIRCUIT CURRENT (AMPS) Buck 5 to 8 ≈8 Boost (5 to 8)(VIN / VOUT) Not Allowed 5 to 8 ≈8 Buck-Boost (Inverting) (1+ VOUT / VIN ) ⎛ ⎞ ⎝ ⎠ CurrentBoosted Buck (5 to 8)⎜⎜ VOUT + N(VVININ − VOUT)⎟⎟ VoltageBoosted Boost (5 to 8)⎜⎜ VOUT V+INN(VIN)⎟⎟ ⎛ ⎞ ⎝ ⎠ 5 to 8 Flyback (Continuous) ( Flyback (Discontinuous) Depends on L ) VOUT / VIN + N ≈8/N Not Allowed ≈8/N ≈8/N CurrentBoosted Boost (VOUT / VIN) − (N /N + 1) Not Allowed Forward 5 to 8/N ≈8/N 5 to 8 These formulas show that short-circuit current can be much higher than full load current for some topologies. If either full load current or short circuit is much higher than is required for a specific application, external current limiting can be added. This has the advantage of reducing stress on external components, avoiding overload on the input supply and reducing heat sink requirements on the LT1070 itself. The relationship between switch current limit point and VC clamp voltage is approximately: ISW(MAX) = 9 (VC –1) –3 • (DC) amps DC = switch duty cycle This relationship is somewhat temperature dependent. The current limit point falls at about 0.3%/°C, so the value set at room temperature should be factored to allow for adequate current limit at higher temperatures. Also, the factor “9” and “3” vary ±30% in production, so a conservative design will normally clamp switch current to about twice the value needed for maximum load current. This can result in rather high short-circuit currents, so the current limit scheme may want to include “foldback,” wherein the peak switch current is clamped to a lower value with VOUT = 0V. By varying the amount of foldback, the short-circuit current can be made greater than, equal to, or less than full load current. Simple current limiting is shown in Figure 35. VX is an external voltage which could be a separate regulated voltage or the unregulated input voltage. R2 is selected to give approximately 2V across R1. The value of R1 is kept to 500Ω or below to keep the knee of the current limit as sharp as possible. If individual adjustment is not necessary, R1 can be replaced with a fixed resistor. (Note that in some topologies the ground, VC and FB pins of the LT1070 are switching at high voltage levels. This will require VX to be referenced to the LT1070 ground pin, not system ground.) an19fc AN19-51 Application Note 19 In Figure 36, D1 has been replaced with a PNP transistor to reduce the current drain through R1 to 100μA. This is helpful in situations where the LT1070 is used in the total shutdown mode. In Figure 37, foldback current limiting is generated by clamping the VC pin to an output voltage divider. This will reduce short-circuit current by an amount which depends on the relative values of R3, R4 and R5. R5 is needed to prevent “latch off,” wherein the output current drops to zero during short circuit and stays at zero even if the short is removed. If this latch-off action is desirable, R5 can be eliminated. A normally closed “start” switch can then be placed in series with D1. If nonzero short-circuit current is desired, R5 is selected to give desired short-circuit current and R4 is adjusted for full load current limit. There is some interaction, so R4 should be set to about midspan for initial selection of R5. If less interaction is desired between R4 and R5 adjustments, a 470Ω resistor can be inserted in series with the wiper on R4 to form a voltage divider with R5. A current transformer (T1) is used in Figure 38 to generate a more precise current limit. The primary is placed in series with the output switching diode for buck, flyback and buck/ boost configurations. Output diode peak current is limited to: IPEAK = N⎛ V • R4 ⎞ VBE + OUT ⎜ R5 ⎝ R3 + R4 ⎟⎠ VBE = base-emitter voltage of Q1 The R3/R4 divider provides foldback as shown in the formula, with short-circuit diode current limited to N(VBE/R5). In a typical application, R3 is selected to set the voltage across R4 to ≈1V at normal output voltage. Then R5 is calculated from: R5 = ( ) N VBE + VR4 IPEAK(PRI) The effective secondary current limit sense voltage is VBE + VR4 at full output voltage and just VBE during short circuit, giving ≈ 2.7:1 foldback ratio. The diode in T1 secondary allows the secondary to “reset” between current pulses, so that true peak-to-peak diode current is controlled. C1 is used to filter out spikes and noise. VX VX LT1070 LT1070 R2 ≈2V GND D1 R2 VC GND ≈2V R1 500Ω VC Q1 2N3906 R1 20k AN19 F36 AN19 F35 Figure 35. External Current Limit Figure 36. External Current Limit VX R5 LT1070 GND VC VOUT R3 = 4mA PRI R1 FB D1 VOUT VOUT LT1070 GND R4 500Ω R2 VC FB Figure 37. Foldback Current Limit ≅1V N R6 Q1 2N3904 300Ω R5 C1 AN19 F37 R3 1 T1 R4 500Ω AN19 F38 Figure 38. Transformer Current Limit an19fc AN19-52 Application Note 19 In Figure 39 a current limit sense resistor (RS) is placed in series with the ground pin of the LT1070. Peak switch current is limited to VBE(Q1)/RS. This circuit is useful only in situations where the negative input line and the negative output line do not have to be common. Power dissipation in RS will be fairly high; P ≈ (0.6V)(IPEAK)(DC), where DC is the duty cycle of the switch. R1 and C1 filter out noise spikes and catch diode reverse turn-off current spikes. VIN VSW LT1070 + GND VC R1 1k FB R2 Q1 C1 1000pF C2 NOTE THAT THE LT1070 GND PIN IS NO LONGER COMMON TO VIN (–) RS AN19 F39 Figure 39. External Current Limit DRIVING EXTERNAL TRANSISTORS High input voltage applications using the LT1070 require an external high voltage transistor. The transistor is connected in a common gate or common base mode as shown in Figures 40 and 41. This allows the LT1070 internal current sensing to continue functioning and operates the external transistor in a mode which maximizes both operating voltage and switching speed capability. the LT1070 and to establish forward gate drive to the MOSFET. Typical gate drive requirement is 10V, with 20V as a typical maximum. The forward gate drive applied to the MOSFET is equal to the supply voltage minus the saturation voltage of the LT1070 switch (saturation voltage is typically under 1V). D1 is used to clamp the source during turn-off; it does not slow down turn-off. Diode requirements are that it withstand narrow (100ns) current spikes equal to drain current and that it turn “on” rapidly to provide proper clamping. In Figure 41, the LT1070 drives an NPN bipolar transistor. These devices require high surge base currents at turn-on and turn-off to ensure fast switching times. R1 establishes DC base drive which might be ≈1/5 of collector current. C1 provides a forward base current surge at turn-on. Typical values are in the range of 0.005μF to 0.05μF. D1 clamps the emitter voltage at turn-off. It prevents full collector current from flowing out the base lead during the turn-off delay time (0.5μs to 2μs). D2 and R1 establish the reverse base turn-off current. The voltage across R2 during turnoff delay time is approximately one diode drop. With R2 = 3Ω and a diode drop of 800mV, this would create ≈ 270mA reverse base current during turn-off. Reverse leakage in the “off” state is not a problem with this circuit because D1 and D2 force the emitter-base voltage to zero bias when the LT1070 switch is off. D1 should be selected for fast turn-on. It must handle current equal to collector current for times equal to the turn-off time of the transistor. D2 can be any medium speed diode rated for several hundred milliamps forward current spikes (1N914, etc.). In Figure 40, the LT1070 drives an N-channel power MOSFET. A separate low voltage supply is used to power C1 D2 R2 D G + 10V TO 20V D1 VIN R1 Q1 S Q1 VIN VSW VSW LT1070 LT1070 GND D1 AN19 F40 Figure 40. Driving External MOSFET GND AN19 F41 Figure 41. Driving External NPN an19fc AN19-53 Application Note 19 OUTPUT RECTIFYING DIODE the input voltage. This gives peak diode currents much higher than the average, and manufacturers current ratings must be used with caution. The output diode is often the major source of power loss in switching regulators, especially with output voltages below 10V. It is therefore very important to be able to calculate diode peak current and average power dissipation to ensure adequate diode ratings. The chart in Figure 42 lists average diode power dissipation and peak diode current for normal loads. It also lists diode current under shorted output conditions where the diode duty cycle approaches 100%, and peak and average currents are essentially the same. The most stressful condition for output diodes is overload or short-circuit conditions. The internal current limit of the LT1070 is typically 9A at low switch duty cycles. This is almost a factor of two higher than the 5A rated switch current, so that even if the regulator is used near its limit at full load, the output diode current may double under current limit conditions. If full load output current requires only a fraction of the 5A rated switch current, the ratio of diode short-circuit current to full load current may be much higher than two to one. A regulator designed to withstand continuous short conditions must either use diodes rated for the full short-circuit current shown in the fourth column, or it must incorporate some form of external current limiting. See Current Limit section for more details. The value for diode forward voltage (VF) used in the average power formulas is the voltage specified for the diode under peak current conditions listed in the next column. The peak current formulas assume no ripple current in the inductor or transformer, but average power calculations will be reasonably close even with fairly high ripple. Boost converters in particular are hard on output diodes when the output voltage is significantly higher than TOPOLOGY AVERAGE DIODE DISSIPATION PD (WATTS) Buck (IOUT)(VF)(1− VOUT / VIN) Current-Boosted Buck (IOUT)(VF)(1− VOUT / VIN) Boost (IOUT)(VF) The last column in Figure 42 shows maximum reverse diode voltage. When calculating this number, be sure to PEAK DIODE CURRENT AT FULL LOAD (AMPS) IOUT + SHORT CIRCUIT (AMPS) ΔI 2 ⎞ IOUT ⎛ VOUT − VOUT + VIN⎟ ⎜ VIN ⎝ N ⎠ ( IOUT VOUT VIN ) + ΔI ( ) (IOUT)(VF) ⎡V ⎛V ⎞ ⎤ ΔIPRI N + 1 IOUT ⎢ OUT + N ⎜ OUT − 1⎟ ⎥ + 2 ⎝ VIN ⎠ ⎥⎦ ⎢⎣ VIN Voltage-Boosted Boost (IOUT)(VF) IOUT N • VIN + VOUT Inverting (Buck Boost) (IOUT)(VF) Flyback (Continuous) (IOUT)(VF) Flyback (Discontinuous) (IOUT)(VF) ( ) ( ) IOUT(VIN + VOUT ) ΔI + VIN N + 1 VIN 2 ⎛ ⎞ V ΔI IOUT ⎜ 1 + OUT ⎟ + PRI ⎜ N VIN ⎟ 2N ⎝ ⎠ 1 N ≈8 VIN ≈8/N VOUT + N (VIN) Not Allowed VOUT Not Allowed ⎛ N ⎞ VOUT − VIN ⎜ ⎟ ⎝ N + 1⎠ Not Allowed VOUT + N (VIN) ≈8 VOUT + VIN ≈7/N VOUT + N (VIN) ≈7/N VOUT + N (VIN) 2 Current-Boosted Boost ( ) 2(IOUT )(VOUT ) f (LPRI) PEAK DIODE VOLTAGE AN19 F42 Figure 42 an19fc AN19-54 Application Note 19 use worst-case high input voltage. Transformer or tapped inductor designs may have an additional damped “ringing” waveform which adds to peak diode voltage. This can be reduced with a series R/C damper network in parallel with the diode. Long reverse recovery times can cause significant extra heating in the diode or the LT1070 switch. Total power dissipated is given by: Pt RR = (V)(f)(tRR)(IF) V = reverse diode voltage f = LT1070 switching frequency tRR = reverse recovery time IF = diode forward current just prior to turn-off With the circuit mentioned, IF is 4A, V = 20V and f = 40kHz. Note that diode “on” current is twice output current for this particular boost configuration. A diode with tRR = 300ns creates a power loss of: PtRR = (20)(40 • 103)(300 • 10– 6)(4) = 0.96W If this same diode had a forward voltage of 0.8V at 4A, its forward loss would be 2A (average current) times 0.8V equals 1.6W. Reverse recovery losses in this example are USD 735C (SCHOTTKY) CURRENT REVERSE CURRENT FLOW 0 DIODE VOLTAGE AND CURRENT Switching diodes have two important transient characteristics: reverse recovery time and forward turn-on time. Reverse recovery time occurs because the diode “stores” charge during its forward conducting cycle. This stored charge causes the diode to act like a low impedance conductive element for a short period of time after reverse drive is applied. Reverse recovery time is measured by forward biasing the diode with a specified current, then forcing a second specified current backwards through the diode. The time required for the diode to change from a reverse conducting state to its normal reverse nonconducting state, is reverse recovery time. Hard turn-off diodes switch abruptly from one state to the other following reverse recovery time. They, therefore, dissipate very little power even with moderate reverse recovery times. Soft turn-off diodes have a gradual turn-off characteristic that can cause considerable diode dissipation during the turn-off interval. Figure 43 shows typical current and voltage waveforms for several commercial diode types used in an LT1070 boost converter with VIN = 10V, VOUT = 20V, 2A. 20V 2A 20V 2A VOLTAGE MUR 415 (ULTRAFAST) CURRENT REVERSE CURRENT FLOW VOLTAGE 0 20V 2A 0 MR 856 (FAST) CURRENT REVERSE CURRENT FLOW VOLTAGE 0 40 80 120 TIME (ns) 160 200 240 AN19 F43 Figure 43. Diode Turn-Off Characteristics nearly as large as forward losses. It is important to realize, however, that reverse losses may not necessarily increase diode dissipation significantly. A hard turn-off diode will shift much of the power dissipation to the LT1070 switch, which will undergo a high current and high voltage condition during the duration of reverse recovery time. This has not shown to be harmful to the LT1070, but the power loss remains. Diode turn-on time can potentially be more harmful than reverse turn-off. It is normally assumed that the output diode clamps to the output voltage and prevents the inductor or transformer connection from rising higher than the output. A diode that turns “on” slowly can have a very high forward voltage for the duration of turn-on time. The problem is that this increased voltage appears across the LT1070 switch. A 20V turn-on spike superimposed on a 40V boost mode output pushes switch voltage an19fc AN19-55 Application Note 19 perilously close to the 65V limit. The graphs in Figure 44 show diode turn-on spikes for three common diode types, fast, ultrafast and Schottky. The height of the spike will be dependent on rate of rise of current and the final current value, but these graphs emphasize the need for fast turnon characteristics in applications which push the limits of switch voltage. Fast diodes can be useless if the stray inductance is high in the diode, output capacitor or LT1070 loop. 20-gauge hookup wire has ≈ 30nH/inch inductance. The current fall time of the LT1070 switch is ≈ 108A/sec. This generates a voltage of (108)(30 • 10– 9) = 3V per inch in stray wiring. Keep the diode, capacitor and LT1070 ground/switch lead lengths short. FORWARD SPIKE 3V 0 USD 735C (SCHOTTKY) –10 Most switching regulator designs draw current from the input supply in pulses. The peak-to-peak amplitude of these current pulses is often equal to or higher than the load current. There is significant high frequency energy in the pulses which can cause EMI problems in some systems. The addition of a simple LC filter between the supply and the switching regulator can reduce the amplitude of this EMI by more than an order of magnitude at the switching frequency and several orders of magnitude at higher harmonic frequencies. The basic filter shown in Figure 45 can be added to any switching regulator. The two major design considerations for the filter are the reverse current transfer function which determines ripple attenuation and the filter output impedance function which must satisfy regulator stability criteria. The stability problem occurs because switching regulators have a negative input impedance at low frequencies: ZIN (DC ) = − –20 FORWARD SPIKE 8V INPUT FILTERS MUR 415 (ULTRAFAST) DIODE VOLTAGE (V) 0 The output impedance of the filter has a sharp peak at the LC resonant frequency. If the output impedance is not well below the negative input impedance of the regulator at frequencies up to the bandwidth of the regulator control loop, the possibility for oscillation exists. –10 –20 FORWARD SPIKE 23V MR 856 (FAST) 0 There is a basic conflict in the two filter requirements. High ripple attenuation is obtained with a large LC product with high Q, but this also tends to aggravate oscillation problems. This conflict is minimized by using large C with smaller L to get the required LC product, but size requirements may also limit this approach. An additional “fix” is to lower the Q of the filter by paralleling L with a small –10 –20 DIODE CURRENT (A) (VIN)2 (VOUT )(IOUT ) 4 2 RF 0 LF 0 100 200 300 TIME (ns) 400 AN19 F44 VIN Figure 44. Diode Turn-On Spike SWITCHING REGULATOR 500 VOUT RS CF AN19 F45 Figure 45 an19fc AN19-56 Application Note 19 resistor (RF). This has the disadvantage of limiting the filter attenuation at high frequencies. Filter Q is also reduced by the ESR (RS) of the capacitor, but deliberately increasing ESR exacts a heavy penalty in ripple attenuation and power loss. Ripple attenuation of an input filter may be calculated from: ( )( ) ( )( ) RS DC 1 − DC R = S+ IIN(P-P) RF L f IOUT(P-P) A typical filter might consist of a 10μH inductor and a 500μF capacitor with RS = 0.05Ω. Filter attenuation is least effective at 50% duty cycle (DC = 0.5), so we will use this number now for worst-case purposes. Ripple attenuation of this filter with RF = ∞ is: ) 0.05 0.5 1 − 0.5 IOUT = 0.031 = 32:1 = ⎛ 10 • 10−6 ⎞ ⎛ 40 • 103 ⎞ IIN ⎝ ⎠⎝ ⎠ The formula assumes rectangular wave inputs with triangular outputs and yields the ratio of peak-to-peak values. Higher frequency components of the square wave current are attenuated much more than the overall attenuation figure. Output impedance of the filter given by: 1 1 J − + RF ωL JωC ( ) 1 + ωRSC ω = radian frequency = 2π(f) 2 + ( ) (C) 2π LC − RS Note that this formula does not contain the value of C. This is because large electrolytic capacitors have a total impedance at 20kHz and above which is essentially equal to ESR. For ripple attenuation, therefore, the value of C is not important; the capacitor is selected on the basis of its ESR. ZOUT = 1 f= RS = effective series resistance of C DC = switching regulator duty cycle ( )( )( This formula has a DC (ω = 0) value of zero and a high frequency value equal to RS in parallel with RF. If RS is simply the ESR of the capacitor, both high and low frequency output impedance of the filter is very low. Unfortunately, the output impedance of the filter at its resonant frequency can be significantly higher, and this resonant frequency is typically in the range where switching regulators have negative input impedance. Resonant frequency and peak output impedance formulas are shown below. ( ) RS ωC ( 2 ) 1 + ωRSC 2 2 2 If RS is simply the ESR of C, the filter resonant frequency is usually closely approximated by: f= 1 2π LC ZOUT(PEAK) = 2 ⎤ ⎡ ⎥ ⎢ RS C << 1⎥ ⎢ ⎥ ⎢ L ⎦ ⎣ ( )() ( ) 2 LC + (RS )(RF)(C) RF LC Resonant frequency for a 500μF, 10μH filter is ≈ 2kHz. Peak output impedance with RF = ∞ and RS = 0.05Ω is ≈ 0.4Ω. The criterion for regulator stability is that the filter impedance be much lower than the input impedance of the regulator: ( ) << ZIN 2 LC + (RS )(RF )(C) RF LC The worst case occurs with switching regulators that have low input voltage. If we let VIN = 5V, and VOUT = 20V, IOUT = 1A, regulator input impedance at low frequencies is (52)/(20)(1) = 1.25Ω. The peak filter impedance was calculated at 0.4Ω, so it seems that stability criterion is met. There is the problem, however, of the too good a capacitor in the filter. If the ESR of C drops to 0.02Ω, peak an19fc AN19-57 Application Note 19 filter impedance rises to 1Ω and stability becomes questionable. To bring peak filter impedance down, RF may have to be added. If RF is set at 1Ω, peak filter impedance drops to 0.5Ω. The penalty in ripple attenuation is a reduction from 32:1 to 12:1 for RS = 0.05Ω. In all this discussion, the output impedance of the actual input source was assumed to be zero. This is not the actual case obviously, and source impedance may have a significant effect on stability. The point of all this is that input filters tend to have resonant frequencies and impedances which fall into the range where they can cause stability problems in switching regulators. It is important, therefore, to include the filter design into the overall regulator design from the beginning. The selected filter must be in place when the regulator is checked for closed-loop stability and the actual source should be used. in two ways. First, there is a DC increase proportional to VC pin voltage. This is the result of increasing bias current for the switch driver to ensure adequate switch drive at high switch currents. Second, there is driver current which is “on” only when the output switch is on. The ratio of switch driver current to switch current is ≈1:40. Total average current into the LT1070 VIN pin is then: IIN ≈ 6mA + ISW(0.0015 + DC/40) ISW = switch current DC = switch duty cycle Use of this formula requires knowledge of switch duty cycle and switch current. This information is available in the sections that deal with each particular switching configuration. A typical example is a buck converter with 28V input and 5V, 4A output. Duty cycle is ≈20% and switch current is 4A. This yields a total supply current of: IIN = 6mA + 4(0.0015 + 0.2/40) = 32mA EFFICIENCY CALCULATIONS The primary reason for using switching regulators is efficiency, so it is important to be able to estimate that factor with some degree of accuracy. In may cases, the overall efficiency is not as critical as the power loss in the individual components. For reliable operation, each power dissipating component must be properly sized or heat sunk to ensure that maximum operating temperature is not exceeded. Overall efficiency is then found by dividing output power by the sum of all losses plus output power: (IOUT)(VOUT) E= ΣPL + (IOUT )(VOUT ) Sources of power loss include the LT1070 quiescent current, switch driver current and switch “on” resistance; the output diode; inductor/transformer winding and core losses; and snubber dissipation. LT1070 Operating Current The LT1070 draws only 6mA quiescent current in its idle state, but this is specified with a voltage on the VC pin such that the output switch never turns on—duty cycle equals zero. When the VC pin is servoed by the feedback loop to initiate switching, supply current at the input pin increases Total power loss due to bias and driver current is equal to input voltage times current: PBD = (IIN)(VIN) = (32mA)(28V) = 0.9W LT1070 Switch Losses Switch “on” resistance losses are proportional to the square of switch current multiplied times duty cycle: PSW = (ISW)2 (RSW)(DC) RSW = LT1070 switch “on” resistance The maximum specified value for RSW is 0.24Ω at maximum rated junction temperature, with 0.15Ω typical value at room temperature. If we use the worst-case number of 0.24Ω, this yields a switch loss in this example of: PSW = (4)2(0.24)(0.2) = 0.77W It is pure coincidence that switch and driver losses are nearly equal in this example. At low switch currents and high input voltages, PBD dominates, whereas switch losses dominate at low input voltages and high switch currents. AC switching losses in the LT1070 are minimal. Rate of switch current rise and fall is ≈108A/sec. This reduces switching times to under 50ns and makes the AC losses small compared to DC losses. An exception to this is the an19fc AN19-58 Application Note 19 ΣPL = PBD + PSW + PD + PL + PSNUB = 0.9 + 0.77 + 2.75 +1 + 0 = 5.42W AC switch loss attributable to output diode reverse recovery time. See Output Diode section. Efficiency is equal to: Output Diode Losses For low to moderate output voltages, the output diode is often the major source of power loss. For this reason, Schottky switching diodes are recommended for minimum forward voltage and reverse recovery time. Diode losses for most topologies can be approximated by the following formula, but please consult the Output Diode section for further details: E= This number is typical of a fairly high efficiency 5V buck regulator. The efficiency of 5V switching supplies is lower than higher voltage outputs because of the high diode losses. A 15V output, for instance, might have E ≈ 86%. PD ≈ (IOUT)(VF)(K) + (V)(f)(tRR)(IF) OUTPUT FILTERS VF = diode forward voltage at peak diode current V = diode reverse voltage t RR = diode reverse recovery time IF = diode forward current at turn-off K = 1 – (VOUT/VIN) for buck converters and 1 for most other topologies Output voltage ripple of switching regulators is typically in the range of tens to hundreds of millivolts if no additional output filter is used. A simple output filter can reduce this ripple by a factor of ten to one hundred at little additional cost. The high frequency “spikes” which may be superimposed on the ripple are attenuated even more. In the buck regulator example, with IOUT = 4A and letting VF = 0.7V, tRR = 100ns: PD (VOUT)(IOUT) = (5)(4) = 78.7% ΣPL + (VOUT )(IOUT ) 5.42 + (5)(4) The presence of high amplitude spikes at the output of switching regulators is often puzzling to first time designers. These spikes occur in switching regulators which, by their topology, cannot use the energy storage inductor as an output filter. These include boost, flyback and buck/ boost designs. The output of these converters can be modeled as a switched current source driving the output capacitor as shown in Figure 46. = (4)(0.7)(1 – 5/28) + (28)(40 • 103)(10–7)(4) = 2.3 + 0.45 = 2.75W Inductor and Transformer Losses See section on Inductors and Transformers. Snubber Losses The output capacitor is shown as COUT. Its model includes parasitic resistance (RS) and inductance (LS). It is the inductance which creates the output voltage spike. The amplitude of this spike can be calculated if the slew rate (dI/dT) of the switch is known. For simple inductor designs operating at full switch current, dI/dT for the See section on Flyback design. Total Losses In this example of a buck regulator, inductor losses might be ≈1W and snubber losses are zero. Total losses therefore are: OUTPUT FILTER L OUTPUT CAPACITOR LS RS LOAD VOUT FILTER CAPACITOR COUT LF RF LOAD CF AN19 F46 Figure 46. Output Filter an19fc AN19-59 Application Note 19 LT1070 switch is approximately 108A/sec. Voltage across LS is: ⎛ dI ⎞ V = LS ⎜ ⎟ = LS ⎛ 108 ⎞ ⎝ ⎠ ⎝ dT ⎠ Straight wire has an inductance of about 0.02μH per inch. If we assume one inch of wire on each end of the output capacitor, including board trace length, this represents 0.04μH. Allowing an additional 0.02μH internal inductance, LS has a total value of 0.06μH, yielding: ( ) V = 0.06 ⎛ 10− 6⎞ ⎛ 108 ⎞ = 6V ⎝ ⎠⎝ ⎠ These spikes are very narrow (<100ns) and are usually attenuated significantly in the wire runs and load bypass capacitors, but these calculations point out the importance of short lead lengths on the output capacitor. Output voltage ripple at the regulator switching frequency is usually of two types. With boost, flyback and inverting (buck/boost) designs, ripple is determined almost totally by the ESR of the output capacitor (RS). The reactance 1/(2πfC), of the capacitor at 40kHz is normally so low compared to RS that it can be ignored. The output ripple is therefore a square wave with amplitude VP-P and duty cycle DC. A formula for VP-P and DC is given in the discussions of these topologies. The second type of output ripple is triangular. It occurs in switching regulators which utilize the storage inductor as an output filter. These include buck converters, forward converters and ’Cuk converters. Again, the amplitude of the ripple is determined by RS, not C, but the waveform is triangular with amplitude VP-P and duty cycle DC. The attenuation of an output filter with rectangular inputs is: VOUT(P-P) VP- P = ( )( ) (f)(L) DC 1 − DC RF ( ) DC = duty cycle of rectangular inputs 50% = 0.5 Notice that attenuation is the same for complementary duty cycles, that is 10% and 90% are equal, and 40% and 60% are equal, 50% is the point of poorest attenuation. A converter running at 40% duty cycle with an output filter consisting of a 10μH inductor and a 200μF capacitor with RF = 0.05Ω would have a filter attenuation of: VOUT(P-P) VP- P = (0.4)(0.6)(0.05) ⎛ 4 • 103 ⎞ ⎛ 10 • 10−6 ⎞ ⎝ ⎠⎝ ⎠ = 0.03 = 33:1 The rectangular input is converted to a triangular output whose peak-to-peak amplitude is 1/33 of the peak-to-peak input. Harmonics of the switching frequency are reduced much more; the third harmonic for instance is attenuated 112:1 with LF = 0.06μH. There are no second harmonics. With buck, forward and ’Cuk converters, the ripple voltage into the filter is already triangular. The output ripple of the filter is of the form V(t) = mt2. Attenuation ratio is given by: VOUT(P-P) VP- P = RF (8)(L)(f) For the same conditions of RF = 0.05Ω, L = 10μH: VOUT(P-P) VP- P = 0.05 = 0.0156 = 64:1 8 ⎛ 10 • 10−6 ⎞ ⎛ 40 • 103 ⎞ ⎝ ⎠⎝ ⎠ () The ripple voltage of these converters is already lower because of the main inductor filtering, so the output filter inductor can often be only a few μH to obtain adequate filtering. The inductor can even be an air core type. A 1/2" diameter, 3/4" long air-wound coil with 13 turns of #16 wire will have an inductance of 1μH, giving a 6:1 attenuation with RF = 0.05Ω. INPUT AND OUTPUT CAPACITORS Large electrolytic capacitors used on switching regulators have several important design considerations. The most important is usually effective series resistance (ESR). This is simply the equivalent parasitic resistance in series with the capacitor leads. At frequencies of 10kHz and above, the total impedance of the capacitor is almost identically equal to ESR, and this parasitic resistance limits the filtering effectiveness of the capacitor. The design equations for capacitors used with the LT1070 most often deal an19fc AN19-60 Application Note 19 simply with ESR; the actual capacitance value is of secondary importance. The following formulas are a very rough guide to maximum ESR vs capacitance for several types of commercially available switching supply capacitors. ESR changes over temperature are shown in Figure 47. RESISTANCE (RELATIVE) 10 SPRAGUE TYPE 673D 1 0.1 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 150 AN19 F47 Nothing’s free, folks. Common design practice is to parallel several capacitors to achieve low ESR and acceptable component height. A second consideration in capacitor selection is ripple current rating. After a capacitor has been selected, its ripple current rating should be checked to verify that operating ripple is less than the maximum allowed by the manufacturer. Keep in mind, however, that ripple current ratings are normally selected to limit temperature rise in the capacitor. Power dissipation is given by (IRMS)2(ESR). For ambient temperatures below the capacitor’s maximum rating, it may be possible to increase ripple current. Consult the capacitor manufacturer. RMS ripple current in the output capacitor for boost, buck-boost and flyback designs can be calculated from output current and switch duty cycle: IRMS = IOUT Figure 47. Typical Capacitor ESR vs Temperature Sprague types 673D or 674D (400)⎛⎝10−6⎞⎠ ESR = Ω 0.6 (C)(V) Mallory type VPR (200)⎛⎝10−6⎞⎠ ESR = Ω 0.6 (C)(V) Cornell Dubilier Type UFT (430)⎛⎝10−6⎞⎠ ESR = Ω 0.25 (C)(V) C = capacitance value V = rated working voltage Note that higher voltage ratings yield lower ESR. This is because higher voltage capacitors are physically larger! DC 1 − DC For buck converters, RMS current in the output capacitor is approximately equal to 0.3ΔI, where ΔI is the peak-topeak ripple current in the inductor (continuous mode). Ripple current in the input capacitor for flyback and buckboost designs is: IRMS = (IOUT )(VOUT ) VIN 1 − DC DC For buck designs it is: ( ) IRMS = IOUT DC − DC 2 and for boost designs, input capacitor ripple current is: IRMS = 0.3ΔI INDUCTOR AND TRANSFORMER BASICS The inductors and transformers used with the LT1070 are very important to the overall performance of the converter, especially with respect to parameters such as efficiency, maximum output power and overall physical size. The many trade-offs associated with the inductance values and the volume of the core require the designer to have a sound basis for selecting the optimum inductor or transan19fc AN19-61 Application Note 19 former for each application. Specific guidelines for inductance values are given in the discussion of suggested applications elsewhere in this section, but a general understanding of inductor theory is also needed. A A The three important characteristics of a simple 2-terminal inductor used in switching regulators are: inductance value (L, in henries), maximum energy storage (I2 • L/2, in ergs) and power loss (watts). Basic definitions of the parameters which determine these characteristics are shown below. g μ = core permeability. This is basically the increase in inductance which is obtained when the inductor is wound on a core instead of just air. A μ of 2000, for instance, will increase inductance by 2000:1. = magnetic path length. In a simple toroid this is the average circumference of the core (see sketch). A = cross-sectional area of the core (see sketch). g = thickness of air gap (if any) used to increase the energy storage capability of a core (see sketch). B = magnetic flux density in the core. If B rises too high, the core will “saturate,” allowing μ and therefore L, to drop drastically. g Toroid B= AN19 F47a E-E Core ()(I N)(μ) (0.4π) (no gap) A properly selected inductor must provide the right value of L without exceeding the maximum limit on flux density, (BM). In other words, the core must not “saturate” under conditions of peak winding current (IP). By combining the formulas for inductance and flux density, it can be shown that core volume (VC) required is a direct function of the energy to be stored by the inductor: N = number of turns in the winding. I = instantaneous winding current. VC = volume of actual core material. In most converter applications, the required inductance is determined by constraints such as maximum output power, ripple requirements, input voltage and transient response. I is determined by load current. For purposes of this discussion, therefore, it is assumed that L and I are known quantities, and the quantities to be determined are N, A, , VC and g. Inductance is determined by core permeability, path length, cross sectional area and number of turns: L= (μ)(A)⎛⎝N2⎞⎠ (0.4π)⎛⎝10− 8⎞⎠ (no gap) Magnetic flux density is a function of winding current, number of turns and path length: () ⎛ 2⎞ ⎜IP ⎟ L ⎝ ⎠ Stored energy = E = 2 ⎛ 2⎞ ⎜IP ⎟ L μ 0.4π 2μ 0.4π ⎝ ⎠ = E VC = A = ⎛ B2⎞ ⎛ 10− 8⎞ ⎛B2⎞ ⎛ 10− 8⎞ ⎝ ⎠⎝ ⎠ ⎝ ⎠⎝ ⎠ ( )( ) ( )( )( ) ( ) ( )( ) In any given application, the value of IP can be determined from maximum load current and duty cycle. Formulas for maximum IP are provided in the individual sections on each topology. In many cases, the maximum load current is much less than the LT1070 is capable of providing. A core designed to handle only full load current may saturate under overload or short-circuit conditions. The cycle-by-cycle current limiting of the LT1070 protects the regulator against damage even with saturated cores. This considerably an19fc AN19-62 Application Note 19 improves the reliability of converters using the LT1070 and eases the design complexity. Although core volume is the main criterion for selecting a given core, the volume still consists of two variables, A and . For minimum overall size of the inductor it is generally best to increase A as much as possible at the expense of , thereby minimizing the number of turns required to obtain the desired inductance. This process can be taken only so far before the “window” in the core becomes too small to accommodate the windings. Cores with Gaps The energy storage capability of a core can be increased by “gapping” the core. A significant portion of the total energy is stored in the air gap. The drawback of a gapped core is that the effective permeability drops, requiring many more turns to achieve the required inductance. More turns require a larger winding window. The overall size of the inductor, however, can be considerably less with a properly gapped core, especially with high permeability core material. The formula for inductance with a gapped core is: L= (μ)(A)⎛⎝N2⎞⎠ (0.4π)⎛⎝10− 8⎞⎠ ⎛ μg ⎞ ⎜ 1+ ⎟ ⎠ ⎝ ⎛ μ • g⎞ Inductance drops by the factor, ⎜1+ ⎟ ⎠ ⎝ With a μ of 2000, = 2" and g = 0.02", inductance will drop by 22:1, requiring that N be increased by √22 to maintain constant inductance. Increase in energy storage is equal to the decrease in permeability. E MAX (with gap) μ•g = 1+ E MAX (no gap) There are several practical limits on the amount which gap size may be increased. First, large gaps require many more turns to achieve the same inductance. This requires smaller diameter wire which increases copper losses from I2R heating. Secondly, with large gaps the effective gap size is considerably less than the actual gap because of fringing fields around the gap. When using commercially available cores, data sheet information on , A and μ is usually given in effective values. The theoretical value of μ, for instance, is the bulk value for the core material. The effective value for a single piece core may approach the bulk value, but with 2-piece cores, the tiny air spaces left in the mating surfaces can reduce the effective permeability by as much as 2:1. This may sound unreasonably pessimistic, but a core with bulk μ = 3000 and = 1.5", will lose half its permeability for g = 0.0005". Data sheets for gapped cores list effective values of μ for each gap size to make calculations simple. They may also list a parameter, “inductance per (turn)2” for each gap to further simplify inductance calculations. There are two types of core material which are effectively self-gapped: iron powder and permalloy. These materials distribute the gap evenly throughout the core, allowing gapless core to be constructed with much higher energy storage capability. The permeability of this material is much reduced, but if the winding window will accommodate the extra turns, the current handling capability of the inductor will be much higher for the same inductance compared to a high-μ formulation. Iron powder cores are cheaper than ferrite and can be custom tailored quickly, but high core loss limits their application to low AC flux density applications such as inductors. A significant advantage of iron powder is that it saturates very “softly,” preventing catastrophic total loss of inductance for large overcurrent conditions. Note that commercially available powdered iron inductors are typically “optimized” so that core losses and winding (I2R) losses are the same order of magnitude. Core loss is dependent on peak-to-peak ripple current which depends on the voltage-time product applied to the inductor. The inductors are therefore specified for a maximum DC current and a maximum volt•microsecond product to limit heating. For applications which require highest possible efficiency, consider using oversized cores or permalloy, which is more expensive, but has much lower core loss. Consult with inductor manufacturers about trading off DC current for ripple current, or vice versa. Inductor Selection Process The simplest way to select an inductor is to find an off-theshelf unit that meets the minimum inductance and current an19fc AN19-63 Application Note 19 requirements. This may not be cost effective, however, if the standard types are not fairly close to your requirements. The next best approach is to have the unit custom wound by one of the many companies in the business. They will select the best core and winding combination for your particular application. A third approach is to scan the literature for standard core types which you can custom wind to meet your particular requirement. This is a quick way to get a prototype up and running. It can also be very cost effective for some production situations. At the end of this application note is a list of core and inductor/transformer manufacturers. The procedure for selecting a do-it-yourself core starts with defining the values of peak winding current and inductance. If the LT1070 is to be used at or near full output power, peak winding current will approach 5A, so a conservative value of 5A should be used for core calculations. If external current limiting is used or if output power levels are lower, peak winding currents can be calculated from the equations supplied in the discussions of each topology. Likewise, inductance values are calculated from specific equations in these sections. Actual values for L generally fall into the range of 50μH to 1000μH, with 200μH to 500μH being most typical. For ferrite cores, the next step is to calculate the core volume required to prevent saturation: Ve = 2 L μe 0.4π (ferrite cores) Powdered iron cores, because of their high core loss and ability to operate at very high DC flux densities, generally have a different design procedure based on temperature rise due to core loss and winding loss. AC flux densities generally need to be kept below 400 gauss. This leads to a volume formula based on AC flux density: (ΔI) (L)(μ)(0.4π) VC = 2 (4)(BAC) ⎛⎝10−8⎞⎠ 2 For ΔI = 1A, L = 200μH, μ = 75 and BAC = 300 gauss, (1) ⎛⎝ 200 • 10− 6⎞⎠ (75)(0.4π) VC = = 5.25cm3 2 ⎛ − 8⎞ (4)(300) ⎝10 ⎠ 2 L = required inductance (henries) IP = peak inductor current (amps) μe = effective relative permeability supplied on core BO = maximum operating flux density data sheets (gauss) Ve = effective core volume } Example: let L = 200μH, IP = 5A, μe = 100, BO = 2500 gauss, (5) ⎛⎝ 200 • 10−6⎞⎠ (100)(0.4π) Ve = = 10cm3 2 ⎛ − 8⎞ (2500) ⎝10 ⎠ 2 Others are left ungapped with the user supplying spacers for setting gap length. Custom gapped cores are also available. A reasonable place to start is with a gap length of 0.02 inches. A core with μ = 3000 and path length (e) of 2 inches would have an effective permeability of μe = μ/(1 + μg/e) = 3000/(1 + 3000 • 0.02/2) = 97. Notice that by simply selecting a large gap we can arbitrarily reduce the required core volume. The problem with attempting to use a large gap is that the effective permeability drops so low that a large number of turns are required to achieve the desired inductance. This forces the use of small diameter wire where the copper losses get high enough to cause overheating of the core. ΔI = peak-to-peak ripple current ( ) ( )( )( ) 2 (BO) ⎛⎝10−8⎞⎠ IP The values chosen for μe and BO are typical for a gapped ferrite core. Some cores come with several standard gaps. To reduce core size, inductance (L) must be increased. This seems backwards according to the formula, but ΔI is inversely proportional to L, so the (ΔI)2 term drops rapidly as L is increased, reducing required core volume. The penalty is increased wire (copper) loss due to the increased turns required. After a tentative core is selected based on volume, a check must be done to see if the power losses from the winding(s) and the core itself are within the allowed limits. an19fc AN19-64 Application Note 19 The first step is to calculate the number of turns required: N= (L)(e ) (μe )(Ae )⎛⎝ 0.4π • 10−8⎞⎠ } N = turns supplied e = effective magnetic path length (cm) on core Ae = effective core area (cm2) data sheets μe = effective permeability (with gap) Using the ferrite example, and assigning e = 9cm, Ae = 1.2cm2, μe = 100, a 200μH inductor would require: N= () ⎛ 200 • 10− 6⎞ 9 ⎝ ⎠ = 34.6 turns (use 35) − 8⎞ ⎛ 100 1.2 0.4π • 10 ⎝ ⎠ ( )( ) To calculate wire size, the usable winding window area (Aw) must be ascertained from the core dimensions. Many data sheets list this parameter directly. The usable window area must allow for bobbin thickness and clearances. Total copper area is only about 60% of window area due to air gaps around the wire. We can now express the required wire gauge in terms of N and Aw. ( )( ) ( )( ) ⎛ 0.08 N ⎞ Wire gauge (AWG) = 10 ⎜ log ⎟ ⎜ 0.6 Aw ⎟⎠ ⎝ ⎡ ⎤ ⎛ − AWG ⎞ N ⎢ 0.32 ⎜ 10 20 ⎟ + 0.01⎥ N D + 0.01 ⎝ ⎠ ⎦ Layers = = ⎣ LB LB ( D = wire diameter in inches LB = bobbin length or toroid inside circumference 0.01 = allowance for enamel and spacing For N = 35, AWG = #14 and LB = 0.9": ⎡ ⎤ ⎛ −14 ⎞ 35 ⎢ 0.32 ⎜ 10 20 ⎟ + 0.01⎥ ⎝ ⎠ ⎦ = 2.87 Layers = ⎣ 0.9 ( ) The reason for calculating layers is that the AC copper losses are very dependent on the number of layers in a winding. To calculate AC losses, a table is used (Figure 48) which requires a factor K: ( )( ) K = D f FP D = wire diameter or foil thickness For foil conductors, FP is 1. For round wires it is equal to: FP = (TL + 1)(NC)(D) LW TL = turns per layer NC = number of paralleled conductors (bifilar→NC = 2) D = wire diameter LW = length of winding (≈ LB) 0.08 factor = area of #1 gauge wire 0.6 factor = air space loss around wire (0.08)(35 ) = 13.68 (use # 14) AWG = 10 log (0.6)(0.2 ) The next step is to determine the number of winding layers. This is determined by bobbin length, or toroid inside circumference: 20 LAYERS = 4 FAC—AC RESISTANCE FACTOR If we assume a value for Aw of 0.2in2 and use N = 35: ( ) ) 3 10 8 2 6 4 1 2 1 0 1 2 3 4 5 6 K 7 8 9 10 11 12 AN19 F48 Figure 48. AC Resistance Factor an19fc AN19-65 Application Note 19 For 35 turns and 3 layers, TL ≈ 12. #14 wire has D = 0.064. NC for a single wire is 1. With LW = 0.9": FP = (12 + 1)(1)(0.064) = 0.92 cases, multiple strands of smaller wire or copper foil must be used to reduce the AC resistance factor to acceptable limits. After winding losses are found, core loss must be calculated. The first step is to find peak AC flux density: 0.9 K is now equal to: ( )( ) ( ) K = D f FP = 0.064 ⎛ 40 • 103 ⎞ 0.92 = 12.3 ⎝ ⎠ This is a very high K factor; in fact it is slightly off the graph in Figure 48, but for now it illustrates the importance of AC resistance calculations. The various lines on the graph represent the number of layers. With three layers, the AC resistance factor is off scale at approximately 23. This means that AC resistance is 23 times DC resistance. Now we can calculate winding losses. DC winding resistance is found from: (N)(m) ⎛⎜10 RDC = 12 ⎝ AWG −4 10 ⎞ ⎟ ⎠ m = mean turn length (core specification) For N = 35, m = 2.4", AWG = #14: (35)(2.4) ⎛⎜10 RDC = 12 ⎝ AWG −4 10 ⎞ ⎟ = 0.0176Ω ⎠ AC resistance is then DC resistance multiplied by AC resistance factor (FAC). ( ) (2N)(Ae )⎛⎝10−8⎞⎠ L ΔI BAC = ΔI = peak-to-peak winding ripple current ΔI is the ripple current in the winding. It is the change in winding current during the time current is flowing in the winding. For L = 200μH, ΔI = 2A, N = 35 and Ae = 1.2cm2: ( )( ) Core loss per unit volume (Ffe) is found from the manufacturers tables (see Figure 49) of Ffe vs flux density and frequency or from the following formula for typical MNZN ferrite material (ferroxcube type 3C8): Ffe = (1.3 – 10 –14)(BAC)2(f1.45) For BAC = 476 gauss, f = 40kHz: Ffe = (1.3 • 10 –14)(476)2(40 • 103)1.45 = 0.014W/cm3 1000 RAC = (RDC)(FAC) = (0.0176)(23) = 0.404Ω MICROMETALS #26 (μ = 75) POWDERED IRON PW = (IDC DC) + (IAC )2(R AC) Formulas for IDC and IAC are shown in Figure 50. If we assume IDC = 5A and IAC = 1A, total winding losses are: LOSS (mW/cm3) To calculate total losses, DC and AC losses are summed: )2(R 100 MAGNETICS HF (μ = 125) MOLYPERMALLOY 10 FERROXCUBE 3C8 (μ = 2600) FERRITE PW = (5)2(0.0176) + (1)2(0.404) = 0.44 + 0.4 = 0.94W In this example, AC losses are about equal to DC losses. Simple inductors used in buck, boost and buck/boost designs may have the ratio of AC to DC losses in the range of 0.25 to 4.0. Transformer designs like flyback usually have AC losses much higher than DC losses. Losses in the primary and secondary are calculated separately. In many () ⎛ 200 • 10−6 ⎞ 2 ⎝ ⎠ = 476 gauss BAC = 35 1.2 ⎛ 10− 8⎞ ⎝ ⎠ 1 10 100 1k FLUX DENSITY (GAUSS) (PEAK) 10k AN19 F49 Figure 49. Core Loss vs Flux Density an19fc AN19-66 Application Note 19 Total core loss is Ffe times core volume: PC = (Ffe)(Ve) = (0.014)(10) = 0.14W Ve = effective core volume (cm3) Core loss for a powdered iron core is approximately 25 times higher than for ferrite. At a lower flux density of 150 gauss, a powdered iron core would still have core losses 2.5 times that of ferrite. Copper losses would also be higher because of the higher inductance required to reduce AC flux density. Powdered iron cores must be carefully designed to avoid overheating. Overall losses in the ferrite core are the sum of winding losses plus core losses: 2. Calculate required gap: ⎛μ ⎞ e ⎜ − 1⎟ ⎝ μe ⎠ g= μ ⎛ 2000 ⎞ − 1⎟ 8.26⎜ ⎝ 150 ⎠ = = 0.051cm = 0.02″ 2000 If an ungapped core is used with spacers, spacer thickness should be 0.02/2 = 0.01". 3. Calculate required turns: P = PW + PC = 0.94 + 0.14 = 1.08W This loss reflects on regulator efficiency, and more importantly, core temperature rise. A 10cm3 core might have a typical thermal resistance of 20°C/W. Temperature rise in this core with P = 1.08W = (1.08)(20) = 21.6°C. 40°C rise is considered a typical design criterion, so this core is being under utilized. Transformer Design Example Requirements: A flyback converter with VIN = 28VDC, VOUT = 5V, IOUT = 6A. From previous calculations it is found that N = 1/3, LPRI = 200μH and IPRI(PEAK) = 4.5A, with ΔI = 1A. 1. Calculate volume of core required with a gapped core. First assume an effective permeability of ≅150 and BO = 2500 gauss: (IPRI) (L)(μe )(0.4π) Ve = 2 (BO) ⎛⎝10−8⎞⎠ 2 (4.5) ⎛⎝ 200 • 10−6⎞⎠ (150)(0.4π) = 12cm3 = 2⎛ − 8⎞ (2500) ⎝10 ⎠ 2 A Pulse Engineering core #0128.005 has Ve = 13.3cm3, Ae = 1.61cm2, e = 8.26cm, μ = 2000. N= = (L)(e ) (μe )(Ae )⎛⎝ 0.4π • 10−8⎞⎠ ⎛ 200 • 10− 6⎞ 8.26 ) ⎝ ⎠( = 23.3 ⎛ 0.4π • 10−8 ⎞ . 150 1 61 ( )( )⎝ ⎠ 4. Calculate wire size. Allocate 1/2 the window space for the primary winding. Window height (build) for the 0128.005 core is 0.25" and coil length is 0.782", giving a window area = (0.25)(0.782) = 0.196in2: AWG = 10 log 0.08N (0.6)(Aw) = 10 log (0.08)(23) ⎛ ⎞ (0.6)⎜⎝ 0.196 2 ⎟⎠ = 14.95 (use # 16) 5. Calculate layers: ⎡ ⎤ ⎛ −AWG ⎞ N ⎢ 0.32 ⎜ 10 20 ⎟ + 0.01⎥ ⎝ ⎠ ⎦ Layers = ⎣ LB ⎡ ⎤ ⎛ −16 ⎞ 23 ⎢ 0.32 ⎜ 10 20 ⎟ + 0.01⎥ ⎝ ⎠ ⎦ = ⎣ 0.782 = 1.79 (assume 2 layers) ( ) ( ) an19fc AN19-67 Application Note 19 6. Calculate K factor (#16 wire has D = 0.05): ⎛ 23 ⎞ + 1⎟ 1 0.05 TL + 1 NC D ⎜⎝ 2 ⎠ FP = = = 0.8 LW 0.782 ( ( )( ) )( )( ) ( )( ) ( ) K = D f FP = 0.05 ⎛ 40 • 103 ⎞ 0.8 = 8.94 ⎝ ⎠ 7. Calculate DC winding resistance: ( )( ) N m ⎛ AWG − 4 ⎞ RDC = ⎜ 10 10 ⎟ = ⎠ 12 ⎝ (23)(3)⎛⎜⎝10 16 − 4 10 12 ⎞ ⎟ ⎠ Power loss in the primary winding is: PW = (IAC)2 RAC + (IDC)2 RDC = (1.95)2 (0.19) + (2.4)2 (0.023) = 0.85W 11. Calculate secondary winding loss. Turns ratio is 1/3, so the secondary will have 23/3 = 7.67 turns. Use 8 turns: AWG = 10 log = 0.023Ω (m for this core is ≈ 3") 8. Use graph to find AC resistance factor. Interleaving of primary and secondary reduces effective layers by two only if primary and secondary conduct simultaneously, which they do not in a flyback design. Use layers = 2 line: FAC = 8.3 (from graph, for K = 8.95) RAC = (RDC)(FAC) = (0.023)(8.3) = 0.19Ω 10. Calculate primary winding losses. First, primary AC RMS current must be calculated. From the chart in Figure 50: = 6 0.75 I IDC = OUT E = 6 0.75 (N)(VOUT ) L 0.782 D= B = = 0.049″ 2N 2 8 ( )( ) The next smallest standard wire diameter is #18. Two #18 wires have three times the DC resistance of a single #10 wire, but AC resistance will not increase nearly that much. Assume one layer bifilar wound #18 secondary interleaved between the two primary layers (to reduce leakage inductance). RDC = VIN ) VOUT VOUT + N • VIN 2 ( 5 5 + 1/ 3 • 28 ( 28) 2 12 ⎝ AWG −4 10 ( )( ) 8 3 ⎛ 18 − 4 ⎞ ⎞ 10 ⎟= ⎜ 10 ⎟ ⎠ ⎠ 12 ⎝ With two wires, total RDC = 0.013/2 = 0.0065Ω. 28 (VIN) (N)(m) ⎛⎜10 = 0.013Ω per wire (1/ 3)(5) = 1.95A ( (0.08)(8) = 10.4 ⎛ ⎞ (0.6)⎜⎝ 0.196 2 ⎟⎠ This is rather large, stiff wire and the large diameter will lead to large AC winding losses. A good solution might be to use multiple smaller diameter wire wound in parallel. If we use the length of the coil divided by 2N, it will tell us what diameter wire can be bifilar wound to just fill one layer: 9. Calculate AC winding resistance: I IAC = OUT E 0.08N = 10 log 0.6Aw ) = 2.4A FP = (TL + 1)(NC)(D) = (8 + 1)(2)(0.04) = 0.92 LW ( )( ) 0.782 ( ) K = D f FP = 0.04 ⎛ 40 • 103 ⎞ 0.92 = 7.7 ⎝ ⎠ From graph, with layers = 1, FAC = 2.3: RAC = (RDC)(FAC) = (0.0065)(2.3) = 0.015Ω an19fc AN19-68 Application Note 19 ⎛ 200 • 10− 6⎞ 1 ( ) ⎝ ⎠( ) BAC = = 2 (N)(Ae )⎛ 10−8 ⎞ 2 (23)(1.61)⎛ 10−8 ⎞ ⎝ ⎠ ⎝ ⎠ From the chart in Figure 50: L ΔI IAC = IOUT 5 VOUT =6 = 4.4 A 1 / 3 ( 28) N (VIN) IDC = IOUT 5 + 1 / 3(28) VOUT + N( VIN) =6 = 7 .4A 1 / 3 ( 28) N (VIN) = 270 gauss ( ) PC = (Ffe )(Ve ) = (0.0045)(13.3) = 0.06W 2 Ffe = ⎛ 1.3 • 10−14 ⎞ BAC ⎛ f1.45 ⎞ = 0.0045W / cm3 ⎝ ⎠ ⎝ ⎠ PW = (4.4)2(0.015)+(7.4)2(0.0065) = 0.65W Total power loss with this core is: 12. Calculate core loss. P = PW + PC = 0.85 + 0.65 + 0.06 = 1.56W Core loss is proportional to AC flux density which is determined by change in primary current (ΔI) during primary current flow period. For ΔI = 1A: The 0128.005 core is specified at 2.78W for a 40°C temperature rise, yielding θ = 40/2.78 = 14.4°C/W ΔT(core) = (P)(θ) = (1.56)(14.4) = 22°C TOPOLOGY [ Flyback ( VIN) IOUT [ ( 2 (VIN) VOUT VOUT + N VIN − VOUT )] IOUT (VIN) ⎛ V ⎞ IOUT ⎜1+ OUT ⎟ VIN ⎠ ⎝ IOUT ’CUK IOUT = DC output current ( N VOUT )] 2 IOUT ( ) ( ) VOUT + N VIN IOUT (VIN − VOUT )[VOUT + N (VIN − VOUT )] 2 N(VIN) ( ) IOUT VIN N + 1 ) N VOUT − VIN IOUT VIN IOUT VIN ⎛V ⎞ IOUT ⎜ OUT ⎟ ⎝ VIN ⎠ [( (VIN) )] 2 “O” or (0.29ΔI) VOUT = DC output voltage IOUT ( ) VIN (N + 1) VOUT + VIN(N + 1) N(VIN) IOUT VOUT ( ) N VIN IOUT VIN = DC input voltage ( ) ( ) 2 N(VIN) VOUT VIN − VOUT NA IOUT IOUT NA VOUT N VIN − VOUT VOUT N VIN NA VOUT + N VIN (0.29)(ΔI) ) IOUT N VIN NA VOUT − VIN ( AC SECONDARY I NA [ ( (IOUT)(N) ( VOUT − VIN)[VOUT + VIN(N + 1)] 2 (VIN) Forward IOUT (0.29)(ΔI) ⎛V ⎞ IOUT ⎜ OUT ⎟ ⎝ VIN ⎠ IOUT ) N VOUT VIN − VOUT ⎛V ⎞ IOUT ⎜ OUT ⎟ ⎝ VIN ⎠ VoltageBoosted Boost DC SECONDARY I (0.29)(ΔI) IOUT Boost Buck-Boost (Inverting) ( IOUT N VOUT E VIN 2 Buck CurrentBoosted Boost ( )] VOUT VOUT + N VIN IOUT E CurrentBoosted Buck AC PRIMARY I DC PRIMARY I VOUT − VIN ( ) VIN N + 1 VOUT − VIN ( ) N VIN NA IOUT [( )] VOUT N VIN − VOUT ( ) N VIN 2 “O” or (0.29ΔI) AN19 F50 Figure 50. AC and DC Winding Currents (RMS Equivalent) an19fc AN19-69 Application Note 19 This is a very conservative design. If minimum core size is required, the procedure now is to go back to step 1 and assume a lower effective permeability (μe), perhaps 100. This would reduce core volume and require a larger gap. More turns would be required and the available space for copper would go down, so copper losses would go up. Flux density remains constant, so core loss drops. Thermal resistance goes up however, so the smaller core gets hotter. In addition, the increased number of turns will increase leakage inductance, which will increase snubber losses. It isn’t easy, folks! HEAT SINKING INFORMATION The efficiency of the LT1070 allows it to be used without a heat sink in many applications, but for full-power output a heat sink is required. The equations contained in the Efficiency section of this application note will allow the user to estimate fairly accurately the total power dissipation of the chip under full load conditions. Short-circuit power dissipation can be either more or less than full load, depending on the topology. Calculation of short-circuit power dissipation in the LT1070 is very complicated because the “on” time of the switch is strongly dependent on parasitic effects such as diode and inductor series resistance, wiring losses and leakage inductance. If continuous output shorts must be tolerated, it is strongly suggested that a temperature probe be used to ensure that maximum junction is not exceeded. Thermal resistance from junction to case is 2°C/W maximum, and shortcircuit power dissipation almost never exceeds 10W, so a case temperature of 100°C for commercial units and 130°C for military units will ensure that maximum junction temperature is not exceeded. Heat sink size for the LT1070 can be calculated if maximum power dissipation and maximum ambient temperature are known. ( )( ) TJ − TA − P θJC θHS = P θHS = heat sink thermal resistance P = LT1070 power dissipation θJC = LT1070 junction-to-case thermal resistance (2°C/W) TJ = LT1070 maximum junction temperature TA = maximum ambient temperature For TJ = 100°C, TA = 60°C, P = 5W: θHS = ( )( ) = 6°C / W 100 − 60 − 5 2 5 TROUBLESHOOTING HINTS The following is a list of “gotchas” we’ve put together to help you avoid some of the pitfalls of switching power supply design. They range from obvious to subtle and serious to hilarious. The LT1070 was specifically designed to eliminate many of the problems commonly found in power supply design and be easy to use. The problem is that there are a significant number of easily overlooked mistakes in breadboarding switching regulators which result in either instant death of the IC or electrical characteristics which are puzzling to even highly experienced power supply designers. So here’s the list we’ve collected so far. We hope your problem is on it to save you time and frustration. If not, give us a call and we’ll help fix the problem. WARNING Before reading this section, be aware that the intent of the author is not to insult, but rather to relate in an attentiongetting manner a list of goofs that, in many cases, he personally has had to own up to. 1. Transformer Wired Backwards Those dots indicate polarity, not smashed flies. 2. Electrolytic Capacitors Installed Backwards This is no problem until you bend over to see what is wrong—then “bang,” a personal demonstration of explosive venting. 3. LT1070 Input and Switch Pins Reversed The catalog and some preliminary data sheets got out with the wrong pinout for the plastic TO-220 package. Our apologies. Pin 5 is input on TO-220 packages. 4. No Input Bypass Capacitor Switching regulators draw current from the input supply in pulses. Long input wires can cause dips in an19fc AN19-70 Application Note 19 the input voltage at the switching frequency. Breadboards should have a large (≥100μF) input capacitor up close to the regulator. 5. Fred’s Inductor (Or Transformer) Inductors are not like lawn mowers. If you want to borrow the one out of Fred’s drawer, make sure it’s the right value for your application. A 50μH inductor with 50V applied will have a current increasing with time at the rate of 1A per microsecond. It doesn’t take a calculator to see that things can get out of hand quickly during the 25μs period of a 40kHz switcher. Likewise, if “Fred’s inductor” is 50 millihenries, it will probably saturate at such low current levels that it is useless, not to mention the fact that the transient response can be measured on a Simpson VOM. Use the formulas in the application note to get a ball park inductance value before starting a breadboard. 6. Wimpy Magnetic Cores Core sizes for the LT1070 will vary from 3cm3 to 20cm3 of core material for properly designed inductors or transformers. A thumbnail size core will simply saturate and get hot when asked to operate at ampere current levels. Breadboard with man-sized cores, then optimize the core size for production. 7. Rat’s Nest Wiring The LT1070 is not a jelly bean op amp that can be wired up with 2-foot clip leads. It achieves its high efficiency by switching current at very high speeds. Long wires will cause every component connected to them to look like an inductor at these speeds. This not only causes totally unpredictable operation; it can generate fatal (to components) transient voltages. Use very short wires to interconnect power components on the breadboard, including bypass capacitors, catch diodes, LT1070 pins, transformer leads, etc. 8. No Snubber Network The LT1070 will tolerate a lot of abuse, but it cannot be overvoltaged on the switch pin and survive to tell the tale. The 65V maximum switch voltage must be observed. Any design using a transformer or tapped inductor will have enough leakage inductance to cause transients well above 65V if no snubber network is used. Load currents and input voltages should be increased slowly while monitoring switch voltage to ensure that the initial snubber design is adequate. 9. 60Hz Diodes The LT1070 will eat 1N914 and 1N4001 diodes and not even burp. Diode currents, especially during startup, can exceed 5A. This takes care of the 1N914s. The 1N4001s will last for a little while, until the heat generated by their horribly slow turn-off characteristics causes them to self-destruct. Use diodes designed for switching applications, with adequate current ratings. Turn-on time is also important to avoid overvoltage stress on other components (see Diode section). 10. Something from Nothing The first step in designing with the LT1070 is to see if it will provide the required power level. Each topology has a different maximum output power that it can provide, depending on things such as input voltage, output voltage and transformer turns ratio. Secondary effects such as inductance values and switch resistance may also limit power. The power graph on the next page is a rough guide to maximum power levels. Use it as a quick guide only. More exact formulas are contained in the application section. Oh, by the way, if you thought about paralleling LT1070s for more power—sorry, it won’t work. You cannot get to the internal 40kHz oscillator to get them in sync. 11. Input Supply Gets Clobbered The LT1070 can draw input currents of up to 6A during start-up. It has to charge up the large output capacitor and it does this at a rate set by the internal current limit unless optional soft start is added. The start-up surge may trip overcurrent latches on some supplies, causing them to stay off until power is recycled. Steady-state problems can also occur. Switching regulators try to deliver constant load voltage. With a given load, this means constant load power. For a high efficiency system, input power also remains constant, so input current increases as input voltage decreases. Low input voltage conditions may require such high input currents that the input supply current limits. This an19fc AN19-71 Application Note 19 causes the supply voltage to drop further, forcing a permanent latch condition. See current limit and soft start sections. 12. Didn’t Read the Data Sheet Then you shall have no pie. 13. Stray Coupling to the VC or FB Pins Voltages on the FB and VC pins are referenced to the LT1070 ground pin. In some topologies the ground pin is switching between input voltage and system ground. Stray capacitance between VC or FB pins and system ground will act like coupling to a switching source. Minimize this capacitance. The problem is particularly acute when using an RC box to iterate frequency compensation on the VC pin. Even configurations which have the LT1070 ground pin “grounded” may have problems if the RC box picks up switching energy. SUBHARMONIC OSCILLATIONS Current mode switching regulators which operate with a duty cycle greater than 50% and have continuous inductor current can exhibit a duty cycle instability known as subharmonic oscillations. This effect is not harmful to the regulator and in many cases it does not even affect the output regulation. Its most annoying effect is to produce a high pitched squeal from power components which effectively have their 40kHz operating frequency modulated by submultiple frequencies; 20kHz, 10kHz, etc. Subharmonic oscillations do not depend on the closedloop characteristics of the regulator. They can occur even when zero feedback is used. Ordinary closed-loop instabilities can also cause audible sounds from switching regulators, but they tend to be in the range of hundreds of hertz to several kilohertz. The source of subharmonic oscillations is the simultaneous conditions of fixed frequency and fixed peak amplitude of inductor current as shown in part a of the accompanying figure. ΔI T1 S1 + SX I2 I1 0 S1 S2 S1 S2 OSCILLATOR PERIOD 0 TIME a b AN19 TA05 The inductor current starts at I1, at the beginning of each switch on cycle. Current increases at a rate (S1) equal to input voltage divided by inductor value. When current reaches the trip level, I2, the current mode loop shuts off the switch and current begins to fall at a rate S2 until the switch is again turned on by the oscillator. Now watch what happens when the point T1 is perturbed so that the current exceeds I2 by ΔI. The time left for the current to fall is reduced so that the minimum current point is increased by ΔI + ΔIS2/S1. This will cause the minimum current on the next cycle to decrease by (ΔI + ΔI S2/S1)(S2/S1). On each succeeding cycle the current perturbation is multiplied by S2/S1. If S2/S1 is greater than 1, the system is unstable. The condition S2/S1 ≥ 1 occurs at a duty cycle of 50% or higher. an19fc AN19-72 Application Note 19 Subharmonic oscillations can be eliminated if an artificial ramp is superimposed on the inductor current waveform as shown in part b of the figure. If this ramp has a slope of SX, the requirement for stability is that SX + S1 be larger than S2. This leads to the following equation: SX ≥ ( ) S1 2DC − 1 1 − DC DC = duty cycle For duty cycles less than 50% (DC = 0.5), SX is a negative number and is not required. For larger duty cycles, SX takes on values dependent on S1 and duty cycle. S1 is simply VIN/L. This yields an equation for the minimum value of inductance for a fixed value of SX: LMIN ≥ The LT1070 has an internal SX voltage ramp fed into the current amplifier whose equivalent current referred value is 2 (105A/sec). A sample calculation for minimum inductance with VIN = 15V, DC = 60% is shown: LMIN = (15)(2• 0.6 − 1) = 37.5μH ⎛ 2 • 105 ⎞ 1 − 0.6 ) ⎝ ⎠( Remember that for discontinuous operation, no subharmonic oscillations can occur. Likewise, with duty cycle less than 50%, there is no restriction on inductor size. ( ) SX (1 − DC) VIN 2DC − 1 an19fc AN19-73 Application Note 19 W W U W ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage LT1070/LT1071 (Note 2) .................................... 40V LT1070HV/LT1071HV (Note 2) .......................... 60V Switch Output Voltage LT1070/LT1071 .................................................. 65V LT1070HV/LT1071HV ........................................ 75V Feedback Pin Voltage (Transient, 1ms) ................ ±15V Operating Junction Temperature Range Commercial (Operating) ....................... 0°C to 100°C Commercial (Short Circuit)................... 0°C to 125°C Industrial ......................................... – 40°C to 125°C Military ............................................ – 55°C to 150°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C W U U PACKAGE/ORDER INFORMATION BOTTOM VIEW VSW 1 4 2 CASE IS GND 3 VIN ORDER PART NUMBER ORDER PART NUMBER VC FB K PACKAGE 4-LEAD TO-3 METAL CAN TJMAX = 100°C, θJA = 35°C/ W, QJC = 2°C (LT1070C, I) TJMAX = 150°C, θJA = 35°C/ W, QJC = 2°C (LT1070M) TJMAX = 100°C, θJA = 35°C/ W, QJC = 4°C (LT1071C, I) TJMAX = 150°C, θJA = 35°C/ W, QJC = 4°C (LT1071M) OBSOLETE PACKAGE LT1070CK LT1070HVCK LT1070HVMK LT1070IK LT1070MK LT1071CK LT1071HVCK LT1071HVMK LT1071MK FRONT VIEW 5 VIN 4 VSW 3 GND 2 FB 1 VC LT1070CT LT1070HVCT LT1070HVIT LT1070IT LT1071CT LT1071HVCT LT1071HVIT LT1071IT T PACKAGE 5-LEAD PLASTIC TO-220 TJMAX = 100°C, θJA = 75°C/ W, QJC = 2°C (LT1070C, I) TJMAX = 100°C, θJA = 75°C/ W, QJC = 4°C (LT1071C) Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS VIN = 15V, VC = 0.5V, VFB = VREF, output pin open unless otherwise specified. SYMBOL PARAMETER CONDITIONS VREF Reference Voltage Measured at Feedback Pin, VC = 0.8V ● IB Feedback Input Current MIN TYP MAX UNITS 1.224 1.214 1.244 1.244 1.264 1.274 V V 350 750 1100 nA nA VFB = VREF ● gm Error Amplifier Transconductance Error Amplifier Source or Sink Current Error Amplifier Clamp Voltage AV ΔIC = ±25μA 6000 7000 μmho μmho 150 120 200 ● 350 400 μA μA 2.30 0.52 V V 0.03 %/V VC = 1.5V Hi Clamp, VFB = 1V Lo Clamp, VFB = 1.5V Reference Voltage Line Regulation 3V ≤ VIN ≤ VMAX, VC = 0.8V Error Amplifier Voltage Gain 0.9V ≤ VC ≤ 1.4V 1.80 0.25 Supply Current 3V ≤ VIN ≤ VMAX, VC = 0.6V Control Pin Threshold Duty Cycle = 0 500 ● Normal/Flyback Threshold on Feedback Pin 0.38 ● ● Minimum Input Voltage IQ 3000 2400 4400 ● 800 V/V 2.6 3.0 V 6 9 0.8 0.6 0.9 1.08 1.25 V V 0.4 0.45 0.54 V mA an19fc AN19-74 Application Note 19 ELECTRICAL CHARACTERISTICS VIN = 15V, VC = 0.5V, VFB = VREF, output pin open unless otherwise specified. SYMBOL PARAMETER CONDITIONS VFB Flyback Reference Voltage IFB = 50μA ● Change in Flyback Reference Voltage BV VSAT ILIM 0.05 ≤ IFB ≤ 1mA Flyback Reference Voltage Line Regulation IFB = 50μA, 3V ≤ VIN ≤ VMAX (Note 3) Flyback Amplifier Transconductance (gm) ΔIC = ±10μA Flyback Amplifier Source and Sink Current VC = 0.6V, IFB = 50μA (Source) VC = 0.6V, IFB = 50μA (Sink) Output Switch Breakdown Voltage TYP MAX UNITS 15 14 16.3 17.6 18.0 V V 4.5 6.8 8.5 V 0.01 0.03 %/V 150 300 650 μmho ● ● 15 25 32 40 70 70 μA μA 3V ≤ VIN ≤ VMAX, ISW = 1.5mA (LT1070/LT1071) (LT1070HV/LT1071HV) ● ● 65 75 90 90 Output Switch “On” Resistance (Note 4) LT1070 LT1071 ● ● Control Voltage to Switch Current Transconductance LT1070 LT1071 Switch Current Limit (LT1070) Duty Cycle ≤ 50%, TJ ≥ 25°C Duty Cycle ≤ 50%, TJ < 25°C Duty Cycle = 80% (Note 5) ● ● ● 5 5 4 10 11 10 A A A Switch Current Limit (LT1071) Duty Cycle ≤ 50%, TJ ≥ 25°C Duty Cycle ≤ 50%, TJ < 25°C Duty Cycle = 80% (Note 5) ● ● ● 2.5 2.5 2.0 5.0 5.5 5.0 A A A 25 35 mA/A 40 45 47 kHz kHz 92 97 ΔIIN ΔISW Supply Current Increase During Switch “On” Time f Switching Frequency 0.15 0.30 Maximum Switch Duty Cycle 35 33 90 Flyback Sense Delay Time Ω Ω 0.24 0.50 A/V A/V % μs 1.5 Shutdown Mode Supply Current 3V ≤ VIN ≤ VMAX, VC = 0.05V Shutdown Mode Threshold Voltage 3V ≤ VIN ≤ VMAX ● The ● denotes the specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Minimum switch “on” time for the LT1070/LT1071 in current limit is ≈1μs. This limits the maximum input voltage during short-circuit conditions, in the buck and inverting modes only, to ≈ 35V. Normal (unshorted) conditions are not affected. Mask changes are being implemented which will reduce minimum “on” time to ≤ 1μs, increasing maximum short-circuit input voltage above 40V. If the present LT1070/LT1071 (contact factory for package date code) is being operated in the buck or inverting mode at high input voltages and short-circuit conditions are expected, a resistor must be placed in series with the inductor, as follows: The value of the resistor is given by: R= V V 8 4 ● DC (Max) MIN 100 50 100 250 μA 150 250 300 mV mV t = Minimum “on” time of LT1070/LT1071 in current limit, ≈1μs f = Operating frequency (40kHz) VF = Forward voltage of external catch diode at ILIMIT ILIMIT = Current limit of LT1070 (≈ 8A), LT1071 (≈ 4A) RL = Internal series resistance of inductor Note 3: VMAX = 55V for LT1070HV and LT1071HV to avoid switch breakdown. Note 4: Measured with VC in hi clamp, VFB = 0.8V. ISW = 4A for LT1070 and 2A for LT1071. Note 5: For duty cycles (DC) between 50% and 80%, minimum guaranteed switch current is given by ILIM = 3.33 (2 – DC) for the LT1070 and ILIM = 1.67 (2 – DC) for the LT1071. t • f • VIN – VF – RL ILIMIT an19fc AN19-75 Application Note 19 U W TYPICAL PERFORMANCE CHARACTERISTICS Switch Current Limit vs Duty Cycle Maximum Duty Cycle 16 FOR LT1071, DIVIDE VERTICAL SCALE BY 2 96 2.2 95 2.0 94 1.8 10 – 55°C 25°C 8 125°C 6 TIME (μs) 12 DUTY CYCLE (%) 93 2 0 92 1.4 91 1.2 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 90 –75 – 50 – 25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) 1.0 –75 – 50 – 25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) 1070/71 G01 1070/71 G02 1.6 2.9 SWITCH SATURATION VOLTAGE (V) SWITCH CURRENT = 5A MINIMUM INPUT VOLTAGE (V) Isolated Mode Flyback Reference Voltage Switch Saturation Voltage Minimum Input Voltage 2.8 2.7 2.6 SWITCH CURRENT = 0A 2.5 2.4 2.3 –75 – 50 – 25 23 FOR LT1071, DIVIDE CURRENT BY 2 1.4 22 150°C 1.2 100°C 1.0 25°C 0.8 – 55°C 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 1 4 5 2 3 6 SWITCH CURRENT (A) 7 1.248 REFERENCE VOLTAGE (V) TJ = – 55°C –1 –2 –4 –5 10 30 40 20 INPUT VOLTAGE (V) 50 60 1070/71 G07 RFEEDBACK = 10k 0 25 50 75 100 125 150 TEMPERATURE (°C) 1070/71 G06 1.246 SWITCHING FREQUENCY 800 41 700 40 1.244 1.242 42 39 REFERENCE V0LTAGE 38 1.240 37 1.238 36 1.236 35 –3 0 17 15 – 75 – 50 – 25 8 1.234 – 75 – 50 – 25 34 0 25 50 75 100 125 150 TEMPERATURE (°C) 1070/71 G08 SWITCHING FREQUENCY (kHz) 1 0 18 Feedback Bias Current vs Temperature 1.250 4 TJ = 25°C RFEEDBACK = 1k 19 Reference Voltage vs Temperature 5 2 20 1070/71 G05 Line Regulation TJ = 150°C RFEEDBACK = 500Ω 21 16 1070/71 G04 3 1070/71 G03 FLYBACK VOLTAGE (V) 0 REFERENCE VOLTAGE CHANGE (mV) 1.6 4 FEEDBACK BIAS CURRENT (nA) SWITCH CURRENT (A) 14 Flyback Blanking Time 600 500 400 300 200 100 0 – 75 – 50 – 25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1070/71 G09 an19fc AN19-76 Application Note 19 U W TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Input Voltage* 16 140 15 100 80 TJ = – 55°C 60 TJ ≥ 25°C 40 ISWITCH ≤ 10mA 13 12 11 50% DUTY CYCLE 10 9 10% DUTY CYCLE 0% DUTY CYCLE 7 6 0 0 1 4 2 3 SWITCH CURRENT (A) 0 5 120 100 VC = 50mV 80 60 40 VC = 0V 10 20 40 30 SUPPLY VOLTAGE (V) 500 –24 490 –22 480 –20 –18 470 460 FEEDBACK PIN VOLTAGE (AT THRESHOLD) –14 440 –12 –10 430 FEEDBACK PIN CURRENT (AT THRESHOLD) 420 50 400 –50 –25 60 0 180 4500 TJ = 150°C 80 60 – 55°C ≤ TJ ≤ 125°C 40 gm = ΔI (VC PIN) ΔV (FB PIN) 4000 3500 3000 2500 2000 1500 1000 500 20 0 TRANSCONDUCTANCE (μmho) SUPPLY CURRENT (μA) Error Amplifier Transconductance 5000 140 –4 25 50 75 100 125 150 TEMPERATURE (°C) 1070/71 G13 Shutdown Mode Supply Current 160 –8 –6 410 200 100 –16 450 1070/71 G12 120 60 1070/71 G11 FEEDBACK PIN CURRENT (μA) FEEDBACK PIN VOLTAGE (mV) 140 0 50 Normal/Flyback Mode Threshold on Feedback Pin TJ = 25°C 20 30 40 20 INPUT VOLTAGE (V) *UNDER VERY LOW OUTPUT CURRENT CONDITIONS, DUTY CYCLE FOR MOST CIRCUITS WILL APPROACH 10% OR LESS Supply Current vs Supply Voltage (Shutdown Mode) 160 10 1070/71 G10 *AVERAGE LT1070 POWER SUPPLY CURRENT IS FOUND BY MULTIPLYING DRIVER CURRENT BY DUTY CYCLE, THEN ADDING QUIESCENT CURRENT SUPPLY CURRENT (μA) 90% DUTY CYCLE 8 20 0 TJ = 25°C 14 120 INPUT CURRENT (mA) DRIVER CURRENT (mA) Driver Current* vs Switch Current 160 0 10 20 30 40 50 60 70 80 90 100 VC PIN VOLTAGE (mV) 1070/71 G14 0 –75 – 50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1070/71 G14 an19fc AN19-77 Application Note 19 U W TYPICAL PERFORMANCE CHARACTERISTICS Idle Supply Current vs Temperature Shutdown Thresholds 400 CURRENT (OUT OF VC PIN) –300 250 –250 200 –200 VOLTAGE 150 –150 100 –100 VC VOLTAGE IS REDUCED UNTIL REGULATOR CURRENT DROPS BELOW 300μA 50 0 – 75 – 50 – 25 VC PIN CURRENT (μA) 300 VC = 0.6V 10 –350 IDLE SUPPLY CURRENT (mA) 350 VC PIN VOLTAGE (mV) 11 – 400 – 50 9 8 VSUPPLY = 60V 7 6 VSUPPLY = 3V 5 4 3 2 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 1 –75 – 50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1070/71 G16 1070/71 G14 Switch “Off” Characteristics 1000 450 900 400 800 – 55°C SWITCH CURRENT (μA) FEEDBACK VOLTAGE (mV) Feedback Pin Clamp Voltage 500 350 25°C 300 250 150°C 200 150 700 600 500 200 50 100 0 0 3V 300 100 0 VSUPPLY = 400 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FEEDBACK CURRENT (mA) 0 15V 40V 55V 10 20 30 40 50 60 70 80 90 100 SWITCH VOLTAGE (V) 1070/71 G19 1070/71 G18 Transconductance of Error Amplifier VC Pin Characteristics 300 6000 VFB = 1.5V (CURRENT INTO VC PIN) 100 0 –100 VFB = 0.8V (CURRENT OUT OF VC PIN) – 200 – 300 – 400 30 5000 gm 4000 0.5 2.0 1.5 1.0 VC PIN VOLTAGE (V) 2.5 1070/71 G20 60 3000 90 2000 120 1000 150 0 180 –1000 0 0 θ 1k 10k 100k 1M FREQUENCY (Hz) PHASE (°) TRANSCONDUCTANCE (μmho) 200 VC PIN CURRENT (μA) – 30 7000 TJ = 25°C 210 10M 1070/71 G21 an19fc AN19-78 Application Note 19 INDUCTOR/TRANSFORMER MANUFACTURERS Pulse Engineering Inc. (619/268-2400) P.O. Box 12235, San Diego, CA 92112 Hurricane Electronics Lab (801/635-2003) P.O. Box 1280, Hurricane, UT 84737 Coilcraft Inc. (312/639-2361) 1102 Silver Lake Rd., Cary, IL 60013 Renco Electronics, Inc. (516/586-5566) 60 Jefryn Blvd. East, Deer Park, NY 11729 CORE MANUFACTURERS Ferroxcube (ferrites) (914/246-2811) 5083 Kings Highway, Saugerties, NY 12477 Micrometals (powdered iron) (714/630-7420) 1190 N. Hawk Circle, Anaheim, CA 92807 Pyroferric International Inc. (powdered iron) (217/849-3300) 200G Madison St., Toledo, IL 62468 Fair-Rite Products Corp. (ferrites) (914/895-2055) P.O. Box J, Wallkill, NY 12589 Stackpole Corp., Ferrite Products Group (814/781-1234) Stackpole St., St. Mary’s, PA 15857 Magnetics Division–Spang & Co.(ferrites)(412/282-8282) P.O. Box 391, Butler, PA 16003 TDK Corp. of America, Industrial Ferrite Products (312/679-8200) 4709 W. Golf Rd., Skokie, IL 60076 BIBLIOGRAPHY Pressman, A.I., “Switching and Linear Power Supply, Power Converter Design,” Hayden Book Co., Hasbrouck Heights, New Jersey, 1977, ISBN 0-8104-5847-0. Chryssis, G., “High Frequency Switching Power Supplies, Theory and Design,” McGraw Hill, New York, 1984, ISBN 0-07-010949-4. Grossner, N.R., “Transformers for Electronic Circuits,” McGraw Hill, New York, 1983, ISBN 0-07-024979-2. Middlebrook, R.D., and ’Cuk, S., “Advances in Switched Mode Power Conversion,” Volumes I, II, III, TESLA Co., Pasadena, CA, 1983. Proceedings of Powercon, Power Concepts, Inc. Box 5226, Ventura, CA “Linear Ferrite Magnetic Design Manual,” Ferroxcube Inc., Saugerties, NY “Design Manual for SMPS Power Transformers,” Pulse Engineering Inc., San Diego, CA an19fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. AN19-79 Application Note 19 U PACKAGE DESCRIPTION T Package 5-Lead Plastic TO-220 (Standard) (LTC DWG # 05-08-1421) .390 – .415 (9.906 – 10.541) .165 – .180 (4.191 – 4.572) .147 – .155 (3.734 – 3.937) DIA .045 – .055 (1.143 – 1.397) .230 – .270 (5.842 – 6.858) .460 – .500 (11.684 – 12.700) .570 – .620 (14.478 – 15.748) .620 (15.75) TYP .330 – .370 (8.382 – 9.398) .700 – .728 (17.78 – 18.491) .095 – .115 (2.413 – 2.921) SEATING PLANE .152 – .202 .260 – .320 (3.861 – 5.131) (6.60 – 8.13) .155 – .195* (3.937 – 4.953) .013 – .023 (0.330 – 0.584) BSC .067 (1.70) .135 – .165 (3.429 – 4.191) .028 – .038 (0.711 – 0.965) * MEASURED AT THE SEATING PLANE T5 (TO-220) 0801 K Package 4-Lead TO-3 Metal Can (LTC DWG # 05-08-1311) 0.320 – 0.350 (8.13 – 8.89) 0.760 – 0.775 (19.30 – 19.69) 0.060 – 0.135 (1.524 – 3.429) 0.420 – 0.480 (10.67 – 12.19) 0.038 – 0.043 (0.965 – 1.09) 1.177 – 1.197 (29.90 – 30.40) 0.470 TP P.C.D. 0.655 – 0.675 (16.64 – 19.05) 0.151 – 0.161 (3.84 – 4.09) DIA 2 PLC 0.167 – 0.177 (4.24 – 4.49) R 72° 18° 0.490 – 0.510 (12.45 – 12.95) R K4(TO-3) 1098 OBSOLETE PACKAGE an19fc AN19-80 Linear Technology Corporation LT 0309 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com © LINEAR TECHNOLOGY CORPORATION 1986

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