DS2526Q 01

®
RT2526Q
DDR Termination Regulator
General Description
Features
The RT2526Q is a 2A sink/source tracking termination
regulator. It is specifically designed for low-cost and lowexternal component count systems. The RT2526Q
possesses a high speed operating amplifier that provides
fast load transient response and only requires 20μF of
ceramic output capacitance. The RT2526Q supports
remote sensing functions and all features required to power
the DDRII/DDRIII VTT bus termination according to the
JEDEC specification. In addition, the RT2526Q includes
integrated sleep-state controls placing VTT in High-Z in
S3 (suspend to RAM) The RT2526Q is available in the
thermal efficient package SOP-8 (Exposed Pad).

Ordering Information

RT2526Q

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Lead Plating System
G : Green (Halogen Free and Pb Free)
DDRIII,
Low-Power
Source/Sink 2A for DDRII and DDRIII
Input Voltage Range : 3.1V to 3.6V
VLDOIN Voltage Range : 1.2V to 1.8V
Requires Only 20μ
μF Ceramic Output Capacitance
Supports High-Z in S3
Integrated Divider Tracks 1/2 VDDQSNS for Both VTT
and VTTREF
Remote Sensing (VTTSNS)
±20mV Accuracy for VTT and VTTREF
10mA Buffered Reference (Sourcing/Sinking)
(VTTREF)
Built-In Soft-Start
Current Limit
Thermal Shutdown
RoHS Compliant and Halogen Free
Applications
Note :

Richtek products are :

DDRII, DDRIII Memory Termination
SSTL-2, SSTL-18, HSTL Termination
RoHS compliant and compatible with the current require-
Pin Configurations
ments of IPC/JEDEC J-STD-020.

and

Package Type
SP : SOP-8 (Exposed Pad-Option 1)

Supports DDRII
Requirement
Suitable for use in SnPb or Pb-free soldering processes.
(TOP VIEW)
RT2526Q
GSPYMDNN
8
GND
Marking Information
S3
2
RT2526QGSP : Product Number
VTTSNS
3
YMDNN : Date Code
VTTREF
7
GND
6
9
4
5
VTT
VLDOIN
VIN
VDDQSNS
SOP-8 (Exposed Pad)
Simplified Application Circuit
RT2526Q
VLDOIN
VLDOIN
C1
3.3V
VTTREF
VDDQSNS
VTTSNS
VIN
VTT
GND
DS2526Q-01 July 2015
VTT
C4
C2
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
VTTREF
C3
S3
S3
is a registered trademark of Richtek Technology Corporation.
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1
RT2526Q
Functional Pin Description
Pin No.
Pin Name
Pin Function
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
1, 9 (Exposed Pad) GND
2
S3
Active Low Suspend to RAM Mode Control Input. In S3 state, VTT is turned
off and left High-Z, VTTREF is active.
3
VTTSNS
VTT Voltage Sense Input. Connect to plus terminal of the output capacitor.
4
VTTREF
Buffered Output. The reference output voltage equals to VDDQSNS / 2.
5
VDDQSNS
VLDOIN Sense Input.
6
VIN
Supply Voltage Input for Control Circuit.
7
VLDOIN
Power Input for VTT Output Stage.
8
VTT
Power Output of the Regulation. The output voltage equals to VDDQSNS / 2.
Function Block Diagram
VDDQSNS
+
VLDOIN
Half DDQ
+
-
VTTREF
-
GND
VIN
ENREF
+
2.32V/
2.2V
+
VIN OK
VTT
-
-
ENVTT
ENVTT
S3
(10%)
+
+
-
+
PGOOD
+
-
(10%)
VTTSNS
Table 1. S3 Control Table
State
S3
VTT
VTTREF
Normal
High
0.75V
0.75V
Standby
Low
High-Z
0.75V
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is a registered trademark of Richtek Technology Corporation.
DS2526Q-01 July 2015
RT2526Q
Operation
Shutdown Mode
VTTREF Buffer
The shutdown mode will happen when the S3 input voltage
is under the logic threshold. The VTT pin will be high
impedance and VTTREF will remain active under shutdown
mode.
The buffer senses the input voltage from VDDQSNS and
provides an internal reference voltage of VDDQSNS/2 for
VTT regulator.
VTT Regulator
VIN OK and Thermal Shutdown
The regulator will detect VIN voltage and junction
temperature. When VIN is lower than the VIN OK threshold
or the junction temperature is over the thermal shutdown
threshold, both the VTT and VTTREF will be discharged
to GND.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS2526Q-01 July 2015
The VTT output is capable of sinking and sourcing current
while sensing from the VTTSNS pin to regulate the output
precisely to VTTREF.
is a registered trademark of Richtek Technology Corporation.
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RT2526Q
Absolute Maximum Ratings
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(Note 1)
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------Supply Input Voltage, VLDOIN, VDDQSNS ------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------------
Recommended Operating Conditions
6V
3.6V
2.04W
49°C/W
15°C/W
260°C
150°C
−65°C to 150°C
2kV
(Note 4)

Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- 3.1V to 3.6V

Supply Input Voltage, VLDOIN, VDDQSNS ------------------------------------------------------------------------- 1.2V to 1.8V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C


Electrical Characteristics
(VIN = 3.3V, VLDOIN = VDDQSNS = 1.5V, TA = −40°C to 85°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VIN Supply Current
IVIN
No Load, S3 = 3.3V
--
--
2
mA
VIN Standby Current
IVINSTB
No Load, S3 = 0V
--
--
300
A
VLDOIN Supply Current
IVLDOIN
No Load, S3 = 3.3V
--
--
2
mA
VLDOIN Standby Current
IVLDOINSTB
No Load, S3 = 0V
--
--
10
A
VDDQSNS Input Current
IVDDQSNS
S3 = 3.3V
--
--
50
A
VTTSNS Input Current
IVTTSNS
S3 = 3.3V
--
--
1
A
VTT Output Voltage
VTT
VDDQSNS = VLDOIN = 1.5V
0.735
0.75
0.768
V
VDDQSNS = VLDOIN = 1.5V,
∣IVTT∣= 0A
20
--
20
VDDQSNS = VLDOIN = 1.5V,
∣IVTT∣= 1.5A
40
--
40
VTTREF, VTT Output
Tolerance
VVTTTOL
mV
VTT Source Current Limit
IVTTOCLsr
VTT = 0V
2.3
3.3
--
A
VTT Sink Current Limit
IVTTOCLsk
VTT = VDDQSNS
2.3
4.3
--
A
VTTREF Output Voltage
VVTTREF
VDDQSNS = 1.5V, IVTTREF = 0mA
0.735
0.75
0.768
VDDQSNS = 1.5V, IVTTREF < 10mA
0.728
0.75
0.772
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V
is a registered trademark of Richtek Technology Corporation.
DS2526Q-01 July 2015
RT2526Q
Parameter
UVLO Threshold Voltage
Symbol
VUVLO
Test Conditions
Min
Typ
Max
Rising
--
--
2.7
Falling
1.4
--
2.4
Unit
V
Logic-High
VIH
1.6
--
--
Logic-Low
VIL
--
--
0.4
S3 Input Leakage Current
IILK
--
--
1
A
Thermal Shutdown
Protection
TSD
--
160
--
C
Thermal Shutdown
Hysteresis
T SD
--
20
--
C
S3 Input
Voltage
V
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS2526Q-01 July 2015
is a registered trademark of Richtek Technology Corporation.
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RT2526Q
Typical Application Circuit
RT2526Q
VLDOIN
3.3V
7
C1
10µF
5
VLDOIN
1, 9 (Exposed Pad)
VTTSNS
VIN
GND
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6
C3
0.1µF
VDDQSNS
6
C2
1µF
VTTREF 4
VTT
S3
VTTREF
3
8
C4
10µF x 2
2
VTT
S3
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DS2526Q-01 July 2015
RT2526Q
Typical Operating Characteristics
VTTREF Output Voltage vs. Temperature
1.0
0.9
0.9
Output Voltage(V)
Output Voltage (V)
VTT Output Voltage vs. Temperature
1.0
0.8
0.7
0.6
0.8
0.7
0.6
VIN = 3.3V,
VLDOIN = VDDQSNS = 1.5V, VTT = 0.75V
VIN = 3.3V,
VLDOIN = VDDQSNS = 1.5V, VTT = 0.75V
0.5
0.5
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
240
1100
220
Standby Current (µA)
Supply Current (µA)
75
100
125
VIN Standby Current vs. Temperature
VIN Supply Current vs. Temperature
1000
900
800
200
180
160
140
120
VIN = 3.3V,
VLDOIN = VDDQSNS = 1.5V, VTT = 0.75V
VIN = 3.3V,
VLDOIN = VDDQSNS = 1.5V, VTT = 0.75V
100
600
-50
-25
0
25
50
75
100
-50
125
-25
0
UVLO vs. Temperature
3.0
1.2
S3 Threshold Voltage (V)
1.4
Rising
2.0
Falling
1.5
1.0
50
75
100
125
S3 Threshold Voltage vs. Temperature
3.5
2.5
25
Temperature (°C)
Temperature (°C)
UVLO (V)
50
Temperature (°C)
1200
700
25
VLDOIN = VDDQSNS = 1.5V,
S3 = 2V, VTT = 0.75V
0.5
Rising
1.0
0.8
Falling
0.6
0.4
0.2
VIN = 3.3V,
VLDOIN = VDDQSNS = 1.5V, VTT = 0.75V
0.0
-50
-25
0
25
50
75
100
Temperature (°C)
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DS2526Q-01 July 2015
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT2526Q
Sink Current Limit vs. Temperature
5.0
4.5
4.5
Sink Current Limit (A)
Source Current Limit (A)
Source Current Limit vs. Temperature
5.0
4.0
3.5
3.0
2.5
VIN = 3.3V,
VLDOIN = VDDQSNS = 1.5V, VTT = 0.75V
4.0
3.5
3.0
2.5
VIN = 3.3V,
VLDOIN = VDDQSNS = 1.5V, VTT = 0.75V
2.0
2.0
-50
-25
0
25
50
75
100
-50
125
0
25
50
75
Temperature (°C)
Temperature (°C)
Power On from S3
Power Off from S3
S3
(2V/Div)
S3
(2V/Div)
VTT
(0.5V/Div)
VTT
(0.5V/Div)
IVTT
(1A/Div)
IVTT
(1A/Div)
VTTREF
(1V/Div)
-25
VIN = 3.3V, VLDOIN = VDDQSNS = 1.5V,
VTT = 0.75V, IOUT = 1.5A
VTTREF
(1V/Div)
100
125
VIN = 3.3V, VLDOIN = VDDQSNS = 1.5V,
VTT = 0.75V, IOUT = 1.5A
Time (10μs/Div)
Time (10μs/Div)
0.75VTT @ 1.5A Transient Response
0.75VTT @ 1.5A Transient Response
VTT
(10mV/Div)
VTT
(10mV/Div)
IVTT
(1A/Div)
IVTT
(1A/Div)
Source, VLDOIN = 1.5V
Time (500μs/Div)
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Sink, VLDOIN = 1.5V
Time (500μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS2526Q-01 July 2015
RT2526Q
Application Information
VTTREF Regulator
VTTREF is a reference output voltage with source/sink
current capability up to 10mA. To ensure stable operation
0.1μF ceramic capacitor between VTTREF and GND is
recommended.
S3 Logic Control
The S3 terminal should be connected to SLP_S3 signals
respectively. Both VTTREF and VTT are turned on at
normal state (S3 = High). In standby state (S3 = Low),
VTTREF is kept alive while VTT is turned off and left high
impedance.
Table 2. S3 Control Talbe
STATE
Normal
Standby
S3
H
L
VTT
ON
OFF (High-Z)
VTTREF
ON
ON
Capacitor Selection
Good bypassing is recommended from VLDOIN to GND
to help improve AC performance. A 10μF or greater input
capacitor located as close as possible to the IC is
recommended. The input capacitor must be located at a
distance of less than 0.5 inches from the VLDOIN pin of
the IC.
Adding a 1μF ceramic capacitor close to the VIN pin and
it should be kept away from any parasitic impedance from
the supply power. For stable operation, the total
capacitance of the ceramic capacitor at the VTT output
terminal must not be larger than 30μF. The RT2526Q is
designed specifically to work with low ESR ceramic output
capacitor in space saving and performance consideration.
Larger output capacitance can reduce the noise and
improve load transient response, stability and PSRR. The
output capacitor should be located near the VTT output
terminal pin as close as possible.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS2526Q-01 July 2015
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 (Exposed Pad) package, the thermal resistance,
θJA, is 49°C/W on a standard JEDEC 51-7 four-layer
thermal test board. The maximum power dissipation at TA
= 25°C can be calculated by the following formula :
P D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W for
SOP-8 (Exposed Pad) package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
2.5
Maximum Power Dissipation (W)1
The RT2526Q is a 2A sink/source tracking termination
regulator. It is specifically designed for low-cost and lowexternal component count system such as notebook PC
applications. The RT2526Q possesses a high speed
operating amplifier that provides fast load transient response
and only requires a 10μF ceramic input capacitor and two
10μF ceramic output capacitors.
Four-Layer PCB
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 1. Derating Curve of Maximum Power Dissipation
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RT2526Q
Outline Dimension
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
B
X
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
4.000
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.000
0.152
0.000
0.006
J
5.791
6.200
0.228
0.244
M
0.406
1.270
0.016
0.050
X
2.000
2.300
0.079
0.091
Y
2.000
2.300
0.079
0.091
X
2.100
2.500
0.083
0.098
Y
3.000
3.500
0.118
0.138
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS2526Q-01 July 2015