! & October 17, 2007 " # $ ' #( ) * & + ) ,! ) ! % (c) IBM Corporation -. /) . 0 1 ) 5- 2 . 6 8) 9 ;) - % 5 3 ! 45- 67 0% : , ! & * <) October 17, 2007 (c) IBM Corporation 2 # % # . 1 5- 6 ! % 1 %' 2 5) =/ 46 ; > ' 6;> 7 ' # ? = % 5 , % . % %% . =8 8 # 2 # 6< ! 8;/ ! ! / = A ! B C 1 - ! " B October 17, 2007 @ ! % 1 8 )< ' ; ) ' ; ) $ @ ! 2 ! C (c) IBM Corporation IBM System p IBM POWER SYSTEMS Consistent Predictable Delivery 2003 2001 2004 2006 2007 POWER6 POWER5+ POWER5 POWER4+ POWER4 All statements regarding IBM future directions and intent are subject to change or withdrawal without notice and represent goals and © 2006 IBM objectives Corporation only. Any reliance on these Statements of General Direction is at the relying party's sole risk and will not create liability or © 2006 IBM Corporation obligation for IBM. IBMSystems Systems IBM IBM System p POWER6 Core POWER6 processor is ~2X frequency of POWER5 (4-5GHz) POWER6 instruction pipeline depth equivalent to POWER5 – Minimize power – Scale performance with frequency Instruction Fetch Instruction Buffer/Decode Instruction Dispatch/Issue Data Fetch/Execute ~6ns/instr ~3ns/instr FXU Dependent execution Load Dependent execution POWER6 Extends functionality of POWER5 Core – – – – – 64K I Cache, 64K D Cache, 2 FXU, 2 FPU, 1 Branch execution unit Two way SMT with 7 instruction dispatch from 2 threads (maximum of 5 instructions per thread) Decimal Unit VMX Unit Recovery Unit All statements regarding IBM future directions and intent are subject to change or withdrawal without notice and represent goals and © 2006 IBM objectives Corporation only. Any reliance on these Statements of General Direction is at the relying party's sole risk and will not create liability or © 2006 IBM Corporation obligation for IBM. IBMSystems Systems IBM IBM System p POWER6 scales chip capabilities with core performance Cache highlights – 4MB Private L2 Cache per Core – 32MB Non-sectored L3 Cache per chip Fabric highlights – Three Intra-Node SMP buses for 8-way Node – Two Inter-Node SMP buses for up to 8 Nodes – Multiplexed Address/Data SMP buses 80GB/s New prefetching capabilities – Coherent Multi-Cacheline Data Prefetch Operations – Prefetching on stores Core Core (SMT+, VMX) (SMT+, VMX) Corona L3 Cache 32MB 2X2B A 2X8B D 2X8B D 4X1B 4X1B 4X2B 4X1B 4X1B 4X2B 75 GB/s A D D A D D L2 Cache (8.0MB) L3 Dir L3 Cntl 20GB/s Mem Cntl Mem Cntl 4B 4B A/D A/D GX+ Cntl Fabric A/D 8B A/D 8B GX+ Bus A /D 8B A /D A/D A/D A/D A/D A/D A /D 8B 8B 8B 8B 8B 8B 8B Intra-Node 8W SMP Buses Total = 300 GB/s 50GB/s 80GB/s All statements regarding IBM future directions and intent are subject to change or withdrawal without notice and represent goals and © 2006 IBM objectives Corporation only. Any reliance on these Statements of General Direction is at the relying party's sole risk and will not create liability or © 2006 IBM Corporation obligation for IBM. IBMSystems Systems IBM IBM System p Flex System to optimize low end to high end server designs SMP busses can be configured in two modes – Cost/performance trade-offs – On node busses are 8B or 2B – Off node busses are 8B or 4B 2 socket Numerous memory controller BW options – 1 or 2 memory controllers are available – Memory controllers can be configured to full width or ½ width L3 cache is supported in three configurations 4 socket – On module High Bandwidth configuration – Optional off module configuration – No L3 option Fully interconnected two-tier SMP fabric – Reduced latencies vs. POWER5 – New two tier memory coherency protocol 32 socket / 64way SMP All statements regarding IBM future directions and intent are subject to change or withdrawal without notice and represent goals and © 2006 IBM objectives Corporation only. Any reliance on these Statements of General Direction is at the relying party's sole risk and will not create liability or © 2006 IBM Corporation obligation for IBM. IBMSystems Systems IBM IBM System p Bullet-proof computing Core Recovery Capability – Array error • Error correction (ECC) • Arrays with parity – Processor restarts – Instruction flow and Data flow Error • Processor restarts – Control Error • Processor restarts Instruction Fetch Decode Execution Units Load/ Store Core error collection Recovery unit Core restart System Resiliency – Processor states are check pointed and protected with ECC – Processor states can be moved from one processor to another upon unsuccessful recovery restart All statements regarding IBM future directions and intent are subject to change or withdrawal without notice and represent goals and © 2006 IBM objectives Corporation only. Any reliance on these Statements of General Direction is at the relying party's sole risk and will not create liability or © 2006 IBM Corporation obligation for IBM. IBMSystems Systems IBM IBM System p Bullet-proof computing System reliability with recovery unit – Every measure possible taken to preserve application execution – Retry soft errors – Change hardware for hard errors Processor architected state check pointed Every 1 cycle ECC & Non-ECC protected circuitry checked Every cycle Processor restarts from last saved checkpoint Soft error case Processor workload moved to another CPU Hard error case All statements regarding IBM future directions and intent are subject to change or withdrawal without notice and represent goals and © 2006 IBM objectives Corporation only. Any reliance on these Statements of General Direction is at the relying party's sole risk and will not create liability or © 2006 IBM Corporation obligation for IBM. IBMSystems Systems IBM IBM System p PowerExecutive Extensions for POWER6 Energy Management Policies Example Energy Management Policies: PowerExecutive Energy cost management – Monitor System workloads/power consumption • If: System utilization reduces reduce system power/performance • If: Multiple Systems go below utilization threshold consolidate workloads • If: System power budgets exceed allocation cap power Acoustic optimization – Monitor Systems temperature • If system temperatures go below threshold reduce fan speeds Performance optimization – Monitor system temperature/power consumption • If temperatures/power consumption go below threshold increase performance Energy Management Policies Enable Customers To Maximize The Compute Capability Of Their Datacenter Or Minimize Energy Costs All statements regarding IBM future directions and intent are subject to change or withdrawal without notice and represent goals and © 2006 IBM objectives Corporation only. Any reliance on these Statements of General Direction is at the relying party's sole risk and will not create liability or © 2006 IBM Corporation obligation for IBM. IBMSystems Systems IBM IBM System p Power6 EMPATH System Control Extended System Functions For PowerExecutive Policies Thermal / Power Measurement IBM Director PowerExecutive Hardware Management Module – Read thermal data from processor chip thermal sensors – Measure power data from system level sensors – Report data via PowerExecutive Power Capping – Use of Hardware controls to keep system power under a specified limit IBM POWER6 Service Processor Power Control Firmware AME API Power Mgmt Policies Power EMPATH Controller Power Measurement Circuits Power Saving – Operation at reduced power when workload and policy allows • Can be a static policy (e.g. overnight reduction) • Can be dynamic (when absolute max performance is not always required) System health monitoring – Use of hardware sensors to ensure system is operating within safe predefined bounds Performance-Aware Power Management – Use of dedicated performance counters to guide power and thermal management tradeoffs Modules All statements regarding IBM future directions and intent are subject to change or withdrawal without notice and represent goals and © 2006 IBM objectives Corporation only. Any reliance on these Statements of General Direction is at the relying party's sole risk and will not create liability or © 2006 IBM Corporation obligation for IBM. IBMSystems Systems IBM IBM System p Power6 Summary & Conclusions POWER6 doubles frequency and bandwidth of POWER5 – Same pipe depth – Same power envelope POWER6 scales chip/system performance with core performance POWER6 provides new capabilities – Decimal Floating Point – Processor recovery POWER6 provides “mainframe”-like reliability for Unix platform System P will begin delivery of system power management with POWER6 POWER6 systems shipping since mid 2007 All statements regarding IBM future directions and intent are subject to change or withdrawal without notice and represent goals and © 2006 IBM objectives Corporation only. Any reliance on these Statements of General Direction is at the relying party's sole risk and will not create liability or © 2006 IBM Corporation obligation for IBM. IBMSystems Systems IBM -. . /) 0 1 ) !" 8) 9 ;) - % 5 2 . 3 ! 45- 67 #$ : , ! & * <) October 17, 2007 (c) IBM Corporation 5 October 17, 2007 9 5- 6 : (c) IBM Corporation 5- 6 5 %& & ' & ' ' ( ( & ) * ) % (0 ', 1 2 % D . )# ' + B % 3 & !% ( ) ' % , & ) . )' 7 0 , ! , ) ) . . . ) D . , D , 0) 4 % October 17, 2007 3 -+ * ! ', . ( * ( ! . 3! . (+/ $ % 3 '. ', @ ) ! , (c) IBM Corporation 5- 6 #= # #= 4 5 = # =' 7 = 3 . & 3 5 = D ) !% ! # 5 ! $ 4$ 5 0 ) +. ' ( 2$ 7 ) ! EE # B C . 4 ! 1 4 ! 7B 4 0 D 7 4 ! ' 7 , * # , ! &7 & 4& 7 ! October 17, 2007 (c) IBM Corporation 5- 6 ! 4/ D 9 / ! D 07 2 ' ) 3B ./ 0 & 4/ 2/D 07 &$ ) ' ) ' ) ' ) ' ) $ 1 5- E B ! E-3 D1 % 2 0%) $ 1 5- E F, D1 % 2 $ 1 $ $ ! 2, D1 D ! D1 D 2 1 ' ) $ 1 ! 2, * H 5- H October 17, 2007 1 5 2 %4 2- 4 GE= ) D % ! E 2 E % ! E DE ) ! ' 2 ' DE% ! 2, D1 ! 4/07 0 ! 2, D1 / 2! 0%) ' ' 2 2, 2 0 % ! 0%) 2 ' %7 !7 (c) IBM Corporation ! 2 4 )7 1 ) % & 2, % 2 ) (0 ! D F ) )) ! F% ! G %% G 3 ! 0 ! + F. 2I $& 2 2I & * ( $ G 2I ! J % %2I ! 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B % % 2, , October 17, 2007 B 4 7 . ! ! &. , , , % % % . ! . % ! , , 4 7 . ! . . ! ! ! ! !% ! (c) IBM Corporation # N % (0 1 2 ' & . !% ' ( % ) & ! 2 $ ( * ( ! * 2 ! 5 J ! ! ! . D ! 5 !% ! ! October 17, 2007 . 2 % % (c) IBM Corporation 5 October 17, 2007 9- : (c) IBM Corporation # 6 *% ! %B ! 4 # 1 The biggest issue in design verification is that all currently known algorithmic solutions are running out of capacity with respect to the designs being developed today. The only foreseeable way to overcome this issue in the short term is with an adequate verification methodology. Many challenges are still to be solved to obtain a sufficiently robust and complete methodology. For instance, there is a need for ways to obtain consistent abstraction techniques of design components, interfaces, etc., that do not drop key aspects of the design in the abstraction October 17, 2007 (c) IBM Corporation 7 -. /) . 0 1 ) 58) ;) 2 6 3 ! ) )) ) 45- 67 0% 9 $ . : 3) 1 / <) October 17, 2007 (c) IBM Corporation -% 5 , ! & 4/7 1 5 !% @ D ! 1 1 , . . F 2 G % , . 2I ! 2I ! ! 4 ! 4 7 7 ! ! ! October 17, 2007 (c) IBM Corporation ! -% 1 5 & , ! & '0 4 7 $) ( !" ' . % 4% ' 7 2 ! @ . D% 9 @ ! 3 9 ! 2 2 J 4 J % 2 2 2 . % . . ! D4 0 ! % ! D October 17, 2007 . D3 (0 1 3) ! ! , D 3 2 # F! G ) O % . !% 0 , 7 0 , $ ' 2, ) (c) IBM Corporation F5 -% 5 . . G % . , ! & 48 7 3P 2! . ! ! . ! % , ! , . , % % % ' % %% . . . . ' % % , B# ' % 3) ! 2 0 @ ! D (04 3 %3 ! @ ! 0 ! % . '4 !% . !% ! ! 27 3 ! ! ! . ! 4 , . % , . October 17, 2007 3J , ! % ! @ . . . ! . " % 2 2 % . . % D . F! ! G (c) IBM Corporation -% 5 5 , ! & 4; 7 . D ! %' %' @ 1 D 2 % ! . % ! ! 25- ! . C , . (0 !, D ! @ 3) ! ! ! . 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'! 2 ! 2 % + ! , . ! , , 0% 2 % ! !, 7 8 8 " 9% ! /$ 1 Many challenges are still to be solved to obtain a sufficiently robust and complete methodology. For instance, there is a need for ways to obtain consistent abstraction techniques of design components, interfaces, etc., that do not drop key aspects of the design in the abstraction October 17, 2007 (c) IBM Corporation * 5 46 7 2 5 5 2 ! , ! 1 %% % 2 F % G % ! % , 2 1 0 . ! , . , : % 2 % G. : F! . ! 4 B# 7 : ' % October 17, 2007 2 . %% : (c) IBM Corporation -. /) . 0 1 ) 5- . 6 8) 9 ;) - % 5 <) 2 3 ! 45- 67 0% : , ! & * ) October 17, 2007 (c) IBM Corporation # . . D . % % R D , # 2 ! ! . D ! J . D . " ! . D % % 2 . . . ! % . . October 17, 2007 ! 8 % J ! !% ! ! % ! . ! ! 2 + ) *0 ) % , ! 3 (c) IBM Corporation