LTC3643 2A Bidirectional Power Backup Supply FEATURES DESCRIPTION Bidirectional Synchronous Boost Capacitor Charger/Buck Regulator for System Backup nn Wide Input Voltage Range: 3V to 17V nn Up to 40V Capacitor Voltage Storage for High Energy Backup nn 2A Maximum CAP Charge Current nn Integrated Power N-Channel MOSFETs (150mΩ Top and 75mΩ Bottom) nn Integrated Power N-Channel MOSFET for Output/CAP Disconnect (50mΩ) nn Input Current Limit During Charging nn Fast 1MHz Switching Frequency nn ±1% Reference Accuracy for System Voltage Regulation nn Indicator Outputs for Charge Status and Input Power Fail nn Low Profile 24-lead 3mm × 5mm QFN Package The LTC®3643 is a bidirectional synchronous step-up charger and step-down converter which efficiently charges a capacitor array up to 40V from an input supply between 3V to 17V. When the input supply falls below the programmable power-fail threshold, the step-up charger operates in reverse as a synchronous step-down regulator to power the system rail from the backup capacitor during this power interuption/failure condition. nn When charging the backup capacitor, an external low-value sense resistor may be used to maintain an accurate current limit from the input supply or implement PowerPath™ functionality. The step-down converter operates at a 1MHz switching frequency, allowing small external components to be used. Low quiescent current during regulation maximizes the energy usage from the backup capacitor. APPLICATIONS L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks and PowerPath is trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents. Including 5481178, 6580258, 6498466, 6611131, 5705919. Backup Capacitor Systems nn Power Failure Backup Systems nn Solid-State Drives nn TYPICAL APPLICATION Approximate Charge/Backup Time Per 1mF of Storage Cap (40V Backup) 40V Backup System Regulating System Supply to 5V 500 4.7µH CLP VIN INDIS GATE 35.7k 0.1µF 47µF SW BOOST 40V BACKUP CAP INTVCC RUN 22µF 4.7µF PFI LTC3643 44.2k 392k FBCAP FBSYS 12.1k 6.04k 6.04k + 1mF ENERGY STORAGE ITH CAPGD PFO SYSTEM LOAD 22pF 470pF CHARGE TIME BACKUP TIME WITH 2A LOAD BACKUP TIME WITH 1A LOAD BACKUP TIME WITH 0.5A LOAD 400 300 200 100 0 400k GND CHARGE/BACKUP TIME (ms) 0.01Ω POWER SUPPLY 3 6 9 12 SYSTEM LOAD VOLTAGE (V) 15 3643 TA01b 3643 TA01a 3643fb For more information www.linear.com/LTC3643 1 LTC3643 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) ILIM NC NC CLP TOP VIEW 24 23 22 21 PGND 1 20 SW PGND 2 19 SW CAP 3 18 SW VIN 4 17 INDIS 25 SGND VIN 5 16 INDIS GATE 6 15 BOOST RUN 7 14 INTVCC 13 PFI FBSYS 8 PFO CAPGD ITH 9 10 11 12 FBCAP VIN.............................................................. –0.3V to 17V RUN................................................... –0.3V to VIN+0.3V CLP............................................................. –0.3V to 17V CAP............................................................. –0.3V to 42V BOOST-SW.................................................... –0.3V to 4V INTVCC, FBSYS, FBCAP................................. –0.3V to 4V PFI................................................................ –0.3V to 4V ILIM..............................................–0.3V to VINTVCC+0.3V PFO, CAPGD................................................. –0.3V to 6V Operating Junction Temperature Range (Note 2).............................................. –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10sec).................... 260°C UDD PACKAGE 24-LEAD (3mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 46°C/W, θJC = 5.0°C/W EXPOSED PAD (PIN 25) IS SGND, MUST BE SOLDERED TO PCB ORDER INFORMATION (http://www.linear.com/product/LTC3643#orderinfo) LEAD FREE FINISH TAPE AND REEL LTC3643EUDD#PBF LTC3643EUDD#TRPBF LTC3643IUDD#PBF LTC3643IUDD#TRPBF PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LGSX 24-Lead (3mm × 5mm) Plastic QFN –40°C to 125°C LGSX 24-Lead (3mm × 5mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 3643fb For more information www.linear.com/LTC3643 LTC3643 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C. VIN = 5V, VRUN = 2V unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP VIN Operating Voltage VIN CAP 3.0 IQ-IN Input Quiescent Current Active Mode Burst Mode® Shutdown Mode; RUN = 0V 800 400 10 RDS(ON) Switch A On Resistance Switch B On Resistance Switch C On Resistance VCAP >= VIN VINTVCC = 3.3V VBOOST = 8.3V 50 75 150 ISW Top Switch Leakage Bottom Switch Leakage VCAP = 40V, VSW = 0 VCAP = VSW = 40V 0.1 0.1 MAX UNITS 17 40 V V 800 20 µA µA µA mΩ mΩ mΩ 1 1 µA µA 40 V Boost Charger Regulation VCAP Cap Voltage VFBCAP Regulated Output Feedback Voltage IFBCAP FBCAP Input Current gm(EA) Error Amplifier Transconductance ILIM-BOOST Peak Inductor Current Limit (Bottom Switch Peak Limit) tOFF(MIN)-BOOST Minimum Off-Time fSW Switching Frequency l ITH = 1.2V l 0.594 0.6 0.606 V ±10 nA 210 270 330 µS 3.0 2.8 3.2 3.4 A A 70 ns 1 Input Current Limit Amplifier Regulated Voltage VCLP-VIN MHz l 48.5 46 50 50 51.5 54 mV mV l 0.594 0.6 0.606 V ±10 nA 2.6 3.2 3.7 4.5 4.7 5.6 A A A A A A Buck Regulator Voltage Regulation VFBSYS Regulated System Feedback Voltage IFBSYS FBSYS Input Current ILIM-BUCK Valley Inductor Current Limit (Bottom Switch Valley Limit) ILIM = FLOAT l 2.0 l 2.9 l 3.8 ILIM = 0V ILIM = VINTVCC tON(MIN)-BUCK Minimum On-Time 30 ns INTVCC Regulator INTVCC Regulated Voltage INTVCC UVLO INTVCC Rising 3.0 3.2 3.4 V 2.6 2.75 2.9 V 1.12 1.2 100 1.28 V mV 0 ±10 nA 1.0 1.1 1.05 1.15 V V 3 20 6 40 µs µs I/O Pins VRUN VPFI RUN High Rising RUN Hysteresis l RUN Input Current VRUN = 12V, VIN = 12V PFI Input Threshold Falling Rising (100mV hysteresis) PFI Delay Time Falling Rising l l 0.95 1.05 3643fb For more information www.linear.com/LTC3643 3 LTC3643 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C. VIN = 5V, VRUN = 2V unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS GATE Turn-on Time GATE Turn-off Time TYP MAX To CLP-GATE > 2.5V, CGATE = 1nF 70 100 µs To CLP-GATE < 1V, CGATE = 1nF 3 6 µs GATE Pull-Down Current UNITS 45 70 95 µA 550 570 15 590 mV mV CAPGD Resistance 170 250 Ω /PFO Resistance 170 250 Ω CAPGD Threshold l FBCAP Rising Hysteresis Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. The LTC3643 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3643E is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction 4 MIN temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3643I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. TJ is calculated from the ambient TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA) 3643fb For more information www.linear.com/LTC3643 LTC3643 TYPICAL PERFORMANCE CHARACTERISTICS Step-Up Charging Waveform PFO 5V/DIV IL 1A/DIV VCAP 20V/DIV CAPGD 2V/DIV IL 2A/DIV VCAP 10V/DIV VCAP 10V/DIV VLOAD 10V/DIV VIN 10V/DIV IL 1A/DIV VLOAD 10V/DIV VIN 10V/DIV 3643 G01 100ms/DIV 3643 G02 400ms/DIV Shutdown Current vs VIN VIN = 5V VCAP = 40V VLOAD = 5V, (SYSTEM LOAD) ILOAD = 100mA RDS(ON) vs Temperature 16 Frequency vs Temperature 300 14 2 250 12 RDSON (mΩ) 8 6 FREQUENCY (MHz) 1.5 10 200 TOP FET 150 BOTTOM FET 100 50 2 3 5 7 11 9 VIN (V) 13 15 17 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1000 900 800 700 VCAP RIPPLE 2V/DIV VOUT RIPPLE 200mV/DIV IL 1A/DIV IL 2A/DIV 7 11 9 VIN (V) 13 15 17 3643 G07 100 125 ILOAD (LOAD) 2A/DIV 400µs/DIV 5 50 25 0 75 TEMPERATURE (°C) Step-Down Regulator Transient Response ICAP 200mA/DIV 600 –25 3643 G06 Step-Up Regulator Transient Response Frequency vs VIN 3 0 –50 3643 G05 3643 G04 500 1 0.5 4 0 3643 G03 400ms/DIV VIN = 12V VCAP = 40V VLOAD = 5V ILOAD = 100mA VIN = 5V VCAP = 40V NO LOAD START-UP FROM RUN FREQUENCY (KHz) Step-Up to Step-Down Handoff Waveform Step-Down Discharge Waveform RUN 5V/DIV SHUTDOWN CURRENT (µA) TA = 25°C, unless otherwise noted. 3643 G08 VIN = 5V VCAP = 40V ICAP = 14mA TO 200mA L = 7.2µH COUT = 47µF 100µs/DIV 3643 G09 VCAP = 40V VLOAD = 5V L = 2.2µH ILOAD = 400mA TO 2.4A (SYSTEM LOAD) 3643fb For more information www.linear.com/LTC3643 5 LTC3643 TYPICAL PERFORMANCE CHARACTERISTICS Run Rising Threshold vs Temperature TA = 25°C, unless otherwise noted. Step-Up Regulator Light Load Switching Waveform Step-Down Regulator Light Load Switching Waveform 1.6 RUN RISING THRESHOLD (V) 1.5 1.4 1.3 1.2 1.1 1 SW 20V/DIV SW 20V/DIV IL 1A/DIV IL 2A/DIV VCAP RIPPLE 200mV/DIV VLOAD RIPPLE 100mV/DIV 3643 G11 10µs/DIV 0.9 0.8 –50 –25 25 75 50 0 TEMPERATURE (°C) 100 125 3643 G10 Quiescent Current vs Temperature 2µs/DIV VIN = 5V VCAP = 40V ILOAD (CAP) = 14mA CCAP = 40µF L = 7.2µH VCAP = 40V VLOAD = 5V VIN = 4.5V ILOAD (LOAD) = 110mA L = 2.2µH Charging Waveform with Programmed Current Limit Switch Leakage Current vs Temperature 1000 500 400 ACTIVE MODE IL 1A/DIV 600 300 SWITCH LEAKAGE (nA) IQ (µA) 800 ILOAD 2A/DIV SLEEP MODE 400 200 100 BOTTOM SWITCH 0 –100 TOP SWITCH –200 200 0 –50 –300 3643 G14 2ms/DIV –400 RSENSE = 10mΩ –25 50 25 0 75 TEMPERATURE (°C) 100 –500 –50 125 –25 50 25 0 75 TEMPERATURE (°C) 3643 G13 100 90 VIN = 5V 60 VIN = 12V 50 40 VCAP = 40V 30 60 50 40 30 20 10 10 0.1 0.01 CAP CURRENT (A) 1 VCAP = 24V 70 20 0 0.001 VCAP = 12V 80 EFFICIENCY (%) EFFICIENCY (%) 80 70 125 Step-Down Regulator Efficiency vs Load 100 90 100 3643 G15 Step-Up Regulator Efficiency vs Cap Current 0 0.001 3643 G16 6 3643 G12 VCAP = 40V VLOAD = 5V 0.1 1 0.01 LOAD CURRENT (A) 10 3643 G17 3643fb For more information www.linear.com/LTC3643 LTC3643 PIN FUNCTIONS PGND (Pins 1-2): Ground Pins for the Power Switch. CAP (Pin 3): Storage Capacitor Connection. This pin is the power input to the step-down regulator’s main switch (boost regulator’s synchronous switch) and connects directly to the backup energy storage capacitor. VIN (Pins 4-5): Input Supply of Boost Charger and Regulated Output Voltage of Step-Down Regulator. This input also powers the INTVCC LDO and input to the current regulation amplifier. GATE (Pin 6): Gate Driver for PowerPath Switch. This pin drives the gate of an external PMOS switch that connects the main power supply to the system load. This output swings from VIN to GND. RUN (Pin 7): Logic Controlled RUN Input. Do not leave this pin floating. Place a resistor divider from VIN to GND for an accurate VIN Undervoltage threshold. FBSYS (Pin 8): Feedback Input to Step-Down Regulator Control Loop. Connect a resistor divider tap to this pin. The VIN voltage can be adjusted such that VIN = 0.6V (1+R2/R1) (See Figure 4). FBCAP (Pin 9): Feedback Input to the Error Amplifier of the Cap Voltage Regulation Loop. Connect a resistor divider tap to this pin. The CAP voltage can be adjusted such that VCAP = 0.6V (1+R4/R3) (See Figure 5). ITH (Pin 10): Error Amplifier Output and Switching Regulator Compensation Point for the Boost Regulator. The current comparator’s trip threshold is linearly proportional to this voltage. The Buck Regulator’s compensation is set internally by the part. CAPGD (Pin 11): Capacitor Good Open Drain Status Output. This output is pulled down when the LTC3643 is charging the storage capacitor. It becomes high impedance when the output cap reaches 95% of the programmed charge voltage. PFO (Pin 12): Power Fail Open Drain Status Output. This pin pulls down when the main supply voltage is above the threshold set by the PFI pin. PFI (Pin 13): Power Fail Input. This pin sets the threshold at which the converter switches from boost charger mode to buck regulator mode. Connect with a resistor divider from the main power supply in order to switch to buck regulator mode when the supply voltage drops below a set threshold. INTVCC (Pin 14): Low Dropout Regulator. Bypass with a low ESR capacitor of at least 1µF to ground. BOOST (Pin 15): Boost Rail. Connect a 0.1µF capacitor between this pin and SW node to power the gate driver of the synchronous boost switch. INDIS (Pins 16-17): Input Disconnect Pin. The Internal power switch that allows for Output Disconnect feature is placed between the VIN and INDIS pins. SW (Pins 18-20): Switch Node Connection to the Power Regulator. ILIM (Pin 21): Buck Mode Peak Current Program Pin. Leave this pin floating for 3A current limit, ground it for 2A current limit, and tie it to INTVCC for 4A current limit during buck mode. CLP (Pin 24): Input to Current Regulation Amplifier. This pin is the inverting input to a current regulation amplifier that reduces the charging current when CLP rises more than 50mV above VIN. SGND (Exposed Pad Pin 25): Signal Ground Pin of the Regulator. Tie to PGND at a single point. Connect to PCB ground plane for rated thermal performance. 3643fb For more information www.linear.com/LTC3643 7 LTC3643 BLOCK DIAGRAM INDIS VIN TOP SWITCH (SWITCH C) SW BOOST CAP INPUT DISCONNECT SWITCH (SWITCH A) VIN RUN ON/OFF BOTTOM COMPARATOR CHARGE PUMP LDO + – PGND INTVCC INTVCC GATE (VIN – 6V) BOTTOM SWITCH (SWITCH B) CHARGE/BUCK ILIM GATE DRIVE PGND PGND PFI FBSYS 1.1V + – 0.6V + BUCK LOGIC BOOST LOGIC + ERROR AMPLIFIER ERROR AMPLIFIER – – 0.6V FBCAP ITH CAPGD 50mV PFO VIN STATUS ON-TIME/ OFF-TIME CALCULATOR CAP + – SENSE AMPLIFIER + – VIN CLP SGND 8 3643fb For more information www.linear.com/LTC3643 LTC3643 OPERATION The LTC3643 is a bidirectional regulator capable of delivering power from VIN to CAP (storage capacitor) as well as from CAP back to VIN, depending on the state of the PFI voltage. The duration for which power can be held up at VIN depends on the amount of system load, the size of the energy storage CAP, and the voltage at which the CAP node was charged to. When the PFI voltage is high, signifying that the power supply is good, power is delivered from VIN to CAP as illustrated in Figure 1. In this mode, LTC3643 operates as a peak current mode constant off-time boost regulator with input disconnect. In this mode, power can be directly delivered from the power supply to the system load, and be used to charge the energy storage element on CAP. The LTC3643 operates with pseudo-constant frequency, which is set solely by the on-time/off-time, which is internally calculated based on the VIN and CAP voltages and set to be 1MHz. Under light output load conditions, the LTC3643 operates in Burst Mode and skips pulses to minimize system power loss. As the output load current increases, the LTC3643 seamlessly transitions to continuous PWM switching to deliver output power. Though the LTC3643 can be configured to operate as a standalone boost regulator with input disconnect, it is primarily targeted at applications where a high voltage energy storage capacitor needs to be charged for the purposes of delivering power back to VIN to maintain system regulation in “dying gasp” situations when the system supply is removed. When the PFI Voltage is low, signifying that the power supply is below the necessary threshold, power delivery is reversed, it operates as a valley current mode constant on-time buck regulator, and delivers power from CAP to power VIN for as long as possible. The power path is illustrated in Figure 2. POWER SUPPLY CLP VIN INDIS SW SYSTEM LOAD BOOST CAP ENERGY STORAGE ON/OFF CHARGE PUMP INTVCC GATE GATEDRIVE 1.1V PFI + – CHARGE/BUCK BUCK LOGIC BOOST LOGIC 3643 F01 Figure 1. Power Path Block – Power Available from Power Source 3643fb For more information www.linear.com/LTC3643 9 LTC3643 OPERATION POWER SUPPLY CLP VIN INDIS SW SYSTEM LOAD BOOST CAP ENERGY STORAGE ON/OFF CHARGE PUMP INTVCC GATE GATEDRIVE 1.1V PFI + CHARGE/BUCK – BUCK LOGIC BOOST LOGIC 3643 F01 Figure 2. Power Path Block – Power Available from Energy Storage Element Boost Mode Control Loop When the PFI voltage is above 1.1V, the input power source is deemed to be good, and power will be delivered from VIN to CAP. If there is sufficient load on CAP or if the CAP voltage has yet to reach its final programmed value, the step-up regulator will switch continuously to deliver the necessary power. Under these circumstances, the bottom switch will turn on, thus ramping up the current in the inductor. Once that current reaches a certain level, which is set by the ITH voltage, the switch will turn off and allow the top (synchronous) switch to turn on. The top switch will remain on for a fixed duration (off-time) before shutting off to allow for the cycle to repeat. The off-time is calculated such that in steady state, the regulator will operate at a frequency around 1MHz. Thus, the off-time is equal to: V tOFF−BOOST = 1µs • IN VCAP 10 The boost mode control loop is compensated through the external ITH pin, and the method of compensating the loop will be discussed in more detail in the applications information section. Boost Mode Low Current Operation Once the CAP voltage has reached its programmed voltage, and the load is minimal, the LTC3643 will automatically transition from continuous mode operation to Burst Mode operation. In this mode, the ITH voltage will transition above and below the sleep threshold depending on the CAP voltage. If the CAP voltage decreases slightly below its regulation point, the regulator will wake up from sleep, and the bottom switch will turn on until the inductor current reaches the burst current clamp of 800mA. Once that value is reached, the bottom switch turns off and the top switch turns on for a fixed duration, tOFF-BOOST. This switching cycle will repeat until the CAP has replenished enough to force the ITH voltage below the sleep threshold. Once that happens, both switches are turned off and the quiescent current is decreased to 400µA. 3643fb For more information www.linear.com/LTC3643 LTC3643 OPERATION Boost Mode Startup The LTC3643 will begin to operate if the RUN voltage is raised above 1.2V and VIN is greater than 3V. In order to prevent conduction from the VIN to CAP through the body diode of the top switch, an input disconnect switch is placed between VIN and INDIS. The body diode of the disconnect switch and that of the top switch are opposite in polarity in order to prevent conduction of current when CAP is less than VIN. The gate of the disconnect switch remains grounded until the regulator begins to operate. Once started, an internal charge pump will slowly charge up the gate of the disconnect switch and regulate that gate voltage such that only 100mA of current is flowing through the switch. That 100mA will thus conduct through the inductor between INDIS and SW, and the body diode of the top switch to charge up the capacitor at the CAP node. The 100mA limit is set as a way to limit the power dissipation through the disconnect switch and the top switch, and protect those switches from overheating. During this period, the voltage at INDIS and SW will be clamped at a diode above CAP. Once the INDIS voltage approaches VIN, and it is sensed that the internal disconnect switch is fully enhanced, an internal signal is issued to allow the top and bottom switches to operate as needed to charge the CAP voltage up to its programmed value. Boost Output Over-Current/Short Operation The current through the disconnect switch is constantly being monitored to resolve overcurrent situations. Once the switch is fully enhanced, if the current through the disconnect switch ever exceeds 4.8A, a signal is sent to the control circuitry to keep the top switch on indefinitely until that current level subsides. During an output short situation, if the CAP voltage were to ever collapse below the VIN voltage, then simply leaving the top switch on to discharge the inductor current would not work. In these situations, if the current through the disconnect switch ever exceeds 8A, the gate of the disconnect switch is immediately pulled down, thus effectively shutting off the disconnect switch. At the same time, both the top and bottom switches are shut off. The current in the inductor will then conduct through the body diode of the top switch and decrease down to 0A. From there, the internal charge pump will slowly charge back up the gate of the disconnect switch and regulate the current through the switch to 100mA, much like the case in startup. Buck Mode Control Loop If the PFI voltage falls below 1.15V, power will be delivered from CAP to VIN. If the system load at VIN is high enough, the regulator will switch continuously. In a typical cycle, the top switch is turned on for a fixed duration (on-time). Once that duration expires, the top switch turns off and the bottom switch is turned on; inductor current is allowed to discharge until a valley current level is reached, at a threshold set by an internally compensated ITH voltage. Once that current level is reached, the bottom switch turns off and the top switch turns back on again and the cycle repeats. The on-time is once again calculated such that in steady state, the regulator will operate at a frequency around 1MHz. Thus, the on-time is equal to: V tON−BUCK = 1µs • IN VCAP The buck mode control loop is compensated by an internal RC network and the external ITH pin is grounded through an internal switch. Buck Mode Low Current Operation When VIN reaches the programmed regulation voltage and a minimal load is present, the regulator will automatically transition into Burst Mode operation. In this mode, the ITH voltage will transition above and below the sleep threshold depending on the VIN voltage. If the VIN voltage decreases slightly below its regulation point, the regulator will wake up from sleep, and the top switch will turn on for a fixed duration, tON-BUCK. Then, the top switch will turn off and the bottom switch will turn on until the inductor current reaches 0A. This switching cycle will repeat until the VIN voltage has replenished enough to force the ITH voltage below the sleep threshold. Once that happens, both switches are turned off and the quiescent current is decreased to 400µA. 3643fb For more information www.linear.com/LTC3643 11 LTC3643 OPERATION Buck Mode End of Charge Operation The energy reservoir on CAP will continue to supply energy to keep VIN at the regulation point for as long as possible. However, at some point, if the system load at VIN continues to be present, the CAP voltage will drop low enough such that the VIN regulation voltage can no longer be maintained due to minimum off-time restrictions. The minimum off-time restriction is present because during every cycle, the bottom switch needs to turn on. Once such a condition is reached, the VIN voltage will regulate to roughly 93% of the CAP voltage. The switching regulator will continue to operate in such a manner until either the RUN voltage falls below 1.1V or the VIN voltage falls below what is necessary for the regulator to operate (typically 2.8V). When either of those situations is reached, both the top and bottom switches are turned off, and the gate of the disconnect switch is pulled low. Boost/Buck Switchover Operation The LTC3643 transitions between boost and buck modes of operation depending on the PFI voltage. If the PFI voltage goes above 1.2V, it is deemed that power at the input supply is good and the boost phase is engaged. If the PFI voltage falls below 1.15V, it is deemed that the input supply is no longer high enough to supply the system load, and buck phase is engaged. The PFO pin is an indicator pin that will display if there is an input power fail. Connect a pull-up resistor from that pin to a known rail (<6V). A high on that pin indicates the input supply is insufficient. The transition from boost to buck mode is relatively fast (~2µs) in order to prevent the voltage on VIN to deplete too much before the buck regulator engages, whereas the transition from buck to boost is somewhat slower (~20µs). This time delay, combined with the 50mV hysteresis on the PFI threshold voltage, helps eliminate momentary glitches on the PFI pin, and prevents unnecessary mode transitions. current into the depleted power supply. Placing a Schottky between the power supply and CLP will achieve that result, but would result in significant power dissipation through the diode when the power supply is present at high load. To mitigate this power loss, an external power PMOS device with low RDSON can be used in place of the Schottky with its gate connected to the GATE pin of the LTC3643. When the application transitions from boost mode to buck mode, the GATE voltage will instantaneously get pulled up to VIN, thus shutting off the external PMOS. When the power supply becomes ready again, the GATE voltage will get pulled low slowly with a 70µA current source, and that voltage will be internally clamped to go no lower than 6V below VIN. Boost Mode Current Limiting If the power supply is current limited, the LTC3643 has the capability of limiting the input current of the boost regulator to ensure that the cumulative current of the boost regulator and the system load does not exceed a programmed amount. That current limit is programmed by the sense resistor between the CLP and VIN pins. In the application example of figure 3, a 10mΩ resistor is placed between CLP and VIN. The voltages across those pins are designed to not exceed 50mV. Thus, a cumulative 5A is allowed to flow through the boost regulator (I1) and the system load (I2). If I2 in the application is 4A, then a maximum of 1A of current can flow through the boost regulator. If I2 is minimal, then I1 will be limited by the maximum current of the boost regulator. Furthermore, if I2 exceeds the 5A limit, the ITH voltage of the regulator will get pulled low and the part will enter its sleep mode. POWER SUPPLY CLP GATE Gate Control for External PMOS Switch Often times, when the VIN voltage falls below the PFI threshold and buck mode is engaged, it is required to have a blocking element present to prevent back conduction of 12 I2 10mΩ VIN I1 INDIS SW BOOST SYSTEM LOAD CAP LTC3643 3643 F03 Figure 3. PowerPath of Boost Regulator with CLP Programmability 3643fb For more information www.linear.com/LTC3643 LTC3643 OPERATION INTVCC Regulator Output Voltage Programming The LTC3643 has an onboard Low Dropout Regulator powered from VIN, and the INTVCC voltage is regulated to 3.3V. The power dissipated across this LDO would thus be equal to (VIN – 3.3V) • IINTVCC. For a typical application, if the regulator is running in continuous mode, the current draw from the INTVCC by the chip is roughly 10mA. The step down converter output VIN and the step-up charger output VCAP are set by an external resistive divider according to the following equations: VIN Undervoltage Programming ⎛ R4 ⎞ VCAP = 0.6V ⎜ 1+ ⎟ ⎝ R3 ⎠ The LTC3643 offers an accurate RUN threshold to start the regulator. As a result, a resistor divider from VIN to GND can be placed with the intermediate node fed back to RUN to set an accurate VIN Undervoltage threshold. As the input voltage rises, the RUN voltage will increase above the VRUN rising threshold (1.2V), and the regulator will turn on. Similarly, once on, if the input voltage decreases below the VRUN falling threshold (1.1V), the regulator will turn off. ⎛ R2 ⎞ VIN = 0.6V ⎜ 1+ ⎟ ⎝ R1⎠ To improve the frequency response, a feedforward capacitor CFF may also be used. Great care should be taken to route the FBSYS or FBCAP line away from noise sources, such as the inductor or the SW trace. VIN R2 VCAP CFF R4 FBSYS LTC3643 CFF FBCAP LTC3643 R1 SGND R3 SGND 3643 F04 3643 F05 Figure 4. Setting The VIN Voltage In Step-Down Mode Figure 5. Setting The VCAP Voltage In Step-Up Mode 3643fb For more information www.linear.com/LTC3643 13 LTC3643 APPLICATIONS INFORMATION Input Capacitor (CIN) Selection If the LTC3643 is only used in the boost direction, then the input filter capacitor is only required to reduce peak currents drawn from the input source and reduce input switching noise. A low ESR bypass capacitor with a value of at least 4.7µF should be located as close to the VIN pin as possible. However, in applications where buck mode is engaged, more bypass capacitance is required. The selection of CIN is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response. The Input ripple, ΔVIN, is determined by: ⎛ ⎞ 1 ΔVIN < ΔIL ⎜ +ESR⎟ ⎝ 8 • f •CIN ⎠ The output ripple is highest at maximum input voltage since ΔI L increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. Special polymer capacitors are very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. Ceramic capacitors have excellent low ESR characteristics and small footprints. Using Ceramic VIN and CAP Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and 14 the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the VCAP input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VCAP large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R and X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. In both the buck mode and boost mode cases, during a load step, the VIN and CAP capacitor respectively must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. Typically in buck mode, ~5 cycles are required to respond to a load step but only in the first cycle does the VIN voltage drop linearly. The VIN voltage droop, VDROOP, is usually about 3 times the linear drop of the first cycle. Thus, a good place to start with the VIN capacitor value is approximately: ΔIIN CIN = 3 f 0 • VDROOP The boost mode response is typically much slower than that of the buck and has a dependency on the duty cycle of the application. Typically, the loop response will be at least 3 times slower than that of the buck. Thus, more ceramic capacitance at CAP may be required. However, in most applications, the LTC3643 will be used to charge a bulk capacitor in which case placing the 22µF ceramic capacitor in parallel to the bulk capacitor just to filter out the square wave current is sufficient. Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency (1MHz) determine the ripple current: ΔIL = VIN ⎛ VIN ⎞ 1– ⎜ ⎟ VCAP(MAX) ⎠ 106 • L ⎝ 3643fb For more information www.linear.com/LTC3643 LTC3643 APPLICATIONS INFORMATION Lower ripple current reduces core losses in the inductor and reduces VIN voltage ripple. However, at extremes, low ripple causes inductor current sensing issues. Highest efficiency operation is obtained at low frequency with reasonably small ripple current. However, achieving this requires a large inductor. There is a trade-off between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 50% of IOUT(MAX). To guarantee that ripple current does not exceed specified inductor saturation current ratings, the inductance should be chosen according to: Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Toko, Vishay, NEC/Tokin, Cooper, TDK and Würth Electronik. Refer to Table 1 for more details. Boost Mode Transient Response ⎛ ⎞ VIN ⎜1– ⎟ L= 6 10 • ΔIL(MAX) ⎜⎝ VCAP(MAX) ⎟⎠ VIN Once the value for L is known, the type of inductor must be selected. Core loss is very dependent on the material, frequency and inductance selected. Higher inductance reduces ripple. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite materials have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! The LTC3643 in boost mode uses peak current mode control compensated with an RC network on the external ITH pin. The ITH external component network shown in Figure 6 will provide an adequate starting point for most applications. The RC filter sets the dominant pole-zero loop compensation. The values can be modified to optimize transient response once the PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Table 1. Inductor Selection Table Vendor P/N L (µH) I (A) L (mm) W (mm) H (mm) Coilcraft XAL5030(50)-XXX 0.16-22 31-3.6 5.28 5.48 3.1-5.1 Coilcraft XAL6030(60)-XXX 0.18-22 39-5.6 6.36 6.56 3.1-6.1 SUMIDA CDEP1Ø5NP-XXX 0.15-8.8 55-4 10 10 5.6 SUMIDA CEP125NP-XXX 0.8-10 35-5 12.9 12.9 5.6 Wurth Elekt. 744393580XX 1-10 17-5.8 8.3 8.8 7.8 Wurth Elekt. 7440280000XX 0.056-6.8 6-0.55 2.8 2.8 1.1 Coiltronics DR73-XXX-R 0.33-1000 14.4-0.25 6.0 7.6 3.55 3643fb For more information www.linear.com/LTC3643 15 LTC3643 APPLICATIONS INFORMATION POWER SUPPLY (5V) C2 0.1µF L1 4.7µH CLP VIN INDIS SW 47µF BOOST GATE CAP LTC3643 ITH CITH2 2.2pF SYSTEM LOAD FBCAP RITH 402k CITH1 470pF SGND PGND 3643 F06 40V RFB1 392k COUT 47µF ROUT RFB2 6.04k Figure 6. 5V to 40V Boost Application Figure 7 shows a simplified block diagram for the application in Figure 6, and can be used to analyze the stability of the application with the given compensation components. 0.6V + – AEA ERROR AMPLIFIER VITH GMP IOUT POWER STAGE TRANSCONDUCTANCE AMPLIFIER ZOUT VOUT OUTPUT IMPEDANCE AFB A = η• VIN A / A MP VCAP Where η is the efficiency of the regulator. Assuming a 90% efficiency and a 5V in to 40V out application: 3643 F07 FEEDBACK GAIN Figure 7. Block Diagram of the Boost Regulator AEA signifies the voltage gain of the internal error amplifier. It translates a difference of FB input error to the output ITH voltage. The gm of the error amplifier, gm(EA), is fixed to the regulator and is typically 210µmho. With the compensation network on ITH, for frequencies above the error amplifier zero, Z1, the gain is roughly AEA(FLATBAND). 1 Z1 = = 0.85kHz 2π •R •C ITH ITH1 AEA(FLATBAND) = gm(EA)•RITH1 = 82.8V / V CITH2 is used purely to filter out high frequency signals and as long as it is sized significantly smaller than CITH1, it should not affect the loop stability of the regulator. 16 GMP is the transconductance gain from VITH to IOUT. Because of the architecture of the regulator, the gain from VITH to IL (inductor current) is fixed internally to be 3mmho. Furthermore, the DC gain from IL to IOUT is equal to AMP: AMP = 0.1125 A/A The AC component of the Gmp can be mainly attributed to the RHP zero of the boost regulator, Z2: Z2 = VIN2 2π •POUT(MAX) •L1 Hz Since POUT(MAX) = VIN • IL(MAX) • η, Z2 = VIN = 94kHz 2π • η•IL(MAX) •L1 The total loop must be compensated such that the crossover frequency is at least 10× slower than that of Z2. ZOUT is the output impedance of the application. It has a DC gain of ROUT and a pole at P1: 1 P1 = Hz 2π •ROUT •COUT 3643fb For more information www.linear.com/LTC3643 LTC3643 APPLICATIONS INFORMATION As a result, the load pole has a unity gain impedance at: 1 = 6.8kHz 2π •COUT The last component of the loop is AFB, which is the gain from VOUT to VFB, and in this application, it is simply 0.015 V/V. For a rough estimation of the crossover frequency of the entire loop, analysis can be done at frequency Z1. At that frequency: AEA ≈ AEA(FLATBAND) = 82.8V / V GMP ≈ 3 • AMP = 0.33Ω ZOUT ≈ equal to the ∆ILOAD • ESR, where ESR is the effective series resistance of CIN. ∆ILOAD also begins to charge or discharge CIN generating a feedback error signal used by the regulator to return VIN to its steady-state value. During this recovery time, VIN can be monitored for overshoot or ringing that would indicate a stability problem. The compensation for the buck mode of the LTC3643 is implemented internal to the IC. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. PZ = 8Ω Z1 AFB = 0.015V / V The total loop gain at Z1 is thus equal to the product of all the components which is 3.27V/V. In addition, at that frequency, since the zero frequency of the error amplifier has already been reached, the system looks like a single pole system, thus making the crossover frequency roughly: 3.27 • Z1 = 2.8kHz. For applications where a large energy reservoir capacitor is placed in parallel to the COUT, the ZOUT component of the block diagram needs to be remodeled, but often times, the zero frequency of the ESR of the large capacitor and its capacitance is well below the crossover frequency of the loop, and can be ignored in analyzing the stability of the loop. Buck Mode Transient Response The buck mode transient response can be checked by looking at the load response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VIN immediately shifts by an amount In some applications, a more severe transient can be caused by switching in loads with large (>1µF) input capacitors. The discharged input capacitors are effectively put in parallel with CIN, causing a rapid drop in VIN. No regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot Swap controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection and soft-starting. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% – (L1 + L2 + L3 +…) 3643fb For more information www.linear.com/LTC3643 17 LTC3643 APPLICATIONS INFORMATION where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC3643 circuits: 1) I2R losses, 2) switching and biasing losses, and 3) other losses. 1.I2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average input current flows through inductor L and front end disconnect switch but is “chopped” between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(1-DC) + (RDS(ON)BOT) (DC) + RDS(ON)BLKFET The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R losses: I2R losses = IL2(RSW + RL) 2.The switching current is the sum of the MOSFET driver and control currents. The power MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC control bias current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the internal top and bottom power MOSFETs and f is the switching frequency. The power loss is thus: switch quickly enough that these losses are not significant compared to other sources. Other losses including diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss. Thermal Conditions In a majority of applications, the LTC3643 does not dissipate much heat due to its high efficiency and low thermal resistance of its exposed-back QFN package. However, in applications where the LTC3643 is running at high ambient temperature, high VIN, and maximum output load current, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 160°C, both power switches will be turned off until the temperature drops about 15°C cooler. To avoid the LTC3643 from exceeding the maximum junction temperature, some thermal analysis must be done. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: tRISE = PD • θJA As an example, consider the case when the LTC3643 is used in applications where VIN = 5V, IL = 2A, and VCAP = 40V. The equivalent power MOSFET resistance RSW is: RSW = RDS(ON)TOP • +R DS(ON)BLKFET = 150mΩ • Switching Loss = IGATECHG • VIN 3.Other “hidden” losses such as transition loss and copper trace and internal load resistances can account for additional efficiency degradations in the overall power system. It is very important to include these “system” level losses in the design of a system. Transition loss arises from the brief amount of time the top power MOSFET spends in the saturated region during switch node transitions. The LTC3643 internal power devices 18 ⎛ VIN V ⎞ +RDS(ON)BOT • ⎜ 1– IN ⎟ VCAP ⎝ VCAP ⎠ 5V 5V ⎞ ⎛ + 75mΩ • ⎜ 1– + 50mΩ ⎝ 40V ⎟⎠ 40V = 134mΩ Typically, the current drawn from INTVCC will be 10mA. Therefore, the total power dissipated by the part is: PD =IOUT 2 •RSW + VIN •IINTVCC = 4A 2 •134mΩ + 5V •10mA = 587.5mW 3643fb For more information www.linear.com/LTC3643 LTC3643 APPLICATIONS INFORMATION The QFN package junction-to-ambient thermal resistance, θJA, is around 46°C/W. Therefore, the junction temperature of the regulator operating in a 25°C ambient temperature is approximately: TJ = 0.587W • 46°C/W + 25°C = 52°C Remembering that the above junction temperature is obtained from an RDS(ON) at 25°C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. Redoing the calculation assuming that RSW increased 10% at 52°C yields a new junction temperature of 54.4°C. If the application calls for a higher ambient temperature and/or higher switching frequency, care should be taken to reduce the temperature rise of the part by using a heat sink or air flow. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3643. Check the following in your layout: 1.Do the capacitors CCAP connect to the CAP and GND terminals as close as possible? 2.Are CIN and L closely connected? The (–) plate of CIN returns current to GND and the (–) plate of CCAP. 3.Solder the Exposed Pad (Pin 25) on the bottom of the package to the GND plane. Connect this GND plane to other layers with thermal vias to help dissipate heat from the LTC3643. 4.Keep sensitive components away from the SW pin. The compensation components CITH and RITH, all resistor dividers, and the INTVCC bypass caps should be routed away from the SW trace and the inductor. 5.A ground plane is required. 6.Flood all unused areas on all layers with copper, which reduces the temperature rise of power components. These copper areas should be connected to GND. Holdup Time Calculation The amount of energy available in the energy reservoir capacitor before the voltage droops below the desired backup voltage is equal to: ( 1 ECAP = CCAP VCAP 2 – VIN2 2 ) The amount of energy necessary to complete the backup is equal to: ELOAD = ISYS • VIN • tHT Where tHT is the amount of backup time needed. Assuming an efficiency of η (this number will vary depending on the application), the total amount of backup time will be equal to: 2 2 ECAP • η CCAP VCAP – VIN • η tHT = = ISYS • VIN 2 •ISYS • VIN ( ) Where ISYS is the system load during backup. Design Example As a design example, consider the LTC3643 in an application with the following specifications: VIN = 4V to 8V VCAP = 40V ICAP (Input) = 2A Given the internally programmed switching frequency of 1MHz, we can calculate the inductor value for about 40% ripple current (800mA based on an average of 2A output current) at maximum VIN: 8V 8V ⎞ ⎛ ⎞⎛ L=⎜ 1− = 8µH ⎝ 1MHz • 0.8A ⎟⎠ ⎜⎝ 40V ⎟⎠ Given this, an 8.2µH inductor would suffice. CCAP and CIN will be selected based on what is required to satisfy the output voltage ripple requirement for the boost and buck modes respectively. A 22µF or 47µF capacitor on both nodes is adequate for most applications. 3643fb For more information www.linear.com/LTC3643 19 LTC3643 APPLICATIONS INFORMATION CCAP Size Selection for System Backup Power Applications This section of the data sheet will discuss how large to size the CAP capacitor, CCAP, to insure that there is sufficient energy to hold up the Input supply when power is removed. Consider the design example where: VIN = 5V VCAP = 40V Holdup Time (tHT) = 10msec System Current Load (ISYS) = 2A The total Energy required during holdup time is equal to: EDISS = VIN • ISYS • tHT = 100mW-sec ( CAP Capacitor (CCAP) Selection When selecting CAP capacitors, the magnitude of the peak inductor current, together with the ripple voltage specifications, determine the choice of the capacitor. Both the ESR (equivalent series resistance) of the capacitor and the charge stored in the capacitor each cycle contribute to the output voltage ripple. The ripple due to the charge is approximately: Total energy available is equal to: E AVAL = is recommended to be at least 30% larger than required. In this particular case, four 47µF capacitors (188µF total) would be recommended. VRIPPLE(CHARGE) ≅ IP • VIN CCAP • VCAP • f where IP is the peak inductor current. ) CCAP VCAP 2 – VIN2 = 787.5 •CCAP (W-sec) 2 Since the regulator is not lossless, the efficiency needs to be taken into consideration, such that: The ESR of the CCAP is usually the most dominant factor for ripple in most power converters. The ripple due to the capacitor ESR is: VRIPPLE(ESR) =ILOAD •RESR • VOUT VIN EAVAL • eff > EDISS EDISS CCAP = eff •E where RESR is equal to the capacitor ESR. AVAL Assuming an efficiency of 90%, with 100mW-sec required by the system, CCAP needs to be at least 141µF. In applications where a large energy storage capacitor is used, a smaller ceramic bypass capacitor is still required close to the regulator due to its low ESR. Typically, a 22µF ceramic capacitor is sufficient for most applications. To be conservative, and to account for some voltage coefficient and tolerance of the capacitors, the capacitor 20 3643fb For more information www.linear.com/LTC3643 VIN 5V-60V 0.1µF 37.4k 22µF 2.2µF 4.7nF 15k + For more information www.linear.com/LTC3643 INTVCC VFB BG SW TG BOOST ILIM SENSE+ SENSE– MODE/PLL PGND SGND SGND ITH RUN TK/SS PGOOD FREQ LTC3891 EXTVCC VIN SIR826ADP SIR826ADP 0.1µF 2.2µF 6.8µH XAL7070-682 220µF VOUT = 5V 137k 511k 5.11k 1M 37.4k 511k 511k 0.01Ω 5V Backup System with VIN From 5V to 60V + 61.9k 324k 3mΩ 20pF 4.7µF SI4491 SGND PGND RUN PFO CAPGD PFI GATE FBSYS ILIM INTVCC ITH FBCAP CAP BOOST SW SW INDIS IN CLP INDIS IN LTC3643 4.7µF 3643 TA02 0.1µF 7.2µH + SYSTEM LOAD 5.11k 322k 2× 4.7µF 40V BACKUP 22pF 47µF *PANASONIC EEEFK1H102AM 470pF 402k 10µF 1000µF* +2× LTC3643 TYPICAL APPLICATIONS 3643fb 21 22 VIN 5V-36V + 47µF 2.2µF 7.15k 0.1µF 5.1V 100k PGND VFB SS FCB RUN VIN SGND SENSE– RSENSE SENSE+ SW2 SW1 VOUT LTM4607 180µF 2.2µF 511k SI4491 For more information www.linear.com/LTC3643 1M 5.11k 97.6k 511k 511k 0.01Ω SGND PGND RUN PFO CAPGD PFI GATE FBSYS ILIM INTVCC ITH FBCAP CAP BOOST SW SW INDIS IN CLP INDIS IN LTC3643 12V Backup System for Automotive Applications **TOKO FDA1254-4R7 56.2k 0.008Ω 10µH** + VOUT 12V 4.7µF 3643 TA03 0.1µF + 470pF 402k 15µH XAL5050-153M 22µF SYSTEM LOAD 2× 4.7µF 1000µF* + 2× *PANASONIC EEEFK1H102AM 5.11k 322k 40V BACKUP 22pF 180µF LTC3643 TYPICAL APPLICATIONS 3643fb LTC3643 TYPICAL APPLICATIONS Temporary Supply Booster 5V SOURCE 0.1Ω 100mΩ CABLE/TRACE RESISTANCE 22µF CLP VIN INDIS RUN BOOST BACKUP SUPPLY 40V ILIM CAPGD PFO SW SYSTEM LOAD 4A 0A CAP GATE 44.2k 47µF x2 0.1µF 7.2µH 22µF 1mF INTV CC 4.7µF LTC3643 FBSYS 392k FBCAP 6.04k 6.04k ITH 402k PFI GND 22pF 470pF NOTE: DRIVE PFI PIN HIGH WHEN HIGH LOAD IS PRESENT TO MAINTAIN DESIRED VOLTAGE AT THE SYSTEM LOAD 3643fb For more information www.linear.com/LTC3643 23 LTC3643 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC3643#packaging for the most recent package drawings. UDD Package 24-Lead Plastic QFN (3mm × 5mm) (Reference LTC DWG # 05-08-1833 Rev Ø) 0.70 ±0.05 3.50 ±0.05 2.10 ±0.05 3.65 ±0.05 1.50 REF 1.65 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.50 REF 4.10 ±0.05 5.50 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 ±0.10 0.75 ±0.05 1.50 REF 23 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER 24 0.40 ±0.10 PIN 1 TOP MARK (NOTE 6) 5.00 ±0.10 1 2 3.65 ±0.10 3.50 REF 1.65 ±0.10 (UDD24) QFN 0808 REV Ø 0.200 REF 0.00 – 0.05 R = 0.115 TYP 0.25 ±0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 24 3643fb For more information www.linear.com/LTC3643 LTC3643 REVISION HISTORY REV DATE DESCRIPTION A 12/15 Changed Typical Application graph PAGE NUMBER 1 B 02/16 Updated ILIM pin description wording 7 Updated voltage from 1.2V to 1.1V on PFI comparator of Figure 1 9 Updated voltage from 1.2V to 1.1V on PFI comparator of Figure 2 10 3643fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its information circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC3643 25 LTC3643 TYPICAL APPLICATION 40V Synchronous Boost Regulator with Input Disconnect VIN 3V TO 17V 7.2µH 22µF CLP VIN INDIS GATE 0.1µF SW BOOST INTVCC RUN VOUT 40V CAP PFI LTC3643 392k FBCAP FBSYS 6.04k ITH CAPGD PFO 47µF 4.7µF 108k GND 47pF 3.3nF 3643 TA04 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3110 2A Bi-Directional Buck-Boost DC/DC Regulator and Charger/Balancer VCAP Range: 0.1V to 5.5V VSYS Range 1.71V to 5.25V, Automatic Switchover from Charge to Backup Mode. 24-Lead TSSOP and 4mm × 4mm QFN Packages. LTC3128 3A Monolithic Buck-Boost Supercapacitor Charger and Balancer with Accurate Input Current Limit ±2% Accurate Average Input Current Limit Programmable to 3A, Active Charge Balancing, Charges 1 or 2 Capacitors, VIN Range: 1.73V to 5.5V, VOUT Range: 1.8V to 5.5V, 20-Lead 4mm × 5mm QFN and 24-Lead TSSOP Packages LTC3226 2-Cell Supercapacitor Charger with Backup PowerPath Controller 1x/2x Multimode Charge Pump Supercapacitor Charger, Automatic Cell Balancing, PowerPath, 2A LDO Backup Supply, Automatic Main/Backup Switchover, 2.5V to 5.5V, 16-Lead 3mm × 3mm QFN Package LTC3350 High Current Supercapacitor Backup Controller and System Monitor High Efficiency Charging of 1 to 4 Series Supercapacitors. Step-Up Mode in Backup, System Health Monitoring. 38-Lead 5mm × 7mm QFN Package. LTC3355 20V, 1A Buck DC/DC with Integrated SCAP Charger and Backup Regulator VIN: 3V to 20V, VOUT: 2.7V to 5V, 1A Main Buck Regulator, 5A Boost Backup Regulator Powered from Single Supercapacitor, Overvoltage Protection. 20-Lead 4mm × 4mm QFN Package LTC3625 1A High Efficiency 2-Cell Supercapacitor Charger with Automatic Cell Balancing High Efficiency Step-Up/Step-Down Charging of Two Series Supercapacitors. Automatic Cell Balancing. Programmable Charging Current to 500mA (Single Inductor), 1A (Dual Inductor). 12-Lead 3mm × 4mm DFN Package LTC4425 Linear SuperCap Charger with Current-Limited Ideal Diode and V/I Monitor Constant-Current/Constant-Voltage Linear Charger for 2-Cell Series Supercapacitor Stack. VIN: Li-Ion/Polymer Battery, a USB Port, or a 2.7V to 5.5V Current-Limited Supply. 2A Charge Current, Automatic Cell Balancing, Shutdown Current <2μA. 12-Pin 3mm × 3mm DFN or 12-Lead MSOP Package LTC4040 2.5A Battery Backup Power Manager VIN: 3.5V to 55V Contains a High Current Step-Up DC/DC Regulator to Back-Up the Supply from A Single Cell Li-Ion LiFePO4 Battery, 24-Lead 4mm × 5mm QFN Package 26 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC3643 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3643 3643fb LT 0216 REV B • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2015