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PT4302
Ultra-Low Power OOK/ASK Receiver
DESCRIPTION
FEATURES
The PT4302 is an ultra-low power OOK/ASK super
heterodyne receiver for the 315/433.92 MHz frequency
bands. It offers a high level of integration and requires
only few external components. The PT4302 consists of
a low-noise amplifier (LNA), a down-conversion mixer,
an on-chip phase-locked loop (PLL) with integrated
voltage-controlled oscillator (VCO) and loop filter, an
OOK/ASK demodulator, a data filter, a data slicing
comparator and an on-chip regulator. The PT4302
also implements a discrete one-step automatic gain
control (AGC) that reduces the LNA gain when the RF
input signal is greater than –68 dBm. The AGC
circuitry can extend the dynamic range of received RF
signal.
• Ultra-low power consumption: 2.7 mA for full
operation (315 MHz)
• Few external components
• Excellent sensitivity of the order of –111 dBm
(peak ASK signal level)
• 2.4 V to 5.5 V supply voltage range
• 250 MHz to 500 MHz frequency range
• Data rate up to 10 Kb/s
APPLICATIONS
•
•
•
•
The PT4302 is available in a 16-pin SSOP package
and is specified over the extended temperature range
(–40 to +85°C).
Automotive remote keyless entry (RKE)
Remote control
Garage door and gate openers
Suitable for applications that meet either the
European ETSI-300-220 or the North American
FCC (Part 15) regulatory standards
BLOCK DIAGRAM
REFOSC
VLO
CTH
DO
CE
SELA
SELB
VSSBB
16
15
14
13
12
11
10
9
Control Logic
Reference
Oscillator
Comparator
OOK/ASK
Demodulator
RTH
Data Filter
(LPF)
PLL
AGC
LNA
On-Chip
Regulator
Buffer
Amplifier
Mixer
1
2
3
4
5
6
7
8
VSSLO
VSSRF
ANT
VRF
MIXOUT
VBB
IFIN
VDD5
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT4302
433.92 MHZ RKE EXAMPLE
10.7 MHz
V1.2
2
October 2012
PT4302
APPLICATION CIRCUIT
BILL OF MATERIALS
Part
Value
Unit
Description
315 MHz
433.92 MHz
L1
82 n
47 n
H
L2
39 n
27 n
H
C1
1.8 p
1.0 p
F
Antenna input matching, coil inductor
Antenna ESD protection, coil inductor
(optional)
Antenna input matching
C2, C3, C4
100 n
100 n
F
Power supply de-coupling capacitor
C5
470 n
470 n
F
C6
220 p
220 p
F
R1
10
10
Ω
CTH (affects coding type and start-up time)
Depends on crystal oscillator vendor, for
frequency fine tuning
Power supply de-coupling resistor (optional)
R2, R3, R4, R5
10 K
10 K
Ω
MCU interface resistor (optional)
R6
8.2 M
8.2 M
Ω
For reducing data output noise (optional)
F1
10.7
10.7
MHz
Band-pass filter
X1
9.509
13.226
MHz
Reference crystal oscillator
U1
PT4302 IC
PT4302 IC
U1
Receiver chip
Notes:
1. L1 and C1 are the components for input matching network. They may have to be adjusted with different PCB layout and antenna requirement.
2. The value of C5 depends upon the data rate and coding pattern.
3. F1 is the 10.7 MHz ceramic filter. The recommended part number is Murata SFELA10M7HA00-B0.
4. The “optional” components are based on application requirements.
V1.2
3
October 2012
PT4302
O
ORDER
R INFORMATION
Valid Part Number
PT430
02-X
Package Typ
pe
16 Pins,
P
SSOP, 150 mil
Top Code
C
PT43
302-X
P
PIN
CO
ONFIGU
URATIO
ON
P
PIN
DES
SCRIP
PTION
Pin Name
P
VSSLO
VSSRF
ANT
VRF
MIXOUT
VBB
IFIN
VDD5
VSSBB
SELB
SELA
CE
DO
CTH
VLO
R
REFOSC
V1.2
I/O
G
G
I
P
O
P
I
P
G
I
I
I
O
I/O
P
I
Desc
cription
Ground for LO portion
Ground for RF
R portion
RF input connection to antenna by a matching
m
netw
work
Supply voltag
ge for RF porrtion
Mixer IF outp
put
Supply voltag
ge for baseba
and chain
IF stage inpu
ut
5 V supply vo
oltage input
Ground for baseband chain
Data filter ba
andwidth selecct (Pin B)
Data filter ba
andwidth selecct (Pin A)
Chip enable pin (pull HIGH
H to enable th
he chip)
Data output
Data slicing threshold
t
cap
pacitor connecction
Supply voltag
ge for LO porrtion
Reference osscillator input pin
4
Pin No
o.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
O
October
2012
PT4302
FUNCTION DESCRIIPTION
N
POWER SUPPLY
S
Y
PT
T4302 provide
es an internall voltage regu
ulator to supp
ply power to the
t entire recceiver. Hence
e, all supply voltage
v
pins,
exccept VDD5, should be connected togeth
her with sufficcient bypass capacitance
c
a
added
as closse to each pin as possible.
On
nly the VDD5 pin (pin 8) sh
hould be conn
nected to an external
e
supplly voltage, witth series-R, shunt-C filterin
ng included if
neccessary. The
e PT4302 chip
p can operate
e over the sup
pply voltage range from 2.4
4 V to 5.5 V.
R FRON
RF
NT-END
The RF front-en
nd of the rece
eiver part is a superhetero
odyne configu
uration that co
onverts the in
nput radio frequency (RF)
sig
gnal into an in
ntermediate frequency
f
(IF
F) signal. The
e IF for the PT4302
P
chip is 10.7 MHzz. According to the block
dia
agram, the RF
F front-end co
onsists of a LNA
L
and a do
own-conversio
on mixer, and
d the local osccillator (LO) signal
s
for the
mixxer is generatted by the PL
LL frequency synthesizer.
s
As the receiver constitutes a superheterod
dyne architeccture, there is no inherent suppression
s
o the image frequency.
of
f
It
depends upon the
t particular application and the system
m's environme
ent conditionss whether an RF front-end
d filter should
be added or nott. If image rejjection or goo
od blocking im
mmunity is rele
evant system
m parameter, a band-pass filter
f
must be
pla
aced in front of
o the LNA. This
T
filter can be a SAW (su
urface acousttic wave) or LC-based
L
filter (e.g. helix tyype).
The RF front-en
nd provides the good low no
oise performa
ance (NF lesss than 5 dB), high
h
voltage conversion
c
ga
ain of over 40
dB, and excellen
nt reversion is
solation. The
e preferred LO
O side-band iss low-side inje
ection for redu
ucing power consumption.
c
The IF output im
mpedance of the
t mixer is about
a
330 Ohm
m in order to match the IF channel sele
ection filter.
The ANT pin may
m be matched to 50 Ω with
w an L-type
e circuit (e.g. a shunt indu
uctor from the
e RF input to
o ground and
ano
other in serie
es from the RF
R input to the antenna pin). An exam
mple of the input matching
g network is shown
s
in the
folllowing figure and the input impedance of
o the PT4302
2 for 315/433.92 MHz frequ
uency bands are
a listed in th
he right-hand
sid
de table. The component values
v
given in
n the BOM forr the application circuit sho
own on page 2 are nominall values only.
Ind
ductor and ca
apacitor value
es may be diffferent from the
t values givven in the table dependin
ng on PCB material,
m
PCB
thicckness, groun
nd configuratiion, and how long the trace
es are in the layout.
RF Frrequency fRF
3 MHz
315
3 MHz
340
3 MHz
390
43
33.92 MHz
V1.2
5
ANT Inpu
ut Impedance (Pin 3)
1.328 － j213.9
91
1.602 － j195.7
74
2.4
469 － j170.9
92
2.086 － j152.17
O
October
2012
PT4302
ANTENNA PART ESD PROTECTION
PT4302 IC provides better than 3 KV ESD immunity (human-body mode) at the ANT pin. However, higher ESD
protection level may be required at the system level for some applications. For such cases, ESD enhancement may rely
on external components. For example, changing L1 from SMD-type to coil-type can enhance ESD protection level by 1
KV, and adding a shunt coil inductor L2 in front of C1 can achieve additional ESD protection.
RF Frequency fRF
315 MHz
340 MHz
390 MHz
433.92 MHz
Suggested value of L2
39 nH
39 nH
33 nH
27 nH
REFERENCE OSCILLATOR
All timing and tuning operations on the PT4302 are derived from the internal one-pin Colpitts reference oscillator. Timing
and tuning is controlled through the REFOSC pin in one of two ways:
1. Connect a crystal,
2. Drive this pin with an external timing signal.
When a crystal is used, the minimum oscillation voltage swing is 300 mVPP. For an externally applied signal, the source
should be AC-coupled and limited to a voltage swing range from 0.3 VPP to 1.5 VPP.
As with any superheterodyne receiver, the mixing between the internal LO (local oscillator) frequency fLO and the
incoming carrier frequency fTX must ideally equal the IF center frequency (10.7 MHz). The following equation may be
used to compute the appropriate fLO for a given fTX:
fLO = fTX ± 10.7.
Frequencies fTX and fLO are expressed in MHz. Note that two values of fLO exist for any given fTX, distinguished as
“high-side” (fLO > fTX) and “low-side" (fLO < fTX) mixing. High-side mixing results in an image frequency above the
frequency of interest and low-side mixing results in an image frequency below. We recommend low-side mixing for
saving receiver power. After choosing one of the two acceptable values of fLO, use the following equation to compute the
reference oscillator frequency fREFOSC:
fREFOSC = fLO / 32 = (fTX － 10.7) / 32.
The following table identifies fREFOSC for some common transmit frequencies when the PT4302 chip is operated with
low-side mixing.
Transmit Frequency fTX
315 MHz
340 MHz
390 MHz
433.92 MHz
Reference Oscillator Frequency fREFOSC
9.509 MHz
10.29 MHz
11.853 MHz
13.226 MHz
The reference oscillator frequency is close to 10.7 MHz intermediate frequency. It is necessary to avoid signal trace
coupling between the reference oscillator and intermediate frequency to prevent degradation of receiver performance.
V1.2
6
October 2012
PT4302
PH
HASE-L
LOCKED
D LOOP (PLL)
(
The PT4302 utilizes a fixed divided-by-32
d
2 PLL to gene
erate the receiver LO. The
e PLL consistss of the voltag
ge-controlled
hronous ÷32 divider, charrge pump, loo
op filter and phase-freque
p
osccillator (VCO)), crystal oscillator, asynch
ncy detector
(PF
FD). All thesse components are integra
ated on-chip. The PFD co
ompares two
o signals and produces an
n error signal
wh
hich is proporttional to the difference
d
bettween the inp
put phases. The
T error sign
nal passes through a loop filter with an
approximately 200
2
KHz ban
ndwidth, and is used to control the VC
CO which generates an LO
L frequencyy. The VCO
frequency is alsso fed through
h a frequencyy divider backk to one inputt of the PFD, producing a feedback
f
loop
p. Thus, the
nce frequencyy at the other input, which is derived from
m a crystal oscillator (i.e. fREFOSC
= (fRF –
outtput is locked to the referen
R
fIF) / 32).
am below sho
ows the basicc elements of the PLL.
The block diagra
ASK DEM
MODULA
ATOR
The OOK/ASK demodulation
d
utilizes the RSSI
R
signal levvel. The RSSI signal is deccimated and filtered in the data
d
filter and
the
e data decisio
on is then com
mpleted by the
e slicing comp
parator.
The RSSI is imp
plemented as
s a successivve-detection lo
ogarithmic am
mplifier which is followed by
b the externa
al IF channel
filte
ering. The log
garithmic amp
plifier achieve
es ±3 dB logarrithmic linearitty, and the RS
SSI output levvel has a dyna
amic range of
aro
ound 80 dB with
w a slope off approximate
ely 11.5 mV /d
dB.
The IFIN pin pre
esents a differential 330 Ohm load to prrovide good matching
m
for th
he off-chip ce
eramic filter.
AUTOMA
ATIC GAIIN CONT
TROL (A
AGC)
The AGC circuitry monitors the RSSI vo
oltage level. When the RSSI
R
voltage exceeds a threshold refe
erence value
68 dBm, the AGC
A
switches on the LNA gain
g
and then
n reduces the
corrresponding to an RF inputt level of apprroximately –6
LN
NA gain by arround 30 dB, thereby reducing the RS
SSI output byy approximate
ely 345 mV. The thresho
old reference
volltage which iss compared with
w the RSS
SI voltage to determine
d
the
e gain state of
o the LNA is also reduced
d. The LNA
ressumes high-g
gain mode when
w
the RS
SSI voltage drops below
w this lower threshold voltage
v
corresponding to
approximately –75
– dBm RF input. The AG
GC incorporattes an additio
onal protection
n mechanism
m (delay timer of 220 × TREF
event immediate resetting
g of the LNA back to the high-gain sttate during re
eception of a “space” for
secconds) to pre
OO
OK/ASK modu
ulation.
The figure below
w shows the change
c
of RS
SSI voltage ve
ersus RF inpu
ut power. Wh
hen the RSSII level increasses and then
ower rising), the
t AGC swittches the LNA
A from high-g
gain mode to low-gain mod
de. As RSSI
excceeds 1.47 V (RF input po
levvel decreases back to 1.06 V (RF input power
p
falling), the AGC swittches the LNA
A from low-ga
ain mode backk to high-gain
mo
ode.
V1.2
7
O
October
2012
PT4302
RSSI Response
1.7
1.6
RSSI Level (V)
1.5
1.4
1.3
1.2
1.1
1
RF Input Power H-to-L
0.9
0.8
-120
RF Input Power L-to-H
-100
-80
-60
-40
-20
0
RF Input Power (dBm)
The AGC hysteresis delay times for the different frequency bands are listed below.
Parameter
AGC Hysteresis Delay Time
Condition
RF input power changes from High to Low
fRF = 315 MHz
110 ms
fRF = 433.92MHz
79 ms
DATA FILTER
The data filter (post-demodulator filter) is utilized here to remove other unwanted spurious signals after the OOK/ASK
demodulator, which is implemented as a 2nd-order low-pass Sallen-Key filter. The data filter bandwidth (BWDF) must be
selected according to the applications and should be set according to equation
BWDF = 0.65 / Shortest pulse-width.
The input pins of SELA and SELB control the data filter bandwidth in four binary steps (see the table below). It should be
noted that the values indicated in this table are nominal values. The filter bandwidth scales linearly with frequency, so
the exact value will depend upon the operating frequency.
SELA
SELB
1
1
0
0
1
0
1
0
Data Filter Bandwidth BWDF
fRF = 315 MHz
fRF = 433.92 MHz
900 Hz
1250 Hz
1800 Hz
2500 Hz
3600 Hz
5000 Hz
7200 Hz
10000 Hz
DATA SLICER
The purpose of the data slicer is to take the analog output of the data filter and convert it to a digital signal. Extraction of
the DC value of the demodulated signal for purposes of logic-level data slicing is accomplished using the external
threshold capacitor CTH and the on-chip resistor RTH, shown in the block diagram. Slicing level time constant (τ) values
vary somewhat with decoder type, data pattern, and data rate, but typical values range from 2 ms to 20 ms. Optimization
of the value of CTH is required to maximize range.
The first step in the process is selection of a data-slicing-level time constant. This selection is strongly dependent on
system issues including system decode response time and data code structure. The effective resistance of RTH is 25 KΩ
and τ of 3x the period of longest “LOW” or “HIGH” bit stream is recommended. Assuming that a slicing level time
constant τ has been established, capacitor CTH may be computed using equation
CTH = τ / RTH.
A standard ±20% X7R ceramic capacitor is generally sufficient.
V1.2
8
October 2012
PT4302
DATA SQUELCHING
During quiet periods (no signal) the data output (DO pin) transitions randomly with noise. Most decoders can
discriminate between this random noise and actual data, but for some system the random transitions do present a
problem. There are two possible approaches to reducing these output noise transitions:
1. Analog squelch to raise the demodulator threshold,
2. Output filter to filter the (high frequency) noise glitches on the data output pin.
The simplest solution is add analog squelch by introducing a small offset, or squelch voltage, on the CTH pin so that
noise does not trigger the internal slicer. Usually 20 mV to 30 mV is sufficient and may be achieved by connecting a
several mega-ohm resistor from the CTH pin to either VSS or internal supply voltage, depending on the desired offset
polarity. The squelch offset requirement does not change as the local noise strength changes from installation to
installation. Introducing squelch will reduce sensitivity and also reduce the receiving dynamic range. Only introduce an
amount of offset sufficient to quiet the output. Typical squelch resistor values range from 5.1 MΩ to 8.2 MΩ.
The circuit below shows an application example of analog squelch, where R6 is the squelch resistor. The demodulated
data then enters into a quasi-mute state as the RF input signal becomes very small (e.g. if there is no RF signal received
or the RF signal is too small) and the DO output remains mostly at a logic “LOW” level. If the environment is very noisy,
the R6 value may be reduced to achieve better immunity against noise, but at the cost of less sensitivity.
SENSITIVITY AND SELECTIVITY
In digital radio systems, sensitivity is often defined as the lowest signal level at the receiver input that will achieve a
specified bit error ratio (BER) at the output. The sensitivity of the PT4302 receiver, when used in the 315 MHz
application, is typically –112 dBm (ASK modulated with 2 Kb/s, 50% duty cycle square wave) to achieve a 0.1% BER.
The input was matched for a 50 Ω signal source. At 433.92 MHz, –111 dBm sensitivity is typically achievable.
The selectivity is governed by the response of the receiver front-end circuitry, the channel filter (off-chip 10.7 MHz IF
filter), and the data filter. Note the IF filter provides not only channel selectivity but also interference rejection. Within the
pass band of the receiver, no rejection for interfering signals is provided.
V1.2
9
October 2012
PT4302
POWER-DOWN CONTROL
The chip enable (CE) pin controls the power on/off behavior of the PT4302. Connecting CE to “HIGH” sets the PT4302
to its normal operation mode; connecting CE to “LOW” sets the PT4302 to standby mode. The chip consumption current
will be lower than 1 μA in standby mode. Once enabled, the PT4302 requires < 10 ms to recover received data with
minimum received RF input level.
The following figure illustrates the system start-up time with T = 27 ºC, fRF = 315 MHz, PRF = –110 dBm, CTH = 100 nF and
DRATE = 2 Kb/s. The CE pin is triggered every 200 mS.
ANTENNA DESIGN
For a λ/4 dipole antenna and operating frequency, f (in MHz), the required antenna length, L (in cm), may be calculated
by using the formula
L=
7132
.
f
For example, if the frequency is 315 MHz, then the length of a λ/4 antenna is 22.6 cm. If the calculated antenna length
is too long for the application, then it may be reduced to λ/8, λ/16, etc. without degrading the input return loss.
However, the RF input matching circuit may need to be re-optimized. Note that in general, the shorter the antenna, the
worse the receiver sensitivity and the shorter the detection distance. Usually, when designing a λ/4 dipole antenna, it is
better to use a single conductive wire (diameter about 0.8 mm to 1.6 mm) rather than a multiple core wire.
If the antenna is printed on the PCB, ensure there is neither any component nor ground plane underneath the antenna on
the backside of PCB. For an FR4 PCB (εr = 4.7) and a strip-width of 30 mil, the length of the antenna, L (in cm), is
calculated by
L=
c
4× f × εr
where “c” is the speed of light (3 x1010 cm/s)
PCB LAYOUT CONSIDERATION
Proper PCB layout is extremely critical in achieving good RF performance. At the very least, using a two-layer PCB is
strongly recommended, so that one layer may incorporate a continuous ground plane. A large number of via holes
should connect the ground plane areas between the top and bottom layers. Note that if the PCB design incorporates a
printed loop antenna, there should be no ground plane beneath the antenna.
V1.2
10
October 2012
PT4302
Careful consideration must also be paid to the supply power and ground at the board level. The larger ground area plane
should be placed as close as possible to all the VSS pins. To reduce supply bus noise coupling, the power supply trace
should be incorporate series-R, shunt-C filtering as shown below.
APPLICATION EXAMPLE
433.92 MHz Receiver / Decoder Application
The following schematic illustrates a typical application at 433.92 MHz frequency band for the PT4302 receiver IC. This
receiver operates continuously (not duty cycled) in the enable (active) mode, and features 6-bit address decoding.
The value of C5 may need to be increased if the idle time is too long between each data frame. Changes from the 1 kb/s
data rate may require a change in the value of R2. A bill of materials accompanies the schematic.
U1 PT4302
C1
1.0 pF
C2 100 nF
L1
47 nH
F1
X1
13.226 MHz
U2 PT2272
1
VSSLO
2
VSSRF
VLO
15
2
A1
VT
17
3
ANT
CTH
14
3
A2
OSC1
16
4
VRF
DO
13
4
A3
OSC2
15
5
MIXOUT
CE
12
5
A4
DIN
14
6
VBB
SELA
11
6
A5
A11
13
7
IFIN
SELB
10
7
A6
A10
12
8
VDD5
VSSBB
9
8
A7
A9
11
9
VSS
A8
10
REFOSC
16
6-bit
address
C4 100 nF
C5
680 nF
5V
1
A0
VCC
18
R3
1K
D1
R2
680 K
C3
4.7 uF
V1.2
Part
Part Number
Manufacturer
Description
U1
PT4302-X
Princeton Technology Corp.
UHF OOK/ASK receiver
U2
PT2272
Princeton Technology Corp.
Remote control decoder
F1
SFELA10M7HA00-B0
Murata
L1
-
-
10.7 MHz ceramic filter with 180 KHz BW
47 nH SMD inductor
C1
-
-
1.0 pF SMD capacitor
C2
-
-
100 nF SMD capacitor
C3
-
-
4.7 F SMD capacitor
C4
-
-
100 nF SMD capacitor
C5
-
-
680 nF SMD capacitor
R1
-
-
1 K SMD resistor with 5% tolerance
R2
-
-
680 K SMD resistor with 5% tolerance
X1
-
-
13.226 MHz crystal with maximum 60 ESR
D1
-
-
Red LED
11
October 2012
PT4302
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage Range
Analog I/O Voltage
Digital I/O Voltage
Operating Temperature Range
Storage Temperature Range
Symbol
VDD5
–
–
TA
TSTG
Min.
–0.3
–0.3
–0.3
–40
-40
Max.
6
3
6
+85
+150
Unit
V
V
V
°C
°C
PACKAGE THERMAL CHARACTERISTIC
Parameter
From Chip Conjunction Dissipation to
External Environment
From Chip Conjunction Dissipation to
Package Surface
V1.2
Symbol
Condition
Rja
Rjc
TA = 27 °C
12
Min.
Typ.
Max.
–
37.15
–
–
1
1.8
Unit
°C/W
October 2012
PT4302
ELECTRICAL CHARACTERISTICS
Nominal conditions: VDD5 = 5.0 V, VSS = 0 V, CE = “High”, TA = +27°C, fRF= 315 / 433.92 MHz, fREFOSC = 9.509 / 13.226
MHz.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
2.4
5.0
5.5
V
–
2.7
3.0
fRF = 433.92 MHz
–
2.9
3.2
CE=”Low”
–
–
1
μA
250
–
500
MHz
–20
–15
–
dBm
–
–112
–109
–
–106
–103
–
–111
–108
–
–105
–102
–
2
10
Kb/s
General Characteristics
Supply Voltage
VDD5
Current Consumption
IDD5
Standby Current
ISTBY
Operating Frequency Range
Maximum Receiver Input Level
Sensitivity1
Data Rate
LO Leakage
System Start-Up Time
Connect the supply voltage to
VDD5 pin only
fRF = 315 MHz
fRF
PRF,MAX
SIN
ASK2, DRate = 2 Kb/s, peak
power level @ 315 MHz
OOK, DRate = 2 Kb/s, peak
power level @ 315 MHz
ASK2, DRate = 2 Kb/s, peak
power level @ 433.92 MHz
OOK, DRate = 2 Kb/s, peak
power level @ 433.92 MHz
DRATE
mA
dBm
dBm
LLO
Measured at antenna input
–
–
–80
dBm
TSTUP
RF input power = –60 dBm
–
5
8
ms
Matched to 50Ω@ 315 MHz
40
43
46
Matched to 50Ω @ 433.92 MHz
39
42
45
Matched to 50Ω @ 315 MHz
–
5.7
6.3
Matched to 50Ω @ 433.92 MHz
–
6.1
6.7
300
330
360
Ω
–
10.7
–
MHz
–
180
–
KHz
RF Front-End
Voltage Conversion Gain
GVRF
Noise Figure
NFRF
Mixer Output Impedance
ZOUT,MIXER Measured at MIXOUT pin
dB
dB
IF Section
IF Frequency
fIF
Depends upon the external
ceramic filter
IF Bandwidth
BWIF
IF Input Impedance
ZIN,IF
300
330
360
Ω
SLRSSI
9.5
11.5
13.5
mV/dB
SELA = SELB = ”HIGH”
–
0.9
–
SELA = ”HIGH”; SELB = ”LOW”
–
1.8
–
SELA = ”LOW”; SELB = ”HIGH”
–
3.6
–
SELA = SELB = ”LOW”
–
7.2
–
TA = +85°C
–
±100
–
fRF = 315 MHz
–
110
–
fRF = 433.92 MHz
–
79
–
RSSI Slope
Demodulator
Post-Demodulator Filter Bandwidth
CTH Leakage Current
BWDF
IZCTH
KHz
nA
Automatic Gain Control (AGC)
AGC Hysteresis Delay Time3
V1.2
THYS
13
ms
October 2012
PT4302
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
7
–
16
MHz
0.3
–
1.5
V
Phase-Locked Loop
Reference Frequency
fREFOSC
Reference Signal Voltage Swing
VREF
Peak-to-peak voltage (VPP)
VCO Frequency Range
fVCO
220
–
550
MHz
Divider Ratio
DIV
–
32
–
–
Digital/Control Interface
Input-High Voltage
VIN,High
CE, SELA, SELB pins
0.8
–
–
VDD5
Input-Low Voltage
VIN,Low
CE, SELA, SELB pins
–
–
0.2
VDD5
DO pin, push-pull
–
20
–
μA
Output Current
IOUT
Output-High Voltage
VOUT,High
DO pin, IOUT = –1 μA
0.9
–
–
VDD5
Output-Low Voltage
VOUT,Low
DO pin, IOUT = +1 μA
–
–
0.1
VDD5
DO pin, CLOAD = 15 pF
–
10
–
μs
Output Rise/Fall Times
tR/ tF
Notes:
1. BER = 1e–3
2. AM 99% with square-wave modulation
3. RF input power changes from high to low
V1.2
14
October 2012
PT4302
Typical Operating Characteristics
Figure 1. Supply Current vs. Supply Voltage
Figure 2. Voltage Regulator Characteristic
Figure 3. Current Consumption vs. RF Frequency
Figure 4. Current Consumption vs. Temperature
Figure 5. Smith Plot of ANT
Figure 6. Sensitivity vs. Temperature
V1.2
15
October 2012
PT4302
Typical Operating Characteristics (cont’d)
Figure 7. Selectivity Response for fRF = 315 MHz
Figure 8. Selectivity Response for fRF = 433.92 MHz
TEST BOARD LAYOUT
<Top Side>
<Bottom Side>
V1.2
16
October 2012
PT4302
PACKAGE INFORMATION
16 Pins, SSOP (Shrink Small Outline Package with 3.9 × 4.9 mm Body
Size, 0.64 mm Pitch Size and 1.6 mm Thick Body)
Symbol
A
A1
A2
b
c
D
E
E1
e
L1
Min.
0.10
1.245
0.203
0.102
Nom.
4.90 BSC
6.00 BSC
3.90 BSC
0.635 BSC
1.04 REF
Max.
1.75
0.305
0.254
θ
0º
-
8º
Notes:
1. Refer to JEDEC MO-137AB
2. Unit: mm
V1.2
17
October 2012
PT4302
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
V1.2
18
October 2012