CDB4340A/41A
Evaluation Board for CS4340A and CS4341A
Features
Description
Demonstrates recommended layout and
grounding arrangements
CS8414 Receives AES/EBU, S/PDIF, &
EIAJ-340 Compatible Digital Audio
Digital and Analog Patch Areas
Requires only a digital signal source and
power supplies for a complete Digital-toAnalog-Converter system
The CDB4340A/41A evaluation board is an excellent
means for quickly evaluating the CS4340A/41A family of
24-bit, stereo D/A converters. Evaluation requires an analog signal analyzer, a digital signal source, a PC for
controlling the CS4341A and a power supply. Analog
outputs are provided via RCA phono jacks for both
channels.
The CS8414 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog
converters and will accept AES/EBU, S/PDIF, and EIAJ340 compatible audio data. The evaluation board may
also be configured to accept external timing signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4340A, CDB4341A
I/O for
Clocks
and Data
CS8414
Digital
Audio
Interface
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Control
Port
CS4340A/41A
Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
Evaluation Board
Mute
Circuit
Analog
Filter
JUN ‘02
DS590DB1
1
CDB4340A/41A
TABLE OF CONTENTS
1. CDB4340A/41A SYSTEM OVERVIEW .......................................................... 4
2. CDB4340A/41A ERRATA .............................................................................. 4
3. CS4340A/41A DIGITAL TO ANALOG CONVERTER .................................... 4
4. CS8414 DIGITAL AUDIO RECEIVER ............................................................ 4
5. CS8414 DATA FORMAT ................................................................................ 4
6. ANALOG OUTPUT FILTER ........................................................................... 5
7. INPUT/OUTPUT FOR CLOCKS AND DATA ................................................. 5
8. POWER SUPPLY CIRCUITRY ....................................................................... 5
9. GROUNDING AND POWER SUPPLY DECOUPLING .................................. 5
10. CDB4341A CONTROL PORT SOFTWARE ................................................. 5
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .............................................. 9
Figure 2. CS4340A/41A .................................................................................... 10
Figure 3. Analog Output Passive Filter .............................................................. 11
Figure 4. External Mute Circuit .......................................................................... 12
Figure 5. CS8414 Digital Audio Receiver Connections ..................................... 13
Figure 6. Digital Audio Inputs ............................................................................ 14
Figure 7. MCLK Divider and Voltage Level Converter ...................................... 15
Figure 8. Control Port Interface ......................................................................... 16
Figure 9. Reset Circuitry .................................................................................... 17
Figure 10. Power Supply ................................................................................... 18
Figure 11. I/O for Clocks and Data .................................................................... 19
Figure 12. Silkscreen Top ................................................................................. 20
Figure 13. Top Side ........................................................................................... 21
Figure 14. Bottom Side ...................................................................................... 22
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only
for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
2
DS590DB1
CDB4340A/41A
LIST OF TABLES
Table 1. CS8414 Supported Formats ................................................................... 4
Table 2. System Connections ............................................................................... 6
Table 3. CDB4340A Jumper Selectable Options .................................................. 6
Table 4. CDB4341A (I2C Mode) Jumper Selectable Options .............................. 7
Table 5. CDB4341A (SPI Mode) Jumper Selectable Options............................... 8
DS590DB1
3
CDB4340A/41A
1. CDB4340A/41A SYSTEM OVERVIEW
The CDB4340A/41A evaluation board is an excellent means of quickly evaluating the
CS4340A/41A. The CS8414 digital audio interface
receiver provides an easy interface to digital audio
signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a
10-pin header for system development.
The CDB4340A/41A schematic has been partitioned into 10 schematics shown in Figures 2
through 11. Each partitioned schematic is represented in the system diagram shown in Figure 1.
Notice that the system diagram also includes
the interconnections between the partitioned schematics.
2. CDB4340A/41A ERRATA
The CS4340A is mounted on the same PCB used to
evaluate the CS4340. Please see tables 3 to 5 for
jumper settings that are not applicable to the
CDB4340A/41A. These jumpers should retain the
default setting from the factory. Also, all SDATA
net names for the CS4340A shall be interpreted as
SDIN, as seen in the pin description of the
CS4340A datasheet.
3. CS4340A/41A DIGITAL TO ANALOG
CONVERTER
A description of the CS4340A is included in the
CS4340A data sheet. A description of the
CS4341A is included in the CS4341A data sheet.
4. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8414 Digital Audio
Receiver, Figure 5. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock
(FSYNC), and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital
audio interface are included in the CS8414
Datasheet.
During normal operation, the CS8414 operates in
the Channel Status mode where the LED's display
channel status information for the channel selected
by the CSLR/FCK jumper.
When the Error & Frequency button is enabled, the
CS8414 operates in the Error and Frequency information mode. The information displayed by the
LED's can be decoded by consulting the CS8414
data sheet.
Encoded sample frequency information can be displayed provided a proper clock is being applied to
the FCK pin of the CS8414. When an LED is lit,
this indicates a "1" on the corresponding pin located on the CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L
or R option of CSLR/FCK should be selected if the
FCK pin is being driven by a clock signal.
5. CS8414 DATA FORMAT
The CS8414 data format can be set with jumpers
M0, M1, M2, and M3, as described the CS8414
datasheet. The format selected must be compatible
with the data format of the CS4340A or CS4341A,
shown in the CS4340A and CS4341A datasheets.
Please note that the CS8414 does not support all the
possible modes of the CS4340A or CS4341A, see
Table 1 for details. The default settings for M0-M3
on the evaluation board are given in Tables 3-5.
CS4341A CS4340A
CS8414
External Internal
Format
Format
Format
SCLK
SCLK
0
2
Yes
Yes
1
0
2
Yes
No
2
1
0
No
Yes
3
2
Unsupported
4
Unsupported
5
3
5
Yes
No
6
6
Yes
Yes
7
0
2
Yes
No
Table 1. CS8414 Supported Formats
4
DS590DB1
CDB4340A/41A
6. ANALOG OUTPUT FILTER
The evaluation board includes a pair of single pole
passive filters. The passive filters, Fig. 3, have a
corner frequency of approximately 95 kHz with
JP3 and JP6 installed and 190 kHz without JP3 and
JP6.
7. INPUT/OUTPUT FOR CLOCKS AND
DATA
The evaluation board has been designed to allow
the interface to external systems via the 10-pin
header, J9. This header allows the evaluation board
to accept externally generated clocks and data. The
schematic for the clock/data I/O is shown in
Figure 11. The 74HC243 transceiver functions as
an I/O buffer where jumpers HDR1-HDR6 determine if the transceiver operates as a transmitter or
receiver. A transmit function is implemented with
the HDR1-HDR6 jumpers in the 8414 position.
LRCK, SDATA, and SCLK from the CS8414 will
be outputs on J9. The transceiver operates as a receiver with jumpers HDR1-HDR6 in the EXTERNAL position. MCLK, LRCK, SDATA and SCLK
on J9 become inputs.
8. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by three
binding posts (GND, +5V, +3V/+5V) (see
Figure 10). The +5V input supplies power to the
+5 Volt digital circuitry (VA+5, VD+5, VDPC+5),
while the +3V/+5V input supplies power to the
DS590DB1
Voltage Level Converter and the CS4340A/41A
for evaluation in either +3 or +5 Volt mode.
9. GROUNDING AND POWER SUPPLY
DECOUPLING
The CS4340A/41A requires careful attention to
power supply and grounding arrangements to optimize performance. Figure 10 details the power distribution used on this board. The CDB4340A/41A
ground plane is split to control the digital return
currents in order to minimize digital interference.
The decoupling capacitors are located as close to
the CS4340A/41A as possible. Extensive use of
ground plane fill on both the analog and digital sections of the evaluation board yields large reductions in radiated noise.
10. CDB4341A CONTROL PORT
SOFTWARE
The CDB4341A is shipped with Windows based
software for interfacing with the CS4341A control
port via the DB25 connector, P1. The software can
be used to communicate with the CS4341A in either SPI or I2C mode; however, in SPI mode the
CS4341A registers are write-only.
Run SETUP.EXE from the distribution diskette to
install the software. Further documentation for the
software is available on the distribution diskette.
The documentation is available in the plain text format file, README.TXT.
5
CDB4340A/41A
CONNECTOR
INPUT/OUTPUT
SIGNAL PRESENT
+5 V
input
+ 5 Volt power
+3V/+5V
input
+ 3 Volt or + 5 Volt power for the CS4340A/41A and the Voltage Level Converter
GND
input
ground connection from power supply
Digital input
input
digital audio interface input via coax
Optical input
input
digital audio interface input via optical
J9
input/output
I/O for master, serial, left/right clocks and serial data
Parallel Port
input/output
parallel connection to PC for SPI/I2C control port signals
Control I/O
input/output
I/O for SPI/I2C control port signals
AOUTA
output
channel A analog output with single-pole passive filter
AOUTB
output
channel B analog output with single-pole passive filter
Table 2. System Connections
JUMPER
CSLR/FCK
PURPOSE
FUNCTION SELECTED
HI
*LO
See CS8414 Datasheet for details
CS8414 mode selection
*Low
*High
*Low
*Low
See CS8414 Datasheet for details
SCLK
N/A
INT
*EXT
N/A
DEM_8414
N/A
*8414
DEM
N/A
HDR1-6
Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes an source
HDR 7
Enables the external mute for
AOUTA
*ON
OFF
Mute Enabled
Mute Disabled
HDR 8
Enables the external mute for
AOUTB
*ON
OFF
Mute Enabled
Mute Disabled
MCLK
Selects Single-Speed or DoubleSpeed Modes
*x1
÷2
Selects Single-Speed Mode
Selects Double-Speed Mode
HDR15
DIF1
HI
*LOW
See CS4340A Datasheet for details
HDR16
DIF0
HI
*LOW
See CS4340A Datasheet for details
HDR17
DEM0
HI
*LOW
See CS4340A Datasheet for details
M0
M1
M2
M3
ENCTRL
Selects channel for CS8414
channel status information
POSITION
Enables/Disables parallel port
Enable
*Disable
Invalid for CS4340A
Disables parallel port
Table 3. CDB4340A Jumper Selectable Options
*Default setting from factory
6
DS590DB1
CDB4340A/41A
JUMPER
CSLR/FCK
PURPOSE
FUNCTION SELECTED
HI
*LO
See CS8414 Datasheet for details
CS8414 mode selection
*Low
*High
*Low
*Low
See CS8414 Datasheet for details
SCLK
N/A
INT
*EXT
N/A
DEM_8414
N/A
*8414
DEM
“Don’t Care” for CS4341A
HDR1-6
Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes an source
HDR 7
Enables the external mute for
AOUTA
*ON
OFF
Mute Enabled
Mute Disabled
HDR 8
Enables the external mute for
AOUTB
*ON
OFF
Mute Enabled
Mute Disabled
MCLK
Selects Single-Speed or DoubleSpeed Modes
*x1
÷2
Selects Single-Speed Mode
Selects Double-Speed Mode
HDR15
SCL Pull-Up
*HI
LOW
SCL pulled high
Invalid for I2C mode
HDR16
SDA Pull-Up
*HI
LOW
SDA pulled high
Invalid for I2C mode
HDR17
AD0
HI
*LOW
“Don’t Care” for Control Port Mode
M0
M1
M2
M3
ENCTRL
Selects channel for CS8414
channel status information
POSITION
Enables/Disables parallel port
*Enable
Disable
Enables parallel port
Disables parallel port (must use HDR14)
Table 4. CDB4341A (I2C Mode) Jumper Selectable Options
*Default setting from factory
Notes:
DS590DB1
The CDB4341A evaluation board is shipped from the factory configured for I2C mode.
7
CDB4340A/41A
JUMPER
CSLR/FCK
PURPOSE
FUNCTION SELECTED
HI
*LO
See CS8414 Datasheet for details
CS8414 mode selection
*Low
*High
*Low
*Low
See CS8414 Datasheet for details
SCLK
N/A
INT
*EXT
N/A
DEM_8414
N/A
*8414
DEM
“Don’t Care” for CS4341A
HDR1-6
Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes an source
HDR 7
Enables the external mute for
AOUTA
*ON
OFF
Mute Enabled
Mute Disabled
HDR 8
Enables the external mute for
AOUTB
*ON
OFF
Mute Enabled
Mute Disabled
MCLK
Selects Single-Speed or DoubleSpeed Modes
*x1
÷2
Selects Single-Speed Mode
Selects Double-Speed Mode
HDR15
CCLK Pull-up or Pull-down
*HI
LOW
“Don’t Care” for SPI mode
HDR16
CDIN Pull-up or Pull-down
*HI
LOW
“Don’t Care” for SPI mode
HDR17
CS Pull-up
HI
*LOW
“Don’t Care” for Control Port Mode
M0
M1
M2
M3
ENCTRL
Selects channel for CS8414
channel status information
POSITION
Enables/Disables parallel port
*Enable
Disable
Enables parallel port
Disables parallel port (must use HDR14)
Table 5. CDB4341A (SPI Mode) Jumper Selectable Options
*Default setting from factory
Notes:
8
When in SPI mode, it is not possible to read the control registers of the CS4341A. The CDB4341A
evaluation board is shipped from the factory configured for I2C mode.
DS590DB1
CDB4340A/41A
I/O for
Clocks
and Data
Fig 11
Digital
Audio
Input
Fig 6
Control
Port
Interface
Fig 8
RXN
RXP
CS8414
Digital
Audio
Receiver
Connections
Fig 5
MCLK
LRCK
SCLK
SDATA
Voltage MCLK
LRCK
Level
Converter SCLK
SDATA
Fig 7
CS4340A/41A
Fig 2
Reset
Circuit
Fig 9
Passive
Analog
Filter
Fig 3
External
Mute
Circuit
Fig 4
Figure 1. System Block Diagram and Signal Flow
DS590DB1
9
10
DEM0/AD0/CS-A
DIF0/SDA/CDIN
DIF1/SCL/CCLK-A
MCLK-A
LRCK-A
DEM1/SCLK-A
SDATA-A
RST
R10
499
R13
499
R14
499
R41
49.9
R40
200
R39
200
8
7
6
5
4
3
2
1
MUTEC
AOUTA
VA
CS4340A AGND
AOUTB
REF_GND
VQ
FILT+
CS4340A_KS
/RST
SDIN
SCLK
LRCK
MCLK
DIF1
DIF0
DEM
Figure 2. CS4340A/41A
1
2
3
4
5
6
7
8
U7
16
15
14
13
12
11
10
9
MUTEC
MUTEC
C20
1UF
AGND
1UF
C21
C34
.1UF
TP4
C17
.1UF
X7R
TP5
ALP
C35
.1UF
C43
3.3UF
C23
10UF
AGND
ARP
FERRITE_BEAD
L1
C44
3.3UF
VA+3/+5
CDB4340A/41A
X7R
X7R
DS590DB1
DS590DB1
ARP
MUTEB
ALP
MUTEA
AGND
R29
10K
R17
AGND
R28
10K
R18
AGND
JP6
AGND
JP3
2
1
2
AGND
C5
1500PF
COG
1
3
4 NC
J3
CON_RCA_RA
3
4 NC
J4
CON_RCA_RA
AGND
C6
1500PF
COG
Figure 3. Analog Output Passive Filter
560
C22
1500PF
COG
HDR1X2
HDR8
1
2
560
C18
1500PF
COG
HDR1X2
HDR7
1
2
AOUTRP
B
AOUTLP
A
CDB4340A/41A
11
12
MUTEC
1
AGND
2
3
3
R31
R25
MMUN2111LT1
Q3
Figure 4. External Mute Circuit
Q4
MMUN2211LT1
1
2
VA+3/+5
2K
2K
3
1
2
AGND
Q1
2SC2878
MUTEA
3
AGND
1
2
MUTEB
Q2
2SC2878
CDB4340A/41A
DS590DB1
8414_DEM
VD+5
RN3
560
10
8
6
4
D2
12
LED_RECT
LED_RECT
D4
D6
LED_RECT
LED_RECT
D5
LED_RECT
D3
2
SN74HC04N
D1
LED_RECT
U8
VD+5
GND
VCC
GND
7
14
13
11
9
5
3
1
C16
.1UF
GND
GND
C1
10UF
VD1
RXP
RXN
1UF
.1UF
X7R
10
CSLR/FCK
C31
C26
R11
VA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
U2
CS8414
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDATA
LRCK
SCLK
C
VERF
CD/F1
CE/F2
CC/F0
SDATA
CB/E2
ERF
CA/E1
M1
/C0/E0
M0
VD+
VA+
DGND
AGND
RXP
FILT
RXN
MCK
FSYNC
M2
SCK
M3
CS12/FCK
SEL
U
CBL
HDR1X3
HDR1
HDR1X3
HDR2
HDR1X3
HDR3
MCLK
VD1
1UF
C32
C33
.1UF
X7R
ERROR & FREQ
R7
47.5K
SW_B3W_1100
S4
R9
470
C27
Figure 5. CS8414 Digital Audio Receiver Connections
VA+5
HDR1X3
HDR4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
DS590DB1
GND
HDR1X3
HDR5
VA
8414_DEM
TP10
GND
CSLR/FCK
GND
DEM1/SCLK
SCLK
.068UF
X7R
CS8414_M2
CS8414_M1
CS8414_M0
HDR1X3
EXT_INT_SCLK
1
INT
2
3
EXT
HDR1X3
8414_DEM
1
DEM
2
3
8414
R6
47.5K
INT/EXT SCLK
HDR1X3
CSLR/FCK
1
2
CSLR/FCK
3
HDR1X3
M3
1
2
8414_M
3
HDR1X3
M2
1
2
M2
3
HDR1X3
M1
1
2
M1
3
HDR1X3
M0
1
2
M0
3
VD1
CDB4340A/41A
13
14
NC
3
4
2
1
GND
CON_RCA_RA
J5
C11
R30 .01UF
75
DIGITAL INPUT
5
Figure 6. Digital Audio Inputs
RXN
6
TORX173
OPT1
4
3
2
1
C9
.01UF
C10
47UH
L4
.01UF
GND
OPTICAL INPUT
VD+5
RXP
CDB4340A/41A
DS590DB1
DS590DB1
GND
VD+5
VD+5
VD+5
VD+5
VD+5
10
11
12
13
4
3
2
1
GND
/Q2
Q2
/Q1
Q1
VCC
C15
.1UF GND
MC74HC74AN
/SET2
CLOCK2
DATA2
/RST2
/SET1
CLOCK1
DATA1
/RST1
U1
7
8
9
6
5
14
GND
HRM
MCLK
MCLK-B
BRM
J20
HDR1X3
DEM0/AD0/CS
DIF1/SCL/CCLK
SDATA
DEM1/SCLK
LRCK
MCLK
2
3
4
5
6
7
8
9
19
1
U5
GND
B1
B2
B3
B4
B5
B6
B7
B8
VCC
SN74VHC245DW
A1
A2
A3
A4
A5
A6
A7
A8
/G
DIR
Figure 7. MCLK Divider and Voltage Level Converter
VD+5
1
2
3
10
18
17
16
15
14
13
12
11
20
GND
C14
VA+3/+5
AGND
DEM0/AD0/CS-A
SDATA-A
DEM1/SCLK-A
LRCK-A
MCLK-A
DIF1/SCL/CCLK-A
.1UF
CDB4340A/41A
15
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
DB25M_RA
P1
GND
GND
2
3
4
5
6
7
8
9
1
11
U3
HDR4X2
HDR14
1
2
3
4
5
6
7
8
LATCH
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
5
GND
9
VDPC+5
DIF1/SCL/CCLK
DIF0/SDA/CDIN
DEM0/AD0/CS
20
10
19
18
17
16
15
14
13
12
GND
.1UF
GND
13
SN74HCT125N
8
U6
11
U6
HDR1X3
HDR15
1
2
3
SN74HCT125N
10
12
Figure 8. Control Port Interface
GND
3
SN74HCT125N
U6
VCC
GND
7 1
14
SN74HC574N
1D
2D
3D
4D
5D
6D
7D
8D
/OC
CLK
4
GND
VCC
U6
6
SN74HCT125N
2
C4
VDPC+5
1K
1K
1K
1K
1K
1K
R2
R3
R5
R4
R8
R12
PC0
LATCH
ENCTRL
VDPC+5
2K
HDR1X3
HDR16
1
2
3
GND
HDR1X3
HDR17
1
2
3
GND
HDR1X3
HDR18
1
2
3
VDPC+5
ENCTRL
DEM0/AD0/CS
DIF0/SDA/CDIN
DIF1/SCL/CCLK
VDPC+5
2K
R19
R16
VA+3/+5
2K
R20
2K
R21
.1UF
2K
R22
16
2K
GND
R23
C7
CDB4340A/41A
DS590DB1
AGND
R1
200K
RST
Figure 9. Reset Circuitry
3.3UF
C29
AGND
D7
R27
BAT85
S1
SW_B3W_1100
DS590DB1
100
VA+3/+5
CDB4340A/41A
17
GND
.1UF
10UF
C19 VDPC+5
C8
VA+5
L3
FB
.1UF
C13
47UF
C25
GND
C3
.1UF
Z2
C2
47UF
C12
47UF
J1
CON_BANANA
+3V/+5V
P6KE6V8P
P6KE6V8P
Figure 10. Power Supply
VD+5
J7
J6
AGND
CON_BANANA
CON_BANANA
Z1
GND
L2
FB
18
+5V
VA+3/+5
CDB4340A/41A
DS590DB1
GND
DS590DB1
GND
C24
.1UF
VD+5
MCLK
SCLK
LRCK
SDATA
14
8
9
10
11
7
GBA
/GAB
A4
A3
A2
A1
13
1
6
5
4
3
Figure 11. I/O for Clocks and Data
VCC
B4
B3
B2
B1
U4
74HC243
GND
10
8
6
4
2
GND
HDR1X3
HDR6
8414
EXTERNAL
CLK SOURCE
DIGITAL I/O
J9
HDR5X2
9
7
5
3
1
VD+5
MCLK
SCLK
LRCK
SDATA
CDB4340A/41A
1
2
3
GND
19
CDB4340A/41A
Figure 12. Silkscreen Top
20
DS590DB1
CDB4340A/41A
Figure 13. Top Side
DS590DB1
21
CDB4340A/41A
Figure 14. Bottom Side
22
DS590DB1
• Notes •