ispPAC-POWR Product Family

Lattice ispPAC-POWR Product Family Qualification Summary
Lattice Document # 25 – 106672 Rev. H
March 2013
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and informati on herein are subject to change
without notice.
www.latticesemi.com
Dear Customer,
Enclosed is Lattice Semiconductor’s ispPAC-POWR Product Family Qualification Summary Product Family
Qualification Report.
This report was created to assist you in the decision making process of selecting and using our products. The
information contained in this report represents the entire qualification effort for this device family.
The information is drawn from an extensive qualification program of the wafer technology and packaging
assembly processes used to manufacture our products. The program adheres to JEDEC and Automotive
Industry standards for qualification of the technology and device packaging. This program ensures you only
receive product that meets the most demanding requirements for Quality and Reliability.
Your feedback is valuable to Lattice. If you have suggestions to improve this report, or the data included, we
encourage you to contact your Lattice representative.
Sincerely,
James M. Orr
Vice President,
Corporate Quality & Product Development
Lattice Semiconductor Corporation
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
2
INDEX
1.0 INTRODUCTION ......................................................................................................................................4
Table 1.1 Lattice ispPAC-POWR Product Family Attributes............................................................................4
2.0 LATTI CE PRODUCT QUALIFICATION P ROGRAM ...................................................................................5
Figure 2.1 ispPAC-POWR Product Qualification Process Flow .......................................................................6
Table 2.2 Standard Qualification Testing .....................................................................................................8
3.0 QUALIFICATION DATA FOR i spP AC-POWR Product Family ................................................................ 10
3.1 ispPAC-POWR Product Family Life Data ................................................................................................. 10
Table 3.1.1 ispPAC-POWR Product Family HTOL Results........................................................................... 10
3.2 ispPAC-POWR Product Family High Temperature Data Retention (HTRX) ................................................... 11
Table 3.2.1 ispPAC-POWR High Temperature Data Retention (HTRX) Results .............................................. 11
3.3 ispPAC-POWR Product Family Extended Endurance (EE) ......................................................................... 12
Table 3.3.1 ispPAC-POWR Extended Endurance (EE) Results .................................................................... 12
3.4 ispPAC-POWR Product Family - ESD and Latch UP Data.......................................................................... 13
Table 3.4.1 ispPAC-POWR ESD-HBM Data .............................................................................................. 13
Table 3.4.2 ispPAC-POWR ESD-CDM Data .............................................................................................. 14
Table 3.4.3 ispPAC-POWR I/O Latch Up Data ........................................................................................... 15
4.0 PACKAGE QUALIFI CATI ON DATA FOR i spPAC-P OWR PRODUCT FAMILY ......................................... 16
Table 4.1 ispPAC-POWR Product-Package Qualification-By-Extension Matrix ............................................... 16
4.1 ispPAC-POWR Product Family Surface Mount Preconditioning Testing ....................................................... 17
Table 4.1.1 Surface Mount Precondition Data ............................................................................................ 17
4.2 ispPAC-POWR Product Family Temperature Cycling Data ......................................................................... 19
Table 4.2.1 Temperature Cycling Data...................................................................................................... 19
4.3 Unbiased HAST Data ............................................................................................................................ 20
Table 4.3.1 Unbiased HAST Data............................................................................................................. 20
4.4 THB: Biased HAST Data........................................................................................................................ 21
Table 4.4.1 Biased HAST Data ................................................................................................................ 21
4.5 HTSL: High Temperature Storage Life Data ............................................................................................. 22
Table 4.5.1 High Temperature Storage Life Results .................................................................................... 22
5.0 ispPAC-POW R Proce ss Reliability Wafer Level Review ........................................................................ 23
Table 5.1 UMC Foundry Wafer Level Reliability Results for EE8A (0.35um) Process Technology ..................... 23
Table 5.2 Epson Foundry Wafer Level Reliability Results for EE8A (0.35um) Process Technology.................... 24
6.0 ispPAC-POW R PACKAGE ASS EMBLY INTEGRITY TES TS ................................................................... 25
6.1 Wire Bond Shear Test ........................................................................................................................... 25
6.2 Wire Bond Pull ..................................................................................................................................... 25
6.3 Solderability ......................................................................................................................................... 25
6.4 Physical Dimensions ............................................................................................................................. 25
7.0 ispPAC-POW R ADDITIONAL FAMILY DATA.......................................................................................... 26
Table 7.1 ispPAC-POWR Package Assembly Data- TQFP/QFNS................................................................. 26
8.0 Revi sion Hi story.................................................................................................................................... 27
Table 8.1 Lattice ispPAC-POWR Product Family Qualification Summary revisions.......................................... 27
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
3
1.0 INTRODUCTION
Lattice ispPAC-POWR devices provide highly accurate, flexible, and low cost solutions for circuit board power
supply and processor/DSP supply management. By integrating a versatile PLD core with Analog-to-Digital (ADC)
converter, Digital-to-Analog Converters (DAC), differential sense analog monitors, I2C communication, and insystem programmability (isp), Lattice power management devices increase board reliability, decrease component
count, and help cut costs. Two power management families: ProcessorPM and Power Manager II address a
variety of applications – all in a single low-cost chip.
The ispPAC-POWR product family is built on EE8A which is a 3.3V shallow trench isolated, 0.35um drawn /
0.25um Leff CMOS process with Electrically Erasable (E2) cells. This process uses three planarized metal
interconnect layers and single layer polysilicon fabricated at either United Microelect ronics Company (UMC) wafer
fab, or Epson wafer fab at Sakata, and assembled at Advance Semiconductor Engineering Malaysia (ASEM),
Amkor Korea and UNISEM Group Singapore, in TQFP and QFNS packages. To verify product reliability, Lattice
Semiconductor maintains an active Early Life and Inherent Life Reliability Monitor program on the ispPAC-POWR
products. Lattice Semiconductor publishes the Reliability Monitor Data quarterly.
Table 1.1 Lattice ispPAC-POWR Product Family Attributes
Family
Device Types /
Parameter
Analog Input Pins
No. of Programmable
Threshold Comparators
Trip Points per Input
Typical Precision
Lowest Supply Voltage
Monitored
Power-Off Detection
CPLD Macrocells
No. of Outputs
No. of FET Drivers
Trim Outputs (DACs)
ADC Support
I2C Interface
Operating Voltage
Process Technology
Die Metallization
Power Manager II
ProcessorPM
12
POWR1014 /A
LA-POWR1014/A*
10
24
20
-
6
6
368
0.20%
368
0.30%
-
192
0.50%
192
0.50%
0.67V
0.67V
-
0.67V
0.67V
75 mV
48
20 & 8
4
8
Yes (10 bit)
Yes
2.8V to 3.9V
0.35um CMOS
Al – 0.5% Cu
75 mV
24
14
2
Yes (10 bit)* +
Yes
2.8V to 3.9V
0.35um CMOS
Al – 0.5% Cu
6 trim outputs
6
Yes (10 bit)
Yes
2.8V to 3.9V
0.35um CMOS
Al – 0.5% Cu
75 mV
16
7
2
No
No
2.6V to 3.9V
0.35um CMOS
Al – 0.5% Cu
75 mV
16
5
No
No
2.6V to 3.9V
0.35um CMOS
Al – 0.5% Cu
Die Interconnect
Dielectric
Plasmaenhanced TEOS
Plasma-enhanced
TEOS
Plasmaenhanced TEOS
Pins/Packages
100 TQFP
(Pb and Pb-Free)
48 TQFP
(Pb and Pb-Free)
32 QFNS
(Pb and Pb-Free)
POWR1220AT8
POWR6AT6
POWR607
POWR605
6
6
6
Plasmaenhanced
TEOS
32 QFNS
(Pb and Pb-Free)
Plasma-enhanced
TEOS
24 QFNS
(Pb-Free)
* LA-POWR1014/A is an Automotive product offering.
+ Available only in isPAC-POWR1014A.
Power Manager II devices are Lattice's second generation of fully -programmable power management devices
specifically designed for power supply sequencing and monitoring of various power supplies.
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
4
2.0 LATTICE PRODUCT QUALIFICATION PROGRAM
Lattice Semiconductor Corp. maintains a comprehensive reliability qualification program to assure that each
product achieves its reliability goals. After initial qualification, the continued high reliability of Lattice produ cts is
assured through ongoing monitor programs as described in Reliability Monitor Program Procedure (Doc. #70101667). All product qualification plans are generated in conformance with Lattice Semiconductor’s Qualification
Procedure (Doc. #70-100164) with failure analysis performed in conformance with Lattice Semiconductor’s
Failure Analysis Procedure (Doc. #70-100166). Both documents are referenced in Lattice Semiconductor’s
Quality Assurance Manual, which can be obtained upon request from a Lattice Semiconductor sales office or
downloaded from the lattice website at www.latticesemi.com. Figure 2.1 shows the Product Qualification Process
Flow.
If failures occur during qualification, an 8-Discipline (8D) process is used to find root cause and eliminate the
failure mode from the design, materials, or process. The effectiveness of any fix or change is validated through
additional testing as required. Final testing results are reported in the qualification report s.
Failure rates in this reliability report are expressed in FITS. Due to the very low failure rate of integrated circuits, it
is convenient to refer to failures in a population during a period of 10 9 device hours; one failure in 109 device
hours is defined as one FIT.
Product families are qualified based upon the requirements outlined in Table 2.2. In general, Lattice
Semiconductor follows the current Joint Electron Device Engineering Council (JEDEC) and Military Standard
testing methods. Lattice automotive products are qualified and characterized to the Automotive Electronics
Council (AEC) testing requirements and methods. Product family qualification will include products with a wide
range of circuit densities, package types, and package lead count s. Major changes to products, processes, or
vendors require additional qualification before implementation.
The ispPAC-POWR product family is built on the 0.35um EE8A Electrically Erasable (E2 cell based) CMOS
process at either United Microelectronics Company (UMC) wafer fab, or Epson wafer fab at Sakata, and
assembled at Advance Semiconductor Engineering Malaysia, (ASEM), Amkor Technology, Korea and UNISEM
Group, Indonesia, in TQFP and QFNS packages. To verify product reliability, Lattice Semiconductor maintains an
active Early Life and Inherent Life Reliability Monitor program on the ispPAC-POWR products.
Lattice Semiconductor maintains a regular reliability monitor program. The current Lattice Reliability Monitor
Report can be found at www.latticesemi.com/lit/docs/qa/product_reliability_monitor.pdf .
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
5
Figure 2.1 ispPAC-POWR Product Qualification Process Flow
Qualification
Plan Request










Determine Generic
Qualification Type
New Foundry Technology
Process Change
Foundry Transfer
New Product Family
Add Product to Family
Design Change
New Package Technology
Package Materials Change
Assembly Transfer
Expand Die or Package Size
Automotive or
Commercial?
Commercial / Industrial
JESD47
Standard Qualification
Requirements
Automotive
AEC-Q100
Standard Qualification
Requirements
Check for Customer
Specific Requirements
Generate FMEA:
Risk Management
& Lessons Learned
Generate Qualification
Plan
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
6
Approved
Qualification Plan
Qualifiable Material
Review
Commercial
Automotive
Automotive or
Commercial?
Commercial
Room Temperature
Pre-stress testing
& data logging
Automotive
3-Temperature
Pre-stress testing
& data logging
JEDEC standard based reliability stressing
Room Temperature
Post-stress testing &
data logging
3-Temperature
Post-stress testing &
data logging
Qualification
Failures?
Failure
Analysis
Qualification
Report
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
7
Table 2.2 Standard Qualification Testing
TEST
STANDARD
High Temperature Lattice Procedure
Operating Life
# 87-101943,
HTOL
MIL-STD-883,
Method 1005.8,
JESD22-A108C
SAMPLE SIZE
PERFORMED ON
(Typ)
125° C,
77/lot
Product Design and
Maximum operating Vcc,
2-3 lots
Foundry Process
168, 500, 1000 hours
Qualification
TEST CONDITIONS
Preconditioned with 100
program/erase cycles
High Temp Data
Retention
HTRX
Lattice Procedure
# 87-101925,
JESD22-A103C
JESD22-A117A
150° C,
Maximum operating Vcc,
168, 500, 1000 hours
100/lot
2-3 lots
Product Design and
Foundry Process
Qualification
Preconditioned with 100
program/erase cycles
Endurance Program/Erase
Cycling
Lattice Procedure,
# 70-104633
JESD22-A117B
E2 Cell Products
ESD HBM
ESD CDM
Latch Up
Resistance
LU
Surface Mount
Pre-conditioning
SMPC
Temperature
Cycling
TC
High Temp
Storage Life
HTSL
Unbiased HAST
UHAST
Lattice Procedure
# 70-100844,
MIL-STD-883,
Method 3015.7
JESD22-A114E
Lattice Procedure
# 70-100844,
JESD22-C101D
Lattice Procedure
# 70-101570,
JESD78A
Lattice Procedure
# 70-103467,
IPC/JEDEC
J-STD-020D.1
JESD-A113F
CPLD/FPGA - MSL 3
Lattice Procedure
#70-101568,
MIL-STD- 883,
Method 1010,
Condition B
JESD22-A104C
Lattice Procedure
# 87-101925,
JESD22-A103C
Lattice Procedure
# 70-104285
JESD22-A118
Program/Erase
devices to 1000 cycles
Program/Erase devices
to 10X cycles of data
sheet specification
Human Body Model
(HBM) sweep to 2000
volts – (130nm and
older)
Charged Device model
(CDM) sweep to 1000
volts (130nm and older)
±100 ma on I/O's,
Vcc +50% on Power
Supplies. (Max operating
temp.)
10 Temp cycles,
24 hr 125° C Bake
192hr. 30/60 Soak
3 SMT simulation cycles
E2 Cell Products
10/lot
Product Design and
2-3 lots typical Foundry Process
Qualification
3 parts/lot
Product Design and
1-3 lots typical Foundry Process
Qualification
3 parts/lot
Product Design and
1-3 lots typical Foundry Process
Qualification
6 parts/lot
Product Design and
1-3 lots typical Foundry Process
Qualification
All units going Plastic Packages only
into
Temp Cycling,
UHAST,
BHAST,
85/85
(1000 cycles)
Repeatedly cycled
between -55° C and
+125° C in an air
environment
45 parts/lot
2-3 lots
Design, Foundry
Process, Package
Qualification
150° C, at 168, 500,
1000 hours
77/lot
2-3 lots
Design, Foundry
Process, Package
Qualification
2 atm. Pressure,
96 hrs, 130 C,
85% Relative Humidity
45 parts/lot
2-3 lots
Foundry Process,
Package Qualification
Plastic Packages only
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
8
TEST
STANDARD
TEST CONDITIONS
Moisture
Resistance
Temperature
Humidity Bias
85/85
THBS
Lattice Procedure
# 70-101571,
JESD22-A101B
Biased to maximum
operating Vcc, 85° C,
85% Relative Humidity,
1000 hours
or
Biased HAST
BHAST
Physical
Dimensions
Wire Bond
Strength
Solderability
SAMPLE SIZE
PERFORMED ON
(Typ)
45 devices/lot Design, Foundry
2-3 lots
Process, Package
Qualification
Plastic Packages only
JESD22-A110B
Lattice Procedure
# 70-100211,
MIL-STD- 883
Method 2016 or
applicable LSC case
outline drawings
Lattice Procedure
# 70-100220
or
Biased to maximum
operating Vcc, 2atm.
Pressure,
96 hrs, 130 C,
85% Relative Humidity
Measure all dimensions
listed on the case
outline.
5 devices
Package Qualification
Per package type
15 devices per Design, Foundry
pkg. per year Process, Package
Qualification
Lattice Procedure
Steam Pre-conditioning
22 leads/
All packages except
# 70-100212,
4-8 hours. Solder dip
3 devices/
BGAs
MIL-STD-883, Method at 245°C+5°C
Package family
2003
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
9
3.0 QUALIFICATION DATA FOR ispPAC-POWR PRODUCT FAMILY
The ispPAC-POWR product family is built on the 0.35um EE8A Electrically Erasable (E2 cell based) CMOS
process at United Microelectronics Company (UMC) and assembled at ASEM, Amkor and UNISEM, in TQFP and
QFNS packages. To verify product reliability, Lattice Semiconductor maintains an active Early Life and Inherent
Life Reliability Monitor program on the ispPAC-POWR products.
3.1 ispPAC-POWR Product Family Life Data
High Temperature Operating Life (HTOL) Test
The High Temperature Operating Life test is used to thermally accelerate those wear out and failure mechanisms
that would occur as a result of operating the device continuously in a system application. Consistent with JEDEC
JESD22-A108 “Temperature, Bias, and Operating Life”, a pattern specifically designed to exercise the maximum
amount of circuitry is programmed into the device and this pattern is continuously exercised at specified voltages
as described in test conditions for each device type.
EE8A Life Test (HTOL) Conditions:
Stress Duration: 168, 500, 1000 hours
Temperature: 125°C
Stress Voltage ispPAC-POWR: VCC = 3.6V
Preconditioned: 100 program/erase cycles
Method: Lattice Document # 87-101943 and JESD22-A108C
Table 3.1.1 ispPAC-POWR Product Family HTOL Results
24 Hrs
Result
48 Hrs 168 Hrs 500 Hrs 1000 Hrs Cumulative
Result Result
Result
Result
Hours
0
0
0
76,000
Product Name
Foundry Lot #
LA-ispPAC-POWR1014A UMC
Lot #1
Qty
76
LA-ispPAC-POWR1014A
UMC
Lot #5
77
0
LA-ispPAC-POWR1014A
UMC
Lot #7
77
0
LA-ispPAC-POWR1014A
UMC
Lot #8
77
LA-ispPAC-POWR1014A
UMC
Lot #9
75
LA-ispPAC-POWR1014A
UMC
Lot #10
77
LA-ispPAC-POWR1014A
UMC
Lot #1
799
0
19,176
LA-ispPAC-POWR1014A
UMC
Lot #5
797
0
19,128
LA-ispPAC-POWR1014A
UMC
Lot #7
813
0
19,512
LA-ispPAC-POWR1014A Epson
Lot #11
77
LA-ispPAC-POWR1014A Epson
Lot #12
77
ispPAC-POWR1220AT8
Epson
Lot #1
77
0
0
0
77,000
ispPAC-POWR1220AT8
Epson
Lot #2
77
0
0
0
77,000
ispPAC-POWR1220AT8
Epson
Lot #3
77
0
0
0
77,000
ispPAC-POWR1220AT8
Epson
Lot #4
26
0
0
0
26,000
ispPAC-POWR1220AT8
Epson
Lot #5
26
0
0
0
26,000
ispPAC-POWR1220AT8
Epson
Lot #6
26
0
0
0
26,000
ispPAC-POWR1220AT8
Epson
Lot #7
26
0
0
0
26,000
ispPAC-POWR1220AT8
Epson
Lot #1
796
0
38,208
ispPAC-POWR1220AT8
Epson
Lot #2
800
0
38,400
ispPAC-POWR1220AT8
Epson
Lot #3
799
0
38,352
0
0
77,000
0
0
0
77,000
0
0
0
75,000
0
0
0
77,000
12,936
0
38,500
0
38,500
EE8A Cumulative Device Hours = 927,712
EE8A Cumulative Sample Size = 0 / 5,752
INDEX return
UMC EE8A Cumulative Device Hours = 452,752
UMC EE8A FIT Rate = 26 FIT (55C, 0.7ev, 60%UCL)
UMC EE8A ELFR Cumulative Results = 0 / 2,868
Epson EE8A Cumulative Device Hours = 526,960
Epson EE8A FIT Rate = 22 FIT (55C, 0.7ev, 60%UCL)
Epson EE8A ELFR Cumulative Results = 0 / 2,884
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
10
3.2 ispPAC-POWR Product Family High Temperature Data Retention (HTRX)
High Temperature Data Retention (HTRX)
The High Temperature Data Retention test measures the Electrically Erasable cell (E2 cell) reliability while the
High Temperature Operating Life test is structured to measure functional operating circuitry failure mechanisms.
The High Temperature Data Retention test is specifically designed to accelerate charge gain on to or charge loss
off of the floating gates in the device's array. Since the charge on these gates determines the actual pattern and
function of the device, this test is a measure of the reliability of the device in retaining programmed information. In
High Temperature Data Retention, the E2 cell reliability is determined by monitoring the cell margin after biased
static operation at 150°C. All cells in all arrays are life tested in both programmed and erased states.
Data Retention (HTRX) Conditions:
Stress Duration: 168, 500, 1000 hours
Temperature: 150°C
Stress Voltage ispPAC-POWR: V CC = 3.6V
Preconditioned with 100 program/erase cycles
Method: Lattice Document # 87-101925 and JESD22-A103C/JESD22-A117A
Table 3.2.1 ispPAC-POWR High Temperature Data Retention (HTRX) Results
Product Name
LA-ispPAC-POWR1014A
Foundry
UMC
Lot #
Lot #1
Qty
77
168 Hrs
Result
0
500 Hrs
Result
0
1000 Hrs
Result
0
Cumulative Hours
77,000
LA-ispPAC-POWR1014A
UMC
Lot #2
77
0
0
0
77,000
LA-ispPAC-POWR1014A
UMC
Lot #3
77
0
0
0
77,000
LA-ispPAC-POWR1014A
Epson
Lot #11
78
0
0
39,000
LA-ispPAC-POWR1014A
Epson
Lot
#13 A
39
0
19,500
LA-ispPAC-POWR1014A
Epson
Lot #14 B
39
0
19,500
ispPAC-POWR1220AT8
Epson
Lot #1
26
0
0
0
77,000
ispPAC-POWR1220AT8
Epson
Lot #2
77
0
0
0
77,000
ispPAC-POWR1220AT8
Epson
Lot #3
77
0
0
0
77,000
A
26
0
0
0
77,000
#9 B
26
0
0
0
77,000
ispPAC-POWR1220AT8
ispPAC-POWR1220AT8
A)
B)
Epson
Epson
Lot #8
Lot
Lot #8 and #13 is a thin tunnel oxide process split.
Lot #9 and #14 is a thick tunnel oxide process split.
Cumulative HTRX Failure Rate = 0 / 618
Cumulative HTRX Device Hours = 540,000
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
11
3.3 ispPAC-POWR Product Family Extended Endurance (EE)
Extended Endurance (EE)
Extended Endurance testing measures the durability of the device through programming and erase cycles.
Extended Endurance testing consists of repeatedly programming and erasing all E2 cells in the array at 25°C to
simulate programming cycles the user would perform. This test evaluates the integrity of the thin tunnel oxide
through which current passes to program the floating gate in each cell of the array..
Extended Endurance (EE) Conditions:
Stress Duration: 1000 cycles
Temperature: 25°C
Stress Voltage ispPAC-POWR: V CC = 3.6V
Method: Lattice Document # 70-104633 and JESD22-A117B
Table 3.3.1 ispPAC-POWR Extended Endurance (EE) Results
Product Name
ispPAC-POWR1220AT8
Foundry
Epson
Lot #
Lot #1
Quantity
10
0 Cycles
Result
0
1000 Cycles
Result
0
ispPAC-POWR1220AT8
Epson
Lot #2
10
0
0
ispPAC-POWR1220AT8
Epson
Lot #3
10
0
0
Epson
Lot
#8 A
10
0
0
#9 B
10
0
0
10
0
0
Lot
#13 A
5
0
0
Lot
#14 B
5
0
0
ispPAC-POWR1220AT8
ispPAC-POWR1220AT8
Epson
Lot
ispPAC-POWR1014A
Epson
Lot #11
ispPAC-POWR1014A
ispPAC-POWR1014A
A)
B)
Epson
Epson
Lot #8 and #13 is a thin tunnel oxide process split.
Lot #9 and #14 is a thick tunnel oxide process split.
Cumulative EE Failure Rate = 0 / 70
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
12
3.4 ispPAC-POWR Product Family - ESD and Latch UP Data
Electrostatic Discharge-Human Body Model:
ispPAC-POWR product family was tested per the JESD22-A114E Electrostatic Discharge (ESD) Sensitivity
Testing Human Body Model (HBM) procedure and Lattice Procedure # 70-100844.
All units were tested at 250C prior to reliability stress and after reliability stress. No failures were observed within
the passing classification.
Table 3.4.1 ispPAC-POWR ESD-HBM Data
Product
Foundry
24-QFNS
32-QFNS
48-TQFP
100-TQFP
POWR1220AT8
UMC
N/A
N/A
N/A
>2000V
Class 2
POWR1014A
UMC
N/A
N/A
>2000V
Class 2
N/A
POWR1014
UMC
N/A
N/A
>2000V
Class 2
N/A
POWR6AT6
UMC
N/A
>2000V
Class 2
N/A
N/A
POWR607
UMC
N/A
>2000V
Class 2
N/A
N/A
POWR605
UMC
>2000V
Class 2
N/A
N/A
N/A
HBM classification for Commercial/Industrial products, per JESD22-A114E
Product
Foundry
24-QFNS
32-QFNS
48-TQFP
100-TQFP
POWR607
Epson
N/A
>2000V
Class 2
N/A
N/A
POWR1014
Epson
N/A
N/A
>2000V
Class 2
N/A
POWR1220AT8
Epson
N/A
N/A
N/A
>2000V
Class 2
HBM classification for Commercial/Industrial products, per JESD22-A114E
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
13
Electrostatic Discharge-Charged Device Model:
ispPAC-POWR product family was tested per the JESD22-C101D, Field-Induced Charged-Device Model Test
Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components procedure and Lattice
Procedure # 70-100844.
All units were tested at 250C prior to reliability stress and after reliability stress. No failures were observed within
the passing Classification.
Table 3.4.2 ispPAC-POWR ESD-CDM Data
Product
Foundry
24-QFNS
32-QFNS
48-TQFP
100-TQFP
POWR1220AT8
UMC
N/A
N/A
N/A
>1000V
Class IV
POWR1014A
UMC
N/A
N/A
>1000V
Class IV
N/A
POWR1014
UMC
N/A
N/A
>1000V
Class IV
N/A
POWR6AT6
UMC
N/A
>1000V
Class IV
N/A
N/A
POWR607
UMC
N/A
>1000V
Class IV
N/A
N/A
POWR605
UMC
>1000V
Class IV
N/A
N/A
N/A
CDM classification for Commercial/Industrial products, per JESD22-C101D
Product
Foundry
24-QFNS
32-QFNS
48-TQFP
100-TQFP
POWR607
Epson
N/A
>1000V
Class IV
N/A
N/A
POWR1014A
Epson
N/A
N/A
>1000V
Class IV
N/A
POWR1220AT8
Epson
N/A
N/A
N/A
>1000V
Class IV
CDM classification for Commercial/Industrial products, per JESD22-C101D
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
14
Latch-Up:
ispPAC-POWR product family was tested per the JEDEC EIA/JESD78A IC Latch-up Test procedure and Lattice
Procedure # 70-101570.
All units were tested at 250C and +1050C prior to reliability stress and after reliability stress. No failures were
observed within the passing classification.
Earlier latch-up testing at Lattice was hardware limited to room temperature testing. Additionally, maxi mum-rated
ambient temperature latch-up testing is generally considered to be approximately 2X worse than the trigger
values found at room temperature. In order to guard band our room temperature IO latch-up testing the standard
was 4X, or +/- 400mA trigger current. Therefore, the previous Lattice I/O LU standard was >400mA at room
temperature, while the present standard is >100mA at maximum-rated ambient temperature.
Table 3.4.3 ispPAC-POWR I/O Latch Up Data
Product
Foundry
24-QFNS
32-QFNS
48-TQFP
100-TQFP
POWR1220AT8
UMC
N/A
N/A
N/A
>+/- 400mA
at room temp
POWR1014A
UMC
N/A
N/A
>+/- 100mA
Class II, Level A
N/A
POWR1014
UMC
N/A
N/A
>+/- 100mA
Class II, Level A
N/A
POWR6AT6
UMC
N/A
>+/- 400mA
at room temp
N/A
N/A
POWR607
UMC
N/A
>+/- 400mA
at room temp
N/A
N/A
POWR605
UMC
>+/- 400mA
at room temp
N/A
N/A
N/A
Product
Foundry
24-QFNS
32-QFNS
48-TQFP
100-TQFP
POWR607
Epson
POWR1014A
Epson
POWR1220AT8
Epson
>+/- 100mA
Class II, Level A
>+/- 100mA
Class II, Level A
N/A
N/A
N/A
>+/- 100mA
Class II, Level A
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
15
4.0 PACKAGE QUALIFICATION DATA FOR ispPAC-POWR PRODUCT
FAMILY
The ispPAC-POWR product family is offered in TQFP and QFNS packages. To cover the range of die in the
largest package types for this product family, different package and die combinations were chosen as the generic
qualification vehicles for all the package qualification tests including, Temperature Cycling (T/C), Un-biased
HAST (UHAST)and Biased HAST (BHAST). Mechanical evaluation tests include Scanning Acoustic Tomography
(SAT) and visual package inspection.
The generation and use of generic data is applied across a family of products or packages emanating from one
base wafer foundry or assembly process is a Family Qualification, or Qualification By Extension. For the package
stresses BHAST and UHAST, these are considered generic for a given Package Technology. T/C is considered
generic up to an evaluated die size + package size + 10%, for a given Package Technology. Surface Mount Pre Conditioning (SMPC) is considered generic up to an evaluated Peak Reflow temperature, for a given Package
Technology. The following table demonstrates the package qualification matrix.
Table 4.1 ispPAC-POWR Product-Package Qualification-By-Extension Matrix
Product-Package
Qualification Matrix
Product
POWR1220AT8
POWR1014A
POWR1014
POWR6AT6
POWR607
POWR605
Unisem
Stress Test
SMPC
Temp Cycle
BHAST
UHAST
(5) HTSL
SMPC
Temp Cycle
BHAST
UHAST
(5) HTSL
SMPC
Temp Cycle
BHAST
UHAST
(5) HTSL
SMPC
Temp Cycle
BHAST
UHAST
HTSL
SMPC
Temp Cycle
BHAST
UHAST
HTSL
SMPC
Temp Cycle
BHAST
UHAST
HTSL
24-QFNS
ASEM / Amkor / Unisem
32-QFNS
Package not offered
Package not offered
MSL1, 260C
1000 cycles
(3) By Extension
96 hours
(3) By Extension
(4) By Extension
(4) By Extension
(3) By Extension
(3) By Extension
(3) By Extension
Package not
offered
(4) By Extension
(4) By Extension
(3) By Extension
(3) By Extension
(3) By Extension
Package not
offered
100-TQFP
Package not
offered
MSL3, 260C
1000 cycles
96 hours
96 hours
1000 hours
MSL3, 260C
1000 cycles
96 hours
96 hours
1000 hours
(2) By Extension
(2) By Extension
(2) By Extension
(2) By Extension
(2) By Extension
Package not offered
Package not
offered
48-TQFP
Package not
offered
Package not
offered
Package not offered
Package not offered
Package not offered
Note: (1) By Extension from LA-Mach4000, 144-TQFP.
(2) By Extension from POWR1014A, 48TQFP.
(3) By Extension from GAL22V10D, 32QFNS.
(4) By Extension from POWR6AT6, 32-QFNS.
(5) Some HTSL data covered by extension from various HTOL data.
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
16
4.1 ispPAC-POWR Product Family Surface Mount Preconditioning Testing
The Surface Mount Preconditioning (SMPC) Test is used to model the surface mount assembly conditions during
component solder processing. All devices stressed through Temperature Cycling, Un-biased HAST and Biased
HAST were preconditioned. This preconditioning is consistent with JEDEC JESD22-A113F “Preconditioning
Procedures of Plastic Surface Mount Devices Prior to Reliability Testing”, Moisture Sensitivity Level 3 (MSL3)
package moisture sensitivity and dry-pack storage requirements.
Consistent with Lattice Semiconductor Corp. document # 25-100164, package reliability testing can be qualified
by extension. Once a package outline is qualified within a package grouping as per doc #70-103639, all lower
lead count (and smaller body size) packages within that package type and assembly technology are qualified by
extension. Additionally, once an assembly technology has been qualified for one package type, that package type
shall be qualified by extension to all future fabrication processes as long as those processes continue to use the
same critical elements. Those critical elements in this case, are that the process-to-process interlayer dielectric
material and thickness differences do not exceed the current production process limits for the qualification vehicle
used. For 180nm and older technologies, the critical elements are considered equivalent.
Surface Mount Preconditioning (MSL3)
(10 Temperature Cycles between -55°C and 125°C, 24 hours bake @ 125°C, 30°C/60% RH, soak 192 hours,
Reflow Simulation, 3 passes) performed before all EE9 package tests.
MSL3 Packages: TQFP
Surface Mount Preconditioning (MSL1)
(10 Temperature Cycles between -55°C and 125°C, 24 hr. bake @ 125°C, 85°C/85%RH soak, 168 hrs, 260C
Reflow Simulation, 3 passes)
MSL1 Packages: QFNS
Method: Lattice Procedure # 70-103467, J-STD-020D.1 and JESD22-A113F
Table 4.1.1 Surface Mount Precondition Data
Assembly
Lot
Site
Number
Product Name
Package
LA-ispPAC-POWR1014A
LA-ispPAC-POWR1014A
ASEM
ASEM
Lot #1
Lot #2
LA-ispPAC-POWR1014A
48 TQFP
48 TQFP
48 TQFP
ASEM
LA-ispPAC-POWR1014A
48 TQFP
LA-ispPAC-POWR1014A
Reflow
Quantity # of Fails Temperature
260°C
81
0
81
0
Lot #3
81
0
260°C
260°C
ASEM
Lot #4
156
0
260°C
48 TQFP
ASEM
Lot #5
156
0
260°C
LA-ispPAC-POWR1014A
48 TQFP
ASEM
Lot #6
156
0
260°C
LA-ispPAC-POWR1014A
48 TQFP
ASEM
Lot #11
77
0
260°C
LA-ispPAC-POWR1014A
48 TQFP
ASEM
Lot #12
77
0
260°C
ispPAC-POWR1208
44 TQFP
ASEM
Lot #1
45
0
260°C
ispPAC-POWR1208
44 TQFP
ASEM
Lot #2
45
0
260°C
ispPAC-POWR604
44 TQFP
ASEM
Lot #1
48
0
260°C
ispPAC-POWR604
44 TQFP
ASEM
Lot #2
48
0
260°C
GAL22V10D
32 QFNS
Unisem
Lot #1
154
0
260°C
GAL22V10D
32 QFNS
Unisem
Lot #2
154
0
260°C
GAL22V10D
32 QFNS
Unisem
Lot #3
154
0
260°C
POWR6AT6
32 QFNS
Unisem
Lot #4
77
0
260°C
POWR6AT6
32 QFNS
Unisem
Lot #5
77
0
260°C
ispPAC-POWR1208
44 TQFP
Unisem
Lot #1
77
0
260°C
ispPAC-POWR1208
44 TQFP
Unisem
Lot #1
77
0
260°C
ispPAC-POWR1208
44 TQFP
Unisem
Lot #1
77
0
260°C
ispMACH 4512
176TQFP
Unisem
Lot#1
99
0
260°C
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
17
Product Name
ispMACH 4512
Package
176TQFP
Assembly
Lot
Site
Number
Unisem
Lot#2
Reflow
Quantity # of Fails Temperature
260°C
98
0
ispMACH 4512
176TQFP
Unisem
Lot#3
75
0
260°C
LA4128V
144 TQFP
ASEM
Lot #1
234
0
260°C
LA4128V
144 TQFP
ASEM
Lot #2
231
0
260°C
LA4128V
144 TQFP
ASEM
Lot #3
234
0
260°C
LA4128V
144 TQFP
Amkor
Lot #1
81
0
260°C
LA4128V
144 TQFP
Amkor
Lot #2
82
0
260°C
LA4128V
144 TQFP
Amkor
Lot #3
78
0
260°C
LA4128V
144 TQFP
Amkor
Lot #4
162
0
260°C
LA4128V
144 TQFP
Amkor
Lot #5
200
0
260°C
LA4128V
144 TQFP
Amkor
Lot #6
200
0
260°C
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #1
314
0
260°C
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #2
314
0
260°C
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #3
314
0
260°C
Cumulative SMPC Failure Rate = 0 / 4,614
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
18
4.2 ispPAC-POWR Product Family Temperature Cycling Data
The Temperature Cycling test is used to accelerate those failures resulting from mechanical stresses induced by
differential thermal expansion of adjacent films, layers and metallurgical interfaces in the die and package.
Devices are tested at 25°C after exposure to repeated cycling between -55°C and +125°C in an air environment
consistent with JEDEC JESD22-A104C “Temperature Cycling”, Condition B temperature cycling requirements.
Prior to Temperature Cycling testing, all devices are subjected to Surface Mount Preconditioning.
MSL3 Packages: TQFP
MSL1 Packages: QFNS
Stress Duration: 1000 cycles
Stress Conditions: Temperature cycling between -55°C to 125°C
Method: Lattice Procedure # 70-101568 and JESD22-A104C
Table 4.2.1 Temperature Cycling Data
Product Name
Package
LA-ispPAC-POWR1014A 48 TQFP
LA-ispPAC-POWR1014A 48 TQFP
Assembly
Lot
Site
Number
Quantity
250
Cycles
500
Cycles
1000
Cycles
ASEM
Lot #4
77
0
0
0
ASEM
Lot #5
77
0
0
0
LA-ispPAC-POWR1014A
48 TQFP
ASEM
Lot #6
77
0
0
0
LA-ispPAC-POWR1014A
48 TQFP
ASEM
Lot #11
77
LA-ispPAC-POWR1014A
48 TQFP
ASEM
Lot #12
76B
ispPAC-POWR1208
44 TQFP
ASEM
Lot #1
42
0
0
0
ispPAC-POWR1208
44 TQFP
ASEM
Lot #2
45
0
0
0
ispPAC-POWR604
44 TQFP
ASEM
Lot #1
48
0
0
0
ispPAC-POWR604
44 TQFP
ASEM
Lot #2
48
0
0
0
POWR6AT6
32 QFNS
Unisem
Lot #4
77
0
0
0
POWR6AT6
32 QFNS
Unisem
Lot #5
77
0
0
0
ispPAC-POWR1208
44 TQFP
Lot #1
77
0
0
0
ispPAC-POWR1208
44 TQFP
Unisem
Unisem
Lot #1
77
0
0
0
ispPAC-POWR1208
44 TQFP
Unisem
Lot #1
77
0
0
0
ispMACH 4512
176TQFP
Unisem
Lot#1
50
0
0
0
ispMACH 4512
176TQFP
Unisem
Lot#2
49
0
0
0
ispMACH 4512
LA4128V
176TQFP
Unisem
Lot#3
45
0
0
0
144 TQFP
ASEM
Lot #1
77
0
0
0
LA4128V
144 TQFP
ASEM
Lot #2
77
0
0
0
LA4128V
0
0
144 TQFP
ASEM
Lot #3
77
0
0
0
LA4128V
144 TQFP
Amkor
Lot #1
81
0
0
0
LA4128V
144 TQFP
Amkor
Lot #2
82
0
0
0
0
0
0
LA4128V
144 TQFP
Amkor
Lot #3
78
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #1
83
0
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #2
83
0
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #3
83
1A
A)
B)
1 unit fails margin & checkerboard for adjacent bit failure. Not package stress related.
1 unit lost by handler. Sample size reduced by one.
Cumulative Temp Cycle Failure Rate = 1 / 1,817
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
19
4.3 Unbiased HAST Data
Unbiased Highly Accelerated Stress Test (HAST) testing uses both pressure and temperature to accelerate
penetration of moisture into the package and to the die surface. The Unbiased HAST test is designed to detect
ionic contaminants present within the package or on the die surface, which can cause chemical corrosion.
Consistent JEDEC JESD22-A118, “Accelerated Moisture Resistance - Unbiased HAST,” the Unbiased HAST
conditions are 96 hour exposure at 130°C, 85% relative humidity, and 2 atmospheres of pressure. Prior to
Unbiased HAST testing, all devices are subjected to Surface Mount Preconditioning.
MSL3 Packages: TQFP
MSL1 Packages: QFNS
Stress Duration: 96 Hrs
Stress Conditions: 130°C, 15psig, 85% RH
Method: Lattice Procedure # 70-104285 and JESD22-A118
Table 4.3.1 Unbiased HAST Data
Product Name
Package
LA-ispPAC-POWR1014A 48 TQFP
LA-ispPAC-POWR1014A
48 TQFP
Assembly
Lot
Site
Number
ASEM
Lot #4
Quantity
77
# of
Fails
0
Stress
Duration
96 Hrs
ASEM
Lot #5
77
0
96 Hrs
LA-ispPAC-POWR1014A
48 TQFP
ASEM
Lot #6
77
0
96 Hrs
GAL22V10D
32 QFNS
Unisem
Lot #1
77
0
96 Hrs
GAL22V10D
32 QFNS
Unisem
Lot #2
77
0
96 Hrs
GAL22V10D
32 QFNS
Unisem
Lot #3
77
0
96 Hrs
ispMACH 4512
176TQFP
Unisem
Lot#1
49
0
96 Hrs
ispMACH 4512
176TQFP
Unisem
Lot#2
49
0
96 Hrs
ispMACH 4512
176TQFP
Unisem
Lot#3
30
0
96 Hrs
LA4128V
144 TQFP
ASEM
Lot #1
77
0
96 Hrs
LA4128V
144 TQFP
ASEM
Lot #2
75
0
96 Hrs
LA4128V
144 TQFP
ASEM
Lot #3
77
0
96 Hrs
LA4128V
144 TQFP
Amkor
Lot #4
81
0
96 Hrs
LA4128V
144 TQFP
Amkor
Lot #5
100
0
96 Hrs
LA4128V
ispPAC-POWR1220AT8
144 TQFP
Amkor
Lot #6
100
0
96 Hrs
100 TQFP
ASEM
Lot #1
77
0
96 Hrs
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #2
77
0
96 Hrs
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #3
77
0
96 Hrs
Cumulative Unb iased HAST failure Rate = 0 / 1,331
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
20
4.4 THB: Biased HAST Data
Highly Accelerated Stress Test (HAST) testing uses both pressure and temperature to accelerate penetration of
moisture into the package and to the die surface. The Biased HAST test is used to accelerate threshold shifts in
the MOS device associated with moisture diffusion into the gate oxide region as well as electrochemical corrosion
mechanisms within the device package. Consistent with JEDEC JESD22-A110B “Highly-Accelerated
Temperature and Humidity Stress Test (HAST)”, the biased HAST conditions are wit h Vcc bias and alternate pin
biasing in an ambient of 130°C, 85% relative humidity, and 2 atmospheres of pressure. Prior to Biased HAST
testing, all devices are subjected to Surface Mount Preconditioning.
MSL3 Packages: TQFP
MSL1 Packages: QFNS
Stress Conditions: ispPAC-POWR - Vcc= 4.0 V, 130°C / 85% RH, 15 psig
Stress Conditions: GAL22V10D - Vcc= 5.0 V, 130°C / 85% RH, 15 psig
Stress Duration: 96 hours
Method: Lattice Procedure # 70-101571 and JESD22-A110B
Table 4.4.1 Biased HAST Data
Product Name
Package
LA-ispPAC-POWR1014A 48 TQFP
Assembly
Lot
Site
Number
ASEM
Lot #4
Quantity
80
# of
Fails
0
Stress
Duration
96 Hrs
LA-ispPAC-POWR1014A
48 TQFP
ASEM
Lot #5
80
0
96 Hrs
LA-ispPAC-POWR1014A
48 TQFP
ASEM
Lot #6
80
0
96 Hrs
GAL22V10D
32 QFNS
Unisem
Lot #1
77
0
96 Hrs
GAL22V10D
32 QFNS
Unisem
Lot #2
77
0
96 Hrs
GAL22V10D
32 QFNS
Unisem
Lot #3
77
0
96 Hrs
LA4128V
144 TQFP
ASEM
Lot #1
80
0
96 Hrs
LA4128V
144 TQFP
ASEM
Lot #2
77
0
96 Hrs
LA4128V
144 TQFP
ASEM
Lot #3
80
0
96 Hrs
LA4128V
144 TQFP
Amkor
Lot #4
81
0
96 Hrs
LA4128V
144 TQFP
Amkor
Lot #5
100
0
96 Hrs
LA4128V
144 TQFP
Amkor
Lot #6
100
0
96 Hrs
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #1
77
0
96 Hrs
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #2
77
0
96 Hrs
ispPAC-POWR1220AT8
100 TQFP
ASEM
Lot #3
77
0
96 Hrs
Cumulative BHAST failure Rate = 0 / 1,220
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
21
4.5 HTSL: High Temperature Storage Life Data
High Temperature storage test is typically used to determine the effect of time and temperature, under storage
conditions, for thermally activated failure mechanisms of solid state electronic devices. Units were stressed per
JESD22-A103C, High Temperature Storage Life. Prior to Unbiased HAST testing, all Pb-free devices are
subjected to Surface Mount Preconditioning.
The High Temperature Storage Life units were stressed at 150°C.
High Temperature Storage Life (HTSL) Conditions:
Stress Duration: 168, 500, 1000, hours.
Temperature: 150°C
Method: Lattice Document # 87-101925 and JESD22-A103C
Table 4.5.1 High Temperature Storage Life Results
Product Name
Assembler
Package
Lot #
Qty
168 Hrs
Result
500 Hrs 1000 Hrs
Result
Result
Cumulative
Hours
LA-ispPAC-POWR1014A
ASEM
100 TQFP
Lot #2
50
0
0
0
50000
LA-ispPAC-POWR1014A
ASEM
100 TQFP
Lot #4
77
0
0
0
77000
LA-ispPAC-POWR1014A
ASEM
100 TQFP
Lot #5
77
0
0
0
77000
LA-ispPAC-POWR1014A
ASEM
100 TQFP
Lot #8
77
0
0
0
77000
LA-ispPAC-POWR1014A
ASEM
100 TQFP
Lot #9
77
0
0
0
77000
LA-ispPAC-POWR1014A
ASEM
100 TQFP Lot #10
77
0
0
0
77000
GAL22V10D
UNISEM
32 QFNS
Lot #1
77
0
77000
GAL22V10D
UNISEM
32 QFNS
Lot #2
77
0
77000
GAL22V10D
UNISEM
32 QFNS
Lot #3
77
0
77000
ispPAC-POWR1220AT8
ASEM
100 TQFP
Lot #1
77
0
77,000
ispPAC-POWR1220AT8
ASEM
100 TQFP
Lot #2
77
0
77,000
ispPAC-POWR1220AT8
ASEM
100 TQFP
Lot #3
77
0
77,000
Cumulative HTSL Failure Rate = 0 / 897
Cumulative HTSL Device Hours = 897,000
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
22
5.0 ispPAC-POWR PROCESS RELIABILITY WAFER LEVEL REVIEW
The ispPAC-POWR product family is built on EE8A which is a 3.3V shallow trench isolated, 0.35um drawn /
0.25um Leff CMOS process with Electrically Erasable (E2) cells. This process uses three planarized metal
interconnect layers and single layer polysilicon fabricated at either United Microelectronics Company (UMC), or
Epson Sakata.
Several key fabrication process related parameters have been identified by the foundry that would affect the
Reliability of the End-Product. These parameters are tested during the Development Phase of the Technology.
Passing data (a 10yr lifetime at the reliability junction temperature) must be obtained for three lots minimum for
each parameter before release to production. Normal operating conditions are defined in the Electrical Design
Rules (EDR). These parameters are:
Hot Carrier Immunity (HCI): Effect is a reduction in transistor Idsat. Worst case is low temperature.
Time Dependent Dielectric Breakdown (TDDB): Transistor and capacitor oxide shorts or leakage.
Negative Bias Temperature Instability (NBTI): Symptom is a shift in Vth (also a reduction in Idsat).
Electromigration Lifetime (EML): Symptom is opens within, or shorts between, metal conductors.
Stress Migration (SM): Symptom is a void (open) in a metal Via due to microvoid coalescence. SM is not an
issue for the EE8A BEOL (etched Al lines, W plug Vias, SiO IMD).
Table 5.1 UMC Foundry Wafer Level Reliability Results for EE8A (0.35um) Process Technology
HCI
TDDB
EML
Device
LVN
LVP
deltaIds
-10%
-10%
Celsius
25
25
Vgstress
Vd/2
0
Vds
DC-HCI
TTF
>1yr
3.6
-3.6
5 lots >
32 yr
1 lot >
1e6yr
Device
LVN
MIM
Celsius
130
130
Vg
3.3
20
Area
8000um^2
2.25e4um^2
0.1%
TTF
1.4e5yr
>1e6yr
Layer
M1
M2
M3
Celsius
130
130
130
Delta R
+20%
+20%
+20%
Jmax
1.0mA/um
1.4mA/um
1.4mA/um
0.1%
TTF
3 lots >
11yr
3 lots >
11yr
2 lots >
16yr
Note: Reliability life times are based on listed temperature and use conditions. Detailed WLR test conditions are available upon request.
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
23
Hot Carrier Immunity (HCI): Effect is a reduction in transistor Idsat. Worst case is low temperature.
Time Dependent Dielectric Breakdown (TDDB): Transistor and capacitor oxide shorts or leakage.
Negative Bias Temperature Instability (NBTI): Symptom is a shift in Vth (also a reduction in Idsat).
Electromigration Lifetime (EML): Symptom is opens within, or shorts between, metal conductors.
Stress Migration (SM): Symptom is a void (open) in a metal Via due to microvoid coalescence. SM is not an
issue for the EE8A BEOL (etched Al lines, W plug Vias, SiO IMD).
Table 5.2 Epson Foundry Wafer Level Reliability Results for EE8A (0.35um) Process Technology
HCI
TDDB
EML
Device
LVN
LVP
deltaIds
-10%
-10%
Celsius
25
25
Vgstress
Vd/2
0
Vds
DC-HCI
TTF
>1yr
3.6
-3.6
3 lots >
5.5yr
2 lots >
8.2e3yr
Device
LVN
MIM
Celsius
130
130
Vg
3.3
15
Area
8000um^2
2.25e4um^2
0.1%
TTF
3 lots >
2.8e3yr
3 lots >
2.1e3yr
Layer
M1
M2
M3
Celsius
130
130
130
Delta R
+20%
+20%
+20%
Jmax
1.0mA/um
1.4mA/um
1.4mA/um
0.1%
TTF
3 lots >
22.4yr
3 lots >
30.5yr
3 lots >
16.2yr
Note: Reliability life times are based on listed temperature and use conditions. Detailed WLR test conditions are available upon request.
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
24
6.0 ispPAC-POWR PACKAGE ASSEMBLY INTEGRITY TESTS
6.1 Wire Bond Shear Test
This procedure is used to measure the wire bond strength at the ball joints. Thirty bonds from a minimum of five
devices were used for Wire Bond Shear.
WIRE BOND SHEAR TEST RESULTS: All bond shear observations were > 20 grams for TQFP pack ages
tested.
The average measured bond shear results for TQFP were Cpk of > 4.76 and Ppk of > 4.8.
6.2 Wire Bond Pull
This procedure is used to measure the wire bond strength at the ball joints and stitch bonds.
For products evaluation thirty bonds from a minimum of five devices were used for and Wire Bond Pull. Test
conditions for these tests were 6 grams minimum for 1.0 mil gold wire
WIRE BOND PULL RESULTS: All bond pull observations were >4 grams for TQFP packages tested.
The average measured wire bond pull results for TQFP were Cpk of > 1.39.
6.3 Solderability
This procedure is used to evaluate the solderability of device terminals normally joined by a soldering operation.
An accelerated aging test is included in this test method, which simulates natural aging under a combination of
various storage conditions that have deleterious effects. Units are exposed to a 8 hour steam preconditioning
followed a flux exposure for 7 seconds and a dip in Pb-free solder alloy @ 260 °C ± 5°C for 5 seconds. Minimum
of 22 leads from 3 devices per lot were tested with zero failure acceptance.
No failures were observed for TQFP packages. All the tested units passed. There was less than 5% pitting and
dewetting on the solder covered area.
No failures were observed for QFNS packages. All the tested units passed. There was less than 5% pitting and
dewetting on the solder covered area.
6.4 Physical Dimensions
Devices were measured using the appropriate Lattice Semiconductor case outline drawings.
The 10 devices of TQFP from 3 different lots were measured with no failures found. The calculated Cpk on this
small sample is Cpk > 2.0.
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
25
7.0 ispPAC-POWR ADDITIONAL FAMILY DATA
Table 7.1 ispPAC-POWR Package Assembly Data- TQFP/QFNS
Package Attributes /
Assembly Sites
Die Family (Product Line)
Fabrication Process
Technology
Package Assembly Site
Package Type
Pin Count
Die Preparation/Singulation
Die Attach Material - TQFP
Die Attach Material - QFNS
Mold Compound
Supplier/ID - TQFP
Mold Compound
Supplier/ID - QFNS
Wire Bond Material
Wire Bond Methods
Lead frame Material
Lead Finish
Marking
ASEM
ispPAC-POWR
EE8A
(0.35um CMOS)
Malaysia
TQFP
Amkor
ispPAC-POWR
EE8A
(0.35um CMOS)
Korea
TQFP
48/100
48/100
wafer saw, full cut
Ablebond 3230
N/A
Hitachi CEL9220HF
Series
wafer saw, full cut
Ablebond 3230
N/A
KTMC 5700TQ
Series
N/A
N/A
Gold (Au)
Thermosonic Ball
Cu Alloy
Matte Sn (annealed)
Laser
Gold (Au)
Thermosonic Ball
Cu Alloy
Matte Sn (annealed)
Laser
Unisem
ispPAC-POWR
EE8A
(0.35um CMOS)
Indonesia
TQFP / QFNS
48/100
24/32
wafer saw, full cut
CRM1076NS
CRM 1066 Series
Sumitomo G700
Series
Sumitomo G770
Series
Gold (Au)
Thermosonic Ball
Cu Alloy
Matte Sn (annealed)
Laser
INDEX return
Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
26
8.0 REVISION HISTORY
Table 8.1 Lattice ispPAC-POWR Product Family Qualification Summary revisions
Date
August 2009
January 2010
Revision
A
B
Section
--4.1 SMPC
November 2011
C
Qualification data
sections 3, 4 & 5
December 2011
January 2012
D
E
August 2012
F
October 2012
March 2013
G
H
Revision History
Table 3.1
Qualification data
sections 3 & 4
Table 2.2
Change Summary
Initial document release.
Added Amkor QFNS MSL1 SMPC data.
Added Qualification data in support of PCN# 01A-12 in
sections 3, 4 and 5:
 In Section 3, see all data records for
Product Name = ispPAC-POWR1220AT8 and
Foundry = Epson
 In Section 4, see all data records for
Product Name = ispPAC-POWR1220AT8 and
Assembly Site = ASEM
 In Section 5, see all Wafer Level Reliability data in
Table 5.2 = Epson Foundry
Added revision history as a standard section.
Updated ispPAC-POWR1220AT8 HTOL device hours
Continuance Qualification data in support of PCN# 01A-12
in sections 3, 4
Administrative change to internal document.
Update program/erase cycles typo and Customer letter.
INDEX return
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Lattice Semiconductor Corporation Doc. #25-106672 Rev. H
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