Datasheet

THC63LVDF84B_Rev.5.11_E
THC63LVDF84B
24bit COLOR LVDS RECEIVER (Falling Edge Clock)
General Description
Features
The THC63LVDF84B receiver supports wide VCC range as
2.5 to 3.6V. At single 2.5V supply, the THC63LVDF84B
reduces EMI and power consumption.
The THC63LVDF84B converts the four LVDS data streams
back into 24bits of LVCMOS data with falling edge clock. At
a transmit clock frequency of 85MHz, 24bits of RGB data and
4bits of timing and control data (HSYNC, VSYNC, DE,
CNTL1, CNTL2) are transmitted at an effective rate of
2.38Gbps.
・1:7 LVDS to LVCMOS De-Serializer
・Operating Temperature Range : -10 to +70C
・No Special Start-up Sequence Required
・Spread Spectrum Clocking Tolerant up to 100kHz Frequency
Modulation and +/-2.5% Deviations.
・Dot Clock Range: 15 to 85MHz Suited for VGA, SVGA,
XGA, WXGA, 720p and 1080i.
・56pin TSSOP Package
・PLL requires no external components.
・Power Down Mode.
Application
・Falling Edge Clock
・EU RoHS Compliant.
・Medium and Small Size Panel
・Tablet PC / Notebook PC
・Security Camera / Industrial Camera
・Multi Function Printer
・Industrial Equipment
・Medical Equipment Monitor
Block Diagram
Figure 1. Block Diagram
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Pin Diagram
RC3
RD6
RC4
GND
RC5
RC6
RD0
LVDS GND
RARA+
RBRB+
LVDS VCC
LVDS GND
RCRC+
RCLKRCLK+
RDRD+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLKOUT
RA0
GND
1
2
3
56
55
54
●
53
52
51
50
49
4
5
6
7
8
9
48
47
46
45
10
11
12
13
14
44
43
42
41
40
15
16
17
18
39
38
37
36
35
19
20
21
22
23
34
33
32
31
30
29
24
25
26
27
28
VCC
RC2
RC1
RC0
GND
RB6
RD5
RD4
VCC
RB5
RB4
RB3
GND
RB2
RD3
RD2
VCC
RB1
RB0
RA6
GND
RA5
RD1
RA4
RA3
VCC
RA2
RA1
Figure 2. Pin Diagram
Pin Description
Pin Name
RA+, RARB+, RBRC+, RCRD+, RDRCLK+,
RCLKRA0 ~ RA6
RB0 ~ RB6
RC0 ~ RC6
RD0 ~ RD6
CLKOUT
Pin #
10, 9
12, 11
16, 15
20, 19
18, 17
Direction
Type
Input
LVDS
27, 29, 30, 32, 33, 35, 37
38, 39, 43, 45, 46, 47, 51
53, 54, 55, 1, 3, 5, 6
7, 34, 41, 42, 49, 50, 2
26
Output
/PDWN
25
Input
VCC
31, 40, 48, 56
GND
LVDS VCC
LVDS GND
4, 28, 36, 44, 52
13
8, 14, 21
PLL VCC
PLL GND
23
22, 24
Description
LVDS Data Inputs
LVDS Clock Inputs
Pixel Data Outputs
LVCOMS
Power
-
Pixel Clock Output
H : Normal Operation
L : Power Down (all outputs are pulled to ground)
Power Supply Pins for LVCMOS outputs and digital
circuitry
Ground Pins for LVCMOS outputs and digital circuitry.
Power Supply Pins for LVDS inputs.
Ground Pins for LVDS inputs.
Power Supply Pins for PLL circuitry.
Ground Pins for PLL circuitry.
Table 1. Pin Description
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Absolute Maximum Ratings
Parameter
Supply Voltage (VCC)
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Input Pin
Junction Temperature
Storage Temperature
Reflow Peak Temperature
Reflow Peak Temperature Time
Maximum Power Dissipation @+25C
Min
-0.3
-0.3
-0.3
-0.3
-55
-
Max
+4.0
VCC + 0.3
VCC + 0.3
VCC + 0.3
+125
+150
+260
10
1.9
Unit
V
V
V
V
C
C
C
sec
W
Table 2. Absolute Maximum Ratings
Recommended Operating Conditions
Symbol
Ta
-
Parameter
All Supply Voltage
Operating Ambient Temperature
VCC = 2.5V to 2.7V
Clock Frequency
VCC = 2.7V to 3.0V
VCC = 3.0V to 3.6V
Min
2.5
-10
20
15
15
Typ
+25
-
Max
3.6
+70
70
70
85
Unit
V
C
MHz
MHz
MHz
Table 3. Recommended Operating Conditions
“Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics Table4, 5, 6, 7” specify conditions for device operation.
“Absolute Maximum Rating” value also includes behavior of overshooting and undershooting.
Equivalent LVDS Input Schematic Diagram
LVDS_InP
AMP
LVDS_InN
Figure 3. LVDS Input Schematic Diagram
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Power Consumption
Over recommended operating supply and temperature range unless otherwise specified
Symbol
IRCCG
IRCCW
IRCCS
Parameter
LVDS Receiver
Operating Current
Gray Scale Pattern 16
(Fig.4)
LVDS Receiver
Operating Current
Worst Case Pattern
(Fig.5)
LVDS Receiver
Power Down Current
Typ*
Max
Unit
RL=100, CL=8pF, f=65MHz, VCC=3.3V
Conditions
41
53
mA
RL=100, CL=8pF, f=85MHz, VCC=3.3V
52
64
mA
RL=100, CL=8pF, f=65MHz, VCC=2.5V
30
42
mA
RL=100, CL=8pF, f=65MHz, VCC=3.3V
72
94
mA
RL=100, CL=8pF, f=85MHz, VCC=3.3V
84
96
mA
RL=100, CL=8pF, f=65MHz, VCC=2.5V
42
64
mA
-
10
µA
/PDWN=L
*Typ values are at the conditions of Ta = +25ºC
Table 4. Power Consumption
16 Grayscale Pattern
CLKIN
f
TA0, TB1, TC2
f/16
TA1, TB2, TC3
f/8
TA2, TB3, TC4
f/4
TA3, TB4, TC5
f/2
TA4-6, TB0,5,6
TC0,1,6, TD0-2
Steady State Low
TD3-6
Steady State High
Figure 4. 16 Grayscale Pattern
Worst Case Pattern
CLKIN
Tx0-6
x=A,B,C,D
Figure 5. Worst Case Pattern
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Electrical Characteristics
LVCMOS DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Symbol
VIH
VIL
VOH1
VOL1
VOH2
VOL2
IIN
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current
Conditions
VCC = 3.0V to 3.6V
IOH = -4mA
VCC = 3.0V to 3.6V
IOL = 4mA
VCC = 2.5V to 3.0V
IOH = -2mA
VCC = 2.5V to 3.0V
IOL = 2mA
GND  VIN  VCC
Min
2.0
GND
Typ*
-
Max
VCC
0.8
Unit
V
V
2.4
-
-
V
-
-
0.4
V
2.1
-
-
V
-
-
0.4
V
-
-
10
A
Table 5. LVCMOS DC Specifications
LVDS Receiver DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Symbol
VTH
VTL
IIN
Parameter
Differential Input High Threshold
Differential Input Low Threshold
Input Current
Conditions
RL=100Ω,
VIC=+1.2V
VIN = +2.4 / 0V
VCC = 3.6V
Min
-100
Typ*
-
Max
100
-
Unit
mV
mV
-
-
10
A
Table 6. LVDS Receiver DC Specifications
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LVCMOS & LVDS Receiver AC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Symbol
tRCP
tRCH
tRCL
tRCD
tRS
tRH
tTLH
tTHL
tRIP1
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
tRPLL
Parameter
VCC = 2.5V to 2.7V
CLKOUT
VCC = 2.7V to 3.0V
Transition Time
VCC = 3.0V to 3.6V
CLKOUT High Time
CLKOUT Low Time
RCLK IN to CLKOUT +/- Delay
LVCMOS Data Setup to CLKOUT
LVCMOS Data Hold from CLKOUT
LVCMOS Low to High Transition Time
LVCMOS High to Low Transition Time
Input Data Position0 (T=11.76ns)
Input Data Position1 (T=11.76ns)
Input Data Position2 (T=11.76ns)
Input Data Position3 (T=11.76ns)
Input Data Position4 (T=11.76ns)
Input Data Position5 (T=11.76ns)
Input Data Position6 (T=11.76ns)
Phase Lock Loop Set
Min
14.3
14.3
11.8
0.35T - 0.3
0.45T – 1.6
-0.4
T/7-0.4
2T/7-0.4
3T/7-0.4
4T/7-0.4
5T/7-0.4
6T/7-0.4
-
Typ
T
T
T
4T/7
3T/7
5T/7
2.0
1.8
0.0
T/7
2T/7
3T/7
4T/7
5T/7
6T/7
-
Max
50.0
66.6
66.6
3.0
3.0
+0.4
T/7+0.4
2T/7+0.4
3T/7+0.4
4T/7+0.4
5T/7+0.4
6T/7+0.4
10.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC
Table 7. LVCMOS & LVDS Receiver AC Specifications
LVCMOS Output
Figure 6. CLKOUT Transmission Time
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AC Timing Diagrams
LVDS Input Data Position
/-
Figure 7. LVDS Input Data Position
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Phase Lock Loop Set Time
/PDWN
Figure 8. PLL Lock Loop Set Time
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LVDS Data Timing Diagram
Figure 9. LVDS Data Timing Diagram
Pixel Data Mapping for JEIDA Format (6bit, 8bit Application)
TX Pin
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6
6bit
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
Hsync
Vsync
DE
-
8bit
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
Hsync
Vsync
DE
R0
R1
G0
G1
B0
B1
N/A
RX Pin
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RD0
RD1
RD2
RD3
RD4
RD5
RD6
Note : Use TA to TC channels and open TD channel for 6bit application.
Table 8. Data Mapping for JEIDA Format
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Pixel Data Mapping for VESA Format (6bit, 8bit Application)
TX Pin
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6
6bit
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
Hsync
Vsync
DE
-
8bit
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
Hsync
Vsync
DE
R6
R7
G6
G7
B6
B7
N/A
RX Pin
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RD0
RD1
RD2
RD3
RD4
RD5
RD6
Note : Use TA to TC channels and open TD channel for 6bit application.
Table 9. Data Mapping for VESA Format
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Normal Connection with JEIDA Format
Figure 10. Typical Connection Diagram
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Notes
1) Cable Connection and Disconnection
Do not connect and disconnect the LVDS cable, when the power is supplied to the system.
2) GND Connection
Connect each GND of the PCB which THC63LVDM83D and LVDS-Rx on it.
reduction to place GND cable as close to LVDS cable as possible.
It is better for EMI
3) Multi Drop Connection
Multi drop connection is not recommended.
Figure 11. Multi Drop Connection
4) Asynchronous use
Asynchronous using such as following systems is not recommended.
Figure 12. Asynchronous Use
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Package
Figure 13. Package Diagram
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Reference Land Pattern
CY1=
10.34
HE=
e=
8.100
0.500
E=
6.10
Package
Land Pattern
Ttyp.=
0.60
Gmin=
5.50
1.90
b=
0.200
Zmax=
Xmax=
0.470
9.30
Zmax/2
Unit mm
Figure 14. Reference of Land Pattern
The recommendation mounting method of THine device is reflow soldering.
The reference pattern is using the calculation result on condition of reflow soldering.
Notes
This land pattern design is a calculated value based on JEITA ET-7501.
Please take into consideration in an actual substrate design about enough the ease of mounting, the intensity of
connection, the density of mounting, and the solder paste used, etc… The optimal land pattern size changes
with these parameters. Please use the value shown by the land pattern as reference data.
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply to
the customer's design. We are not responsible for possible errors and omissions in this material. Please note if
errors or omissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the
contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will
be exempted from the responsibility unless it directly relates to the production process or functions of the
product.
5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video device,
office automation device, communication device, consumer electronics, smartphone, feature phone, and
amusement machine device. This product must not be used for applications that require extremely
high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control
device, combustion chamber device, medical device related to critical care, or any kind of safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product
conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this data sheet.
THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other than the Specified
Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the
user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain
small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have
sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to
support warranty for performance of this product. Except where mandated by applicable law or deemed
necessary by THine based on the user’s request, testing of all functions and performance of the product is not
necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or
malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a
smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses.
THine Electronics, Inc.
sales@thine.co.jp
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