IDT 72V85L15PAG

IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85
3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
DUAL 512 x 9, DUAL 1,024 x 9
DUAL 2,048 x 9, DUAL 4,096 X 9
DUAL 8,192 X 9
FEATURES:
DESCRIPTION:
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The IDT72V81/72V82/72V83/72V84/72V85 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional and
compatible to two IDT72V01/72V02/72V03/72V04/72V05 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflow and expansion logic to allow for unlimited expansion capability in both
word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity
bits at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when RT is pulsed low to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using IDT’s high-speed CMOS technology.
They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
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The IDT72V81 is equivalent to two IDT72V01 - 512 x 9 FIFOs
The IDT72V82 is equivalent to two IDT72V02 - 1,024 x 9 FIFOs
The IDT72V83 is equivalent to two IDT72V03 - 2,048 x 9 FIFOs
The IDT72V84 is equivalent to two IDT72V04 - 4,096 x 9 FIFOs
The IDT72V85 is equivalent to two IDT72V05 - 8,192 x 9 FIFOs
Low power consumption
— Active: 330 mW (max.)
— Power-down: 18 mW (max.)
Ultra high speed—15 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
Ideal for bidirectional, width expansion, depth expansion, busmatching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS™ technology
Space-saving TSSOP package
Industrial temperature range (–40°°C to +85°°C) is available
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(DA0-DA8)
WA
WRITE
CONTROL
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
WRITE
POINTER
RSA
DATA INPUTS
(DB0-DB8)
WB
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
READ
CONTROL
READ
CONTROL
RESET
LOGIC
FLAG
LOGIC
XOA/HFA
RESET
LOGIC
FLAG
LOGIC
EXPANSION
LOGIC
XIA
READ
POINTER
THREESTATE
BUFFERS
THREESTATE
BUFFERS
RA
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
RSB
EXPANSION
LOGIC
FFA
EFA
DATA
OUTPUTS
(QA0-QA8)
RB
FLA/RTA
XIB
XOB/HFB
FFB
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The AsyncFIFO™ is a trademark of Integrated Device Technology, Inc.
COMMERICAL TEMPERATURE RANGE
EFB
DATA
OUTPUTS
(QB0-QB8)
FLB/RTB
3966 drw 01
FEBRUARY 2009
1
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3966/3
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
FFA
QA0
QA1
QA2
QA3
QA8
GND
RA
QA4
QA5
QA6
QA7
XOA/HFA
EFA
FFB
QB0
QB1
QB2
QB3
QB8
GND
RB
QB4
QB5
QB6
QB7
XOB/HFB
EFB
XIA
DA0
DA1
DA2
DA3
DA8
WA
VCC
DA4
DA5
DA6
DA7
FLA/RTA
RSA
XIB
DB0
DB1
DB2
DB3
DB8
WB
VCC
DB4
DB5
DB6
DB7
FLB/RTB
RSB
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TSTG
IOUT
Symbol
VCC
GND
VIH(1)
VIL(2)
TA
–55 to +125
–50 to +50
°C
mA
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Commercial
Min.
3.0
0
2.0
—
0
Typ.
3.3
0
—
—
—
Max.
3.6
0
VCC+0.5
0.8
70
Unit
V
V
V
V
°C
Parameter(1)
Input Capacitance
Output Capacitance
Condition
VIN = 0V
VOUT = 0V
Max.
8
8
Unit
pF
pF
AC TEST CONDITIONS
IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85
Commercial
tA = 15, 20 ns
ICC1(3,4)
ICC2(3,5)
V
NOTE:
1. Characterized values, not currently tested.
(Commercial: VCC = 3.3V±0.3V, TA = 0°C to +70°C)
VOL
–0.5 to +7.0
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
DC ELECTRICAL
CHARACTERISTICS(1)
Parameter
Unit
NOTES:
1. For RT/RS/XI input, VIH = 2.6V (commercial).
2. 1.5V undershoots are allowed for 10ns once per cycle.
Symbol
CIN
COUT
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage
IOH = –2mA
Output Logic “0” Voltage
IOL = 8mA
Active Power Supply Current (both FIFOs)
Standby Current (R=W=RS=FL/RT=VIH)
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Commercial
RECOMMENDED DC OPERATING
CONDITIONS
TSSOP (SO56-2, order code: PA)
TOP VIEW
ILI(1)
ILO(2)
VOH
Rating
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
3966 drw 02
Symbol
COMMERCIAL TEMPERATURE RANGE
Min.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
Max.
Unit
–1
–10
2.4
1
10
—
µA
µA
V
—
0.4
V
—
—
100
5
mA
mA
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
3.3V
330Ω
TO
OUTPUT
PIN
510Ω
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. Tested at f = 20 MHz.
5. All Inputs = VCC - 0.2V or GND + 0.2V.
30pF*
3966 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes scope and jib capacitances.
2
FEBRUARY 5, 2009
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V±0.3V, TA = 0°C to +70°C)
Commercial
IDT72V81L15
IDT72V82L15
IDT72V83L15
IDT72V84L15
IDT72V85L15
Symbol
tS
tRC
tA
tRR
tRPW
tRLZ
tWLZ
tDV
tRHZ
tWC
tWPW
tWR
tDS
tDH
tRSC
tRS
tRSS
tRSR
tRTC
tRT
tRTS
tRTR
tEFL
tHFH,FFH
tRTF
tREF
tRFF
tRPE
tWEF
tWFF
tWHF
tRHF
tWPF
tXOL
tXOH
tXI
tXIR
tXIS
IDT72V81L20
IDT72V82L20
IDT72V83L20
IDT72V84L20
IDT72V85L20
Parameter
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width(2)
Read Pulse Low to Data Bus at Low Z(3)
Write Pulse High to Data Bus at Low Z(3, 4)
Min.
—
25
—
10
15
3
5
Max.
40
—
15
—
—
—
—
Min.
—
30
—
10
20
3
5
Max.
33.3
—
20
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
Data Valid from Read Pulse High
Read Pulse High to Data Bus at High Z(3)
Write Cycle Time
Write Pulse Width(2)
Write Recovery Time
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width(2)
Reset Set-up Time(3)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width(2)
Retransmit Set-up Time(3)
Retransmit Recovery Time
Reset to Empty Flag Low
Reset to Half-Full and Full Flag High
Retransmit Low to Flags Valid
Read Low to Empty Flag Low
Read High to Full Flag High
Read Pulse Width after EF High
Write High to Empty Flag High
Write Low to Full Flag Low
Write Low to Half-Full Flag Low
Read High to Half-Full Flag High
Write Pulse Width after FF High
Read/Write to XO Low
Read/Write to XO High
XI Pulse Width(2)
XI Recovery Time
XI Set-up Time
5
—
25
15
10
11
0
25
15
15
10
25
15
15
10
—
—
—
—
—
15
—
—
—
—
15
—
—
15
10
10
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
25
25
25
15
15
—
15
15
25
25
—
15
15
—
—
—
5
—
30
20
10
12
0
30
20
20
10
30
20
20
10
—
—
—
—
—
20
—
—
—
—
20
—
—
20
10
10
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
20
20
—
20
20
30
30
—
20
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
3
FEBRUARY 5, 2009
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
SIGNAL DESCRIPTIONS
COMMERCIAL TEMPERATURE RANGE
Single Device Mode, this pin acts as the retransmit input. The Single Device
Mode is initiated by grounding the Expansion In (XI).
The IDT72V81/72V82/72V83/72V84/72V85 can be made to retransmit
data when the Retransmit Enable control (RT) input is pulsed low. A retransmit
operation will set the internal read pointer to the first location and will not affect
the write pointer. Read Enable (R) and Write Enable (W) must be in the high
state during retransmit for the IDT72V81/72V82/72V83/72V84/72V85 respectively. This feature is useful when less than 512/1,024/2,048/4,096/8,192 writes
are performed between resets. The retransmit feature is not compatible with the
Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on
the relative locations of the read and write pointers.
INPUTS:
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET ( RS )
Reset is accomplished whenever the Reset (RS) input is taken to a low state.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power up before a write operation can take place. Both
the Read Enable ( R ) and Write Enable ( W ) inputs must be in the high
state during the window shown in Figure 2, (i.e., tRSS before the rising
edge of RS ) and should not change until tRSR after the rising edge of
RS. Half-Full Flag ( HF ) will be reset to high after Reset ( RS ).
EXPANSION IN ( XI )
This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate
an operation in the single device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth Expansion or Daisy
Chain Mode.
WRITE ENABLE ( W )
A write cycle is initiated on the falling edge of this input if the Full Flag (FF)
is not set. Data set-up and hold times must be adhered to with respect to the rising
edge of the Write Enable (W). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set to low and will remain set until the
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by the rising edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write
operations. Upon the completion of a valid read operation, the Full Flag (FF)
will go high after tRFF, allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from W, so external changes in W will not affect
the FIFO when it is full.
OUTPUTS:
FULL FLAG ( FF )
The Full Flag (FF) will go low, inhibiting further write operation, when the write
pointer is one location less than the read pointer, indicating that the device is full.
If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go low
after 512 writes for the IDT72V81, 1,024 writes for the IDT72V82, 2,048 writes
for the IDT72V83, 4,096 writes for the IDT72V84 and 8,192 writes for the
IDT72V85.
EMPTY FLAG ( EF )
The Empty Flag (EF) will go low, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating that the device is
empty.
EXPANSION OUT/HALF-FULL FLAG ( XO/HF )
This is a dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set low and will remain set until the
difference between the write pointer and read pointer is less than or equal
to one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion
Out (XO) of the previous device in the Daisy Chain by providing a pulse to the
next device when the previous device reaches the last location of memory.
READ ENABLE ( R )
A read cycle is initiated on the falling edge of the Read Enable (R) provided
the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis,
independent of any ongoing write operations. After Read Enable (R) goes high,
the Data Outputs (Q0 – Q8) will return to a high impedance condition until the
next Read operation. When all data has been read from the FIFO, the Empty
Flag (EF) will go low, allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance state. Once a
valid write operation has been accomplished, the Empty Flag (EF) will go high
after tWEF and a valid Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from R so external changes in R will not affect the FIFO
when it is empty.
DATA OUTPUTS ( Q0 – Q8 )
Data outputs for 9-bit wide data. This data is in a high impedance
condition whenever Read (R) is in a high state.
FIRST LOAD/RETRANSMIT ( FL/RT )
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first loaded (see Operating Modes). In the
4
FEBRUARY 5, 2009
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
COMMERCIAL TEMPERATURE RANGE
tRSC
tRS
RS
tRSS
tRSR
W
tRSS
R
tEFL
EF
tHFH, tFFH
HF, FF
3966 drw 04
NOTES:
1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.
2. W and R = VIH around the rising edge of RS.
Figure 2. Reset
tRC
tA
tRPW
tRR
tA
R
tDV
tRLZ
Q0-Q8
tRHZ
DATA OUT VALID
tWPW
tWC
DATA OUT VALID
tWR
W
tDS
D0-D8
tDH
DATA IN VALID
DATA IN VALID
3966 drw 05
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
FIRST
WRITE
R
W
tWFF
tRFF
3966 drw 06
FF
Figure 4. Full Flag From Last Write to First Read
5
FEBRUARY 5, 2009
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
COMMERCIAL TEMPERATURE RANGE
FIRST READ
W
R
tREF
tWEF
EF
tA
DATA OUT
VALID
VALID
3966 drw 07
Figure 5. Empty Flag From Last Read to First Write
tRTC
tRT
RT
tRTR
tRTS
W,R
tRTF
HF, EF, FF
FLAG VALID
3966 drw 08
Figure 6. Retransmit
W
tWEF
EF
tRPE
R
3966 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
R
tRFF
FF
tWPF
W
3966 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse
6
FEBRUARY 5, 2009
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
COMMERCIAL TEMPERATURE RANGE
W
tRHF
R
tWHF
HF
HALF-FULL OR LESS
HALF-FULL OR LESS
MORE THAN HALF-FULL
3966 drw 11
Figure 9. Half-Full Flag Timing
WRITE TO
LAST PHYSICAL
LOCATION
W
READ FROM
LAST PHYSICAL
LOCATION
R
tXOL
tXOH
tXOH
tXOL
3966 drw 12
XO
Figure 10. Expansion Out
tXI
tXIR
XI
tXIS
W
WRITE TO
FIRST PHYSICAL
LOCATION
tXIS
R
READ FROM
FIRST PHYSICAL
LOCATION
3966 drw 13
Figure 11. Expansion In
OPERATING MODES:
strates a four-FIFO Depth Expansion using two IDT72V81/72V82/72V83/
72V84/72V85s. Any depth can be attained by adding additional IDT72V81/
72V82/72V83/72V84/72V85s. These FIFOs operate in the Depth Expansion
mode when the following conditions are met:
Care must be taken to assure that the appropriate flag is monitored by each
system (i.e. FF is monitored on the device where W is used; EF is monitored on
the device where R is used).
1. The first FIFO must be designated by grounding the First Load (FL) control
input.
2. All other FIFOs must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied to the Expansion
In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag (FF) and Empty
Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all
must be set to generate the correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in
the Depth Expansion Mode.
Single Device Mode
A single IDT72V81/72V82/72V83/72V84/72V85 may be used when the
application requirements are for 512/1,024/2,048/4,096/8,192 words or less.
These FIFOs are in a Single Device Configuration when the Expansion In (XI)
control input is grounded (see Figure 12).
Depth Expansion
These devices can easily be adapted to applications when the requirements
are for greater than 512/1,024/2,048/4,096/8,192 words. Figure 14 demon7
FEBRUARY 5, 2009
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
USAGE MODES:
FIFO permits a reading of a single word after writing one word of data into an
empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the bus until the R line
is raised from low-to-high, after which the bus would go into a three-state mode
after tRHZ ns. The EF line would have a pulse showing temporary deassertion
and then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permits the writing
of a single word of data immediately after reading one word of data from a
full FIFO. The R line causes the FF to be deasserted but the W line being low
causes it to be asserted again in anticipation of a new data word. On the rising
edge of W, the new word is loaded in the FIFO. The W line must be toggled when
FF is not asserted to write new data in the FIFO and to increment the write pointer.
Width Expansion
Word width may be increased simply by connecting the corresponding
input control signals of multiple FIFOs. Status flags (EF, FF and HF) can be
detected from any one FIFO. Figure 13 demonstrates an 18-bit word width by
using the two FIFOs contained in the IDT72V81/72V82/72V83/72V84/72V85s.
Any word width can be attained by adding FIFOs (Figure 13).
Bidirectional Operation
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT72V81/72V82/72V83/72V84/72V85s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.
Compound Expansion
The two expansion techniques described above can be applied together
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
Data Flow-Through
Two types of flow-through modes are permitted, a read flow-through
and write flow-through mode. For the read flow-through mode (Figure 17), the
(HALF-FULL FLAG)
WRITE (W)
(HF)
READ (R)
FIFO
A or B
IDT
72V81
72V82
72V83
72V84
72V85
9
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
COMMERCIAL TEMPERATURE RANGE
9
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
3966 drw 14
EXPANSION IN (XI)
Figure 12. Block Diagram of One 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 FIFO Used in Single Device Mode
9
18
DATA
IN
(D)
HFA
HFB
FIFO A
FIFO B
9
WRITE (W)
READ (R)
EMPTY FLAG (EFB)
FULL FLAG (FFA)
RESET (RS)
RETRANSMIT (RT)
9
72V81/72V82/72V83
XIA
9 72V84/72V85
XIB
18
DATA
OUT (Q)
3966 drw 15
Figure 13. Block Diagram of One 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18 FIFO Memory Used in Width Expansion Mode
8
FEBRUARY 5, 2009
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
COMMERCIAL TEMPERATURE RANGE
TABLE I—RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Reset
Retransmit
RS
0
1
Inputs
RT
X
0
XI
0
0
Read Pointer
Location Zero
Location Zero
Read/Write
1
1
0
Increment(1)
Mode
Internal Status
Write Pointer
Location Zero
Unchanged
EF
0
X
Increment(1)
Outputs
FF
1
X
X
HF
1
X
X
X
NOTE:
1. Pointer will increment if flag is High.
TABLE II—RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Mode
Reset First Device
Reset All Other Devices
Read/Write
RS
0
0
Inputs
FL
0
1
XI
(1)
(1)
1
X
(1)
Internal Status
Read Pointer
Write Pointer
Location Zero
Location Zero
Location Zero
Location Zero
X
Outputs
X
EF
0
0
FF
1
1
X
X
NOTE:
1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,
sion Input, HF = Half-Full Flag Output
XI = Expan-
XOA
EFA
FFA
FIFO A
FLA
XIA
72V81/72V82
72V83/72V84
72V85
W
FFB
D
9
9
XOB
R
EFB
FIFO B
9
FLB
Q
V CC
XIB
XOA
FFA
FULL
EFA
EMPTY
FIFO A
9
FLA
72V81/72V82
72V83/72V84
72V85
FFB
9
XIA
XOB
EFB
FIFO B
RSA
FLB
XIB
3966 drw 16
Figure 14. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9 and 32,768 x 9 FIFO Memory (Depth Expansion)
9
FEBRUARY 5, 2009
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
R, W, RS
COMMERCIAL TEMPERATURE RANGE
Q0-Q8
Q9-Q17
Q(N-8)-QN
Q0-Q8
Q9-Q17
Q(N-8)-QN
IDT
72V81/72V82/72V83
72V84/72V85
IDT
72V81/72V82/72V83
72V84/72V85
IDT
72V81/72V82/72V83
72V84/72V85
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
D9-D17
D0-D8
D(N-8)-DN
D0-DN
D9-DN
D18-DN
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
D(N-8)-DN
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Figure 15. Compound FIFO Expansion
WA
RA
EFA
HFA
FIFO
IDTA
7201A
FFA
DA 0-8
QA 0-8
IDT
72V81
72V82
72V83
72V84
72V85
SIDE 1
SIDE 2
DA 0-8
QB 0-8
RB
HFB
EFB
WB
FIFO B
FFB
3966 drw 18
Figure 16. Bidirectional FIFO Mode
DATA IN
W
tRPE
R
EF
tWLZ
tWEF
tA
DATA OUT
tREF
DATA
OUT
VALID
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Figure 17. Read Data Flow-Through Mode
10
FEBRUARY 5, 2009
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
COMMERCIAL TEMPERATURE RANGE
R
tWPF
W
tRFF
FF
tDH
tWFF
DATA
DATA IN
tA
DATA OUT
IN
VALID
tDS
DATA
OUT
VALID
3966 drw 20
Figure 18. Write Data Flow-Through Mode
11
FEBRUARY 5, 2009
ORDERING INFORMATION
XXXX
X
XXX
X
Device Type
Power
Speed
Package
X
X
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
PA
Thin Shrink SOIC (TSSOP, SO56-2)
15
20
Commercial
L
Low Power
72V81
72V82
72V83
72V84
72V85
512 x 9 ⎯ 3.3V Dual FIFO
1,024 x 9 ⎯ 3.3V Dual FIFO
2,048 x 9 ⎯ 3.3V Dual FIFO
4,096 x 9 ⎯ 3.3V Dual FIFO
8,192 x 9 ⎯ 3.3V Dual FIFO
Access Time (tA)
Speed in Nanoseconds
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NOTES:
1. Industrial temperature range is available by special order.
2. Green parts are available. For specific speeds contact your local sales office.
DATASHEET DOCUMENT HISTORY
07/17/2006
02/05/2009`
pgs. 1 and 12.
pg. 12.
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12
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