CDB4334/8/9 評価用ボード・データシート

CDB4334/8/9
Evaluation Board for CS4334/8/9 Family of Products
Features
Description
l Demonstrates
The CDB4334/8/9 evaluation board is an excellent
means for quickly evaluating the CS4334/8/9 family of
24-bit, stereo D/A converters. Evaluation requires an analog signal analyzer, a digital signal source and a power
supply. Analog outputs are provided via RCA connectors
for both channels.
recommended layout and
grounding arrangements
l CS8414 Receives AES/EBU, S/PDIF, &
EIAJ-340 Compatible Digital Audio
l Digital and Analog Patch Areas
l Requires only a digital signal source and
power supplies for a complete Digital-toAnalog-Converter system
The CS8414 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog
converters and will accept AES/EBU, S/PDIF, and EIAJ340 compatible audio data. The evaluation board may
also be configured to accept external timing signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4334, CDB4338, CDB4339
I/O for
Clocks
and Data
CS8414
Digital
Audio
Interface
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
CS4334/38/39
Analog
Filter
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 1998
(All Rights Reserved)
AUG ‘98
DS248DB2
23
CDB4334/8/9
CDB4334/8/9 SYSTEM OVERVIEW
The CDB4334/8/9 evaluation board is an excellent
means of quickly evaluating the CS4334/8/9. The
CS8414 digital audio interface receiver provides an
easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to
supply clocks and data through a 10-pin header for
system development.
The CDB4334/8/9 schematic has been partitioned
into 7 schematics shown in Figures 2 through 8.
Each partitioned schematic is represented in the
system diagram shown in Figure 1. Notice that the
the system diagram also includes the interconnections between the partitioned schematics.
The CS8414 does not support a compatible data
format for the CS4335, CS4336 or CS4337. As a
result, an evaluation board is not available for these
devices. However, the evaluation board does allow
external generation of clocks and data, bypassing
the CS8414, and will support the CS4335/36/37 in
this configuration.
CS4334/8/9 DIGITAL TO ANALOG
CONVERTER
A description of the CS4334/5/6/7/8/9 is included
in the CS4334/5/6/7/8/9 data sheet.
CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8414 Digital Audio
Receiver, Figure 5. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock
(FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in
the CS8414 Datasheet.
During normal operation, the CS8414 operates in
the Channel Status mode where the LED’s display
channel status information for the channel selected
24
by the CSLR/FCK jumper. This allows the CS8414
to decode the de-emphasis bit from the digital audio interface for control of the CS4334/8/9 de-emphasis filter.
When the Error Information Switch is activated,
the CS8414 operates in the Error and Frequency information mode. The information displayed by the
LED’s can be decoded by consulting the CS8414
data sheet. It is likely that the de-emphasis control
for the CS4334/8/9 will be erroneous and produce
an incorrect audio output if the Error Information
Switch is activated and the CS4334/8/9 is in the internal serial clock mode.
Encoded sample frequency information can be displayed provided a proper clock is being applied to
the FCK pin of the CS8414. When an LED is lit,
this indicates a "1" on the corresponding pin located on the CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L
or R option of CSLR/FCK should be selected if the
FCK pin is being driven by a clock signal.
The evaluation board has been designed such that
the input can be either optical or coax, Figure 6.
However, both inputs can not be driven simultaneously.
CS8414 DATA FORMAT
The CS8414 data format can be set with jumpers
M0, M1, M2, and M3, as described the CS8414
datasheet. The format selected must be compatible
with the data format of the CS4334/8/9, shown in
Figures 4-7 of the CS4334/8/9 datasheet. The default settings for M0-M3 on the evaluation board
are given in Tables 2-4. The compatible data formats we have chosen for the CS8414 and
CS4334/8/9 are:
CS8414 format 2 ; CS4334
CS8414 format 5 ; CS4338
CS8414 format 6 ; CS4339
DS248DB2
CDB4334/8/9
ANALOG OUTPUT FILTER
The evaluation board includes a pair of single pole
passive filters and a pair of 3-pole active filters.
The passive filters are provided as an example for
cost-sensitive desigins. The active filters demonstrate a higher performance alternative with better
out-of-band noise rejection. The passive filters,
Fig. 4, have a corner frequency of approximately
95 kHz with JP3 and JP6 installed and 190 kHz
without JP3 and JP6. The 3-pole active filters are
shown in Fig. 3. The output filter options are selected via the Left and Right Channel filter jumpers, Fig. 2.
INPUT/OUTPUT FOR CLOCKS AND
DATA
The evaluation board has been designed to allow
the interface to external systems via the 10-pin
header, J9. This header allows the evaluation board
to accept externally generated clocks and data. The
schematic for the clock/data I/O is shown in
Figure 10. The 74HC243 transceiver functions as
DS248DB2
an I/O buffer where jumpers HDR1-HDR6 determine if the transceiver operates as a transmitter or
receiver. A transmit function is implemented with
the HDR1-HDR6 jumpers in the 8414 position.
LRCK, SDATA, and SCLK from the CS8414 will
be outputs on J9. The transceiver operates as a receiver with jumpers HDR1-HDR6 in the EXTERNAL position. MCLK, LRCK, SDATA and SCLK
on J9 become inputs.
GROUNDING AND POWER SUPPLY
DECOUPLING
The CS4334/8/9 requires careful attention to power
supply and grounding arrangements to optimize
performance. Figure 9 shows CDB power arrangements. The CDB4334/8/9 ground plane is divided
in a manner to control to digital return currents in
order to minimize noise. The decoupling capacitors
are located as close to the CS4334/8/9 as possible.
Extensive use of ground plane fill on both the analog and digital sections of the evaluation board
yield large reductions in radiated noise effects.
25
CDB4334/8/9
CONNECTOR
INPUT/OUTPUT
SIGNAL PRESENT
input
+ 5 Volt power
GND
input
ground connection from power supply
Digital input
input
digital audio interface input via coax
+5 V
Optical input
input
Digital I/O
input/output
digital audio interface input via optical
AOUTLA
output
left channel analog output with 3-pole active filter
AOUTRA
output
right channel analog output with 3-pole active filter
I/O for master, serial, left/right clocks and serial data
AOUTLP
output
left channel analog output with single-pole passive filter
AOUTRP
output
right channel analog output with single-pole passive filter
Table 1. System Connections
JUMPER
CSLR/FCK
M0
M1
M2
M3
SCLK
DEM_8414
HDR1-6
PURPOSE
Selects channel for CS8414
channel status information
POSITION
FUNCTION SELECTED
HI
LO
See CS8414 Datasheet for details
CS8414 mode selection
*Low
*High
*Low
*Low
See CS8414 Datasheet for details
Selects SCLK Mode
INT
*EXT
Internal SCLK Mode
External SCLK Mode
Selects source of de-emphasis
control
*8414
DEM
CS8414 de-emphasis
De-emphasis input static high
Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes an source
MCLK
Selects High-Rate or Base-Rate
Modes
x1
÷2
Selects Base Rate Mode
Selects High Rate Mode
Left Channel
Filter
Selects Active 3-pole or passive
single-pole filter
Active
Passive
Selects 3-pole active filter
Selects Single-pole passive filter
Right Channel
Filter
Selects Active 3-pole or passive
single-pole filter
Active
Passive
Selects 3-pole active filter
Selects Single-pole passive filter
*Default setting from factory
Notes:
The CS8414 data format requires the CS4334 to operate in the external serial clock mode.
Table 2. CDB4334 Jumper Selectable Options
26
DS248DB2
CDB4334/8/9
JUMPER
CSLR/FCK
M0
M1
M2
M3
SCLK
DEM_8414
HDR1-6
PURPOSE
Selects channel for CS8414
channel status information
POSITION
FUNCTION SELECTED
HI
LO
See CS8414 Datasheet for details
CS8414 mode selection
*High
*Low
*High
*Low
See CS8414 Datasheet for details
Selects SCLK Mode
INT
*EXT
Internal SCLK Mode
External SCLK Mode
Selects source of de-emphasis
control
*8414
DEM
CS8414 de-emphasis
De-emphasis input static high
Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes an source
MCLK
Selects High-Rate or Base-Rate
Modes
x1
÷2
Selects Base Rate Mode
Selects High Rate Mode
Left Channel
Filter
Selects Active 3-pole or passive
single-pole filter
Active
Passive
Selects 3-pole active filter
Selects Single-pole passive filter
Right Channel
Filter
Selects Active 3-pole or passive
single-pole filter
Active
Passive
Selects 3-pole active filter
Selects Single-pole passive filter
*Default setting from factory
Notes:
The CS8414 data format requires the CS4338 to operate in the external serial clock mode.
Table 3. CDB4338 Jumper Selectable Options
JUMPER
CSLR/FCK
M0
M1
M2
M3
SCLK
DEM_8414
HDR1-6
PURPOSE
Selects channel for CS8414
channel status information
POSITION
FUNCTION SELECTED
HI
LO
See CS8414 Datasheet for details
CS8414 mode selection
*Low
*High
*High
*Low
See CS8414 Datasheet for details
Selects SCLK Mode
INT
*EXT
Internal SCLK Mode
External SCLK Mode
Selects source of de-emphasis
control
*8414
DEM
CS8414 de-emphasis
De-emphasis input static high
Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes an source
MCLK
Selects High-Rate or Base-Rate
Modes
x1
÷2
Selects Base Rate Mode
Selects High Rate Mode
Left Channel
Filter
Selects Active 3-pole or passive
single-pole filter
Active
Passive
Selects 3-pole active filter
Selects Single-pole passive filter
Right Channel
Filter
Selects Active 3-pole or passive
single-pole filter
Active
Passive
Selects 3-pole active filter
Selects Single-pole passive filter
*Default setting from factory
Table 4. CDB4339 Jumper Selectable Options
DS248DB2
27
CDB4334/8/9
I/O for
Clocks
and Data
Fig 10
Digital
Audio
Input
Fig 6
RXN
RXP
CS8414
Digital
Audio
Interface
Fig 5
MCLK
LRCK
SCLK
SDATA
Clock
Gating
MCLK
LRCK
SCLK
SDATA
Active
Analog
Filter
Fig 3
CS4334/38/39
Fig 2
Fig 7
Power
Down
Fig 8
Passive
Analog
Filter
Fig 4
Figure 1. System Block Diagram and Signal Flow
AGND
R31
267K
LEFT CHANNEL FILTER
C44
3.3UF
TP5
ALP
ALA
J21
1
2
3
PASSIVE
ACTIVE
HDR1X3
VA+5
FERRITE_BEAD
L1
TP1
U7
SDATA-A
TP6
DEM-/SCLK-A
TP7
LRCK-A
TP8
MCLK-A
1
2
3
4
SDATA
DEM/SCLK
LRCK
MCLK
AOUTL
VA+
AGND
AOUTR
CS4334
8
7
6
5
C17
.1UF
X7R
C23
10UF
RIGHT CHANNEL FILTER
C43
3.3UF
AGND
ARP
ARA
TP4
R12
267K
J22
1
2
3
PASSIVE
ACTIVE
HDR1X3
AGND
Figure 2. CS4334/5/6/7/8/9
28
DS248DB2
CDB4334/8/9
R2
5.9K
C3
270PF
COG
C20
.1UF
VA+5
R24
4.75K
R3
R16
1.21K
V+
8
AGND
2
ALA
1.15K
C34
2700PF
COG
C36
2700PF
COG
AGND
1
+
V-
1
4
MC33202
U3
R5
23.2K
R23
C39
10UF
C21
.1UF
AOUTLA
LEFT
R27
100K
R15
C40 TP3
10UF
7
MC33202
U3
6
C4
R1
5.9K
J1
CON_RCA_RA
1
5
1.21K
AGND
20K
+
ARA
C37
2700PF
COG
3
4 NC
AGND
AGND AGND
1.15K
2
AGND
VA+5
R4
J2
CON_RCA_RA
3
AGND
R25
4.75K
C41 TP2
10UF
2
3
4 NC
AOUTRA
RIGHT
R26
100K
270PF
COG
AGND
AGND
C35
2700PF
COG
AGND
Figure 3. Analog Output Active Filter
J4
CON_RCA_RA
R18
ALP
R28
10K
560
C18
1500PF
COG
1
C6
1500PF
COG
2
3
4 NC
AOUTLP
LEFT
JP3
AGND
R17
ARP
R29
10K
AGND
J3
CON_RCA_RA
AGND
560
C22
1500PF
COG
1
C5
1500PF
COG
2
3
4 NC
AOUTRP
RIGHT
JP6
AGND
AGND
AGND
Figure 4. Analog Output Passive Filter
DS248DB2
29
1
2
3
30
HDR1X3
HDR5
HDR1X3
HDR3
GND
C1
10UF
1
2
3
VA+5
1
2
3
MCLK
HDR1X3
HDR4
VA
GND
1
2
3
SCLK
HDR1X3
HDR2
C26
.1UF
C16
.1UF
VD+5
RN3
560
8414_DEM
VCC
GND
U8
D1
LED_RECT
2
1UF
1
SN74HC04N
D3
LED_RECT
4
3
D5
LED_RECT
6
5
D6
LED_RECT
8
RXP
RXN
CSLR/FCK
VD1
C27
.1UF
SDATA
U2
C31
VD+5
14
HDR1X3
HDR1
10
1
2
3
LRCK
R11
VD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C
VERF
CD/F1
CE/F2
CC/F0
SDATA
CB/E2
ERF
CA/E1
M1
/C0/E0
M0
VD+
VA+
DGND
AGND
RXP
FILT
RXN
MCK
FSYNC
M2
SCK
M3
CS12/FCK
SEL
U
CBL
CS8414_M0
C32
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1UF
CS8414_M1
CS8414_M2
VA
R9
1K
CS8414
C33
.047UF
HDR1X3
HDR7
1
2
M0
3
HDR1X3
HDR8
1
2
M1
3
HDR1X3
HDR9
1
2
M2
3
HDR1X3
HDR10
1
2
8414_M
3
GND
HDR1X3
HDR11
1
2
CSLR/FCK
3
CSLR/FCK
9
GND
VA+5
SW_B3W_1100
S4
D4
10
LED_RECT
11
R7
47K
ERROR & FREQ
D2
12
LED_RECT
13
R6
47K
TP10
8414_DEM
VD1
7
DEM-/SCLK
SCLK
GND
DS248DB2
Figure 5. CS8414 Digital Audio Receiver Connections
HDR1X3
HDR13
1
INT
2
3
EXT
INT/EXT SCLK
CDB4334/8/9
GND
HDR1X3
HDR12
1
DEM
2
3
8414
CDB4334/8/9
OPTICAL INPUT
DIGITAL INPUT
OPT1
6
C10
1
J5
CON_RCA_RA
3
NC 4
1
2
RXP
2
C11
RXN
.01UF
C9
.01UF
3
R30 .01UF
75
L4
4
VD+5
47UH
5
TORX173
GND
GND
Figure 6. Digital Audio Inputs
MCLK
C28
U5
.1UF
74LVXC4245
U1
VD+5
VD+5
VD+5
4
3
2
1
10
11
12
13
GND
VCC
/SET1
CLOCK1
DATA1
/RST1
/SET2
CLOCK2
DATA2
/RST2
Q1
/Q1
Q2
/Q2
GND
VD+5
MCLK
PD
22
1
2
3
VD+5
14
J20
HDR1X3
5
HRM
6
BRM
VD+5
SDATA
DEM-/SCLK
LRCK
9
8
7
MC74HC74AN
GND
2
3
4
5
6
7
8
9
10
OE
VCCA
VCCB
T/\R
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
C14
.1UF
GND
1
24
21
20
19
18
17
16
15
14
VD+5
R20
R21
R22
R19
47
47
47
47
SDATA-A
DEM-/SCLK-A
LRCK-A
MCLK-A
R8
100K
GND
11
12
13
VD+5
GND
C15
.1UF GND
Figure 7. MCLK Divider and Clock Gating
DS248DB2
31
CDB4334/8/9
U10
VD+5
LM555CM
POWER DOWN
#
TIMER
LM555
R13
10K
S3
SW_B3W_1100
VD+5
2
TRIGGER
R14
10K
5
CONTROL
GND
4
VD+5
3
RESET
PD
OUTPUT
6
THRESHOLD
7
C38
10UF
C8
.01UF
DISCHARGE
8
VD+5
GND
R10
113K
+VCC
GND
1
C19
.1UF
GND
VD+5
GND
Figure 8. Power Down Circuitry
+5V
GND
CON_BANANA
CON_BANANA
J6
J7
Z1
P6KE6V8P
C12
47UF
VA+5
C25
.1UF
AGND
L3
FB
C13
47UF
VD+5
GND
Figure 9. Power Supply
32
DS248DB2
CDB4334/8/9
GND
7
MCLK
SCLK
LRCK
SDATA
8414
EXTERNAL
CLK SOURCE
VD+5
14
B4
B3
B2
B1
VCC
A4
A3
A2
A1
GBA
/GAB
6
5
4
3
13
1
C24
.1UF
1
2
3
HDR1X3
HDR6
8
9
10
11
U4
74HC243
GND
9
7
5
3
1
10
8
6
4
2
MCLK
SCLK
LRCK
SDATA
J9
HDR5X2
GND
DIGITAL I/O
GND
VD+5
GND
Figure 10. I/O for Clocks and Data
DS248DB2
33
CDB4334/8/9
Figure 11. Silkscreen Top
34
DS248DB2
CDB4334/8/9
Figure 12. Top Side
DS248DB2
35
CDB4334/8/9
Figure 13. Bottom Side
36
DS248DB2
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