IDT 74ALVCH162245

IDT74ALVCH162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUS
TRANSCIEVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
IDT74ALVCH162245
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
µ W typ. static)
• CMOS power levels (0.4µ
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. The ALVCH162245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit
transceiver. It allows data transmission from the A bus to the B bus or from
the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the
device so that the buses are effectively isolated.
The ALVCH162245 has series resistors in the device out-put structure
of the “A” port which will significantly reduce line noise when used with light
loads. This driver has been designed to drive ±12mA at the designated
threshold levels. The “B” port has a ±24mA driver.
The ALVCH162245 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA (A port)
• High Output Drivers: ±24mA (B port)
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1 D IR
1
2 D IR
24
48
25
1 OE
1A 1
47
2A 1
2
1A 2
2A 2
3
1A 3
2A 3
1A 5
1A 6
1A 7
1A 8
17
2A 5
19
2A 6
20
2A 7
22
2A 8
12
2B 6
2B 7
26
23
1B 8
2B 5
27
1B 7
37
2B 4
29
1B 6
38
2B 3
30
1B 5
40
11
2B 2
32
1B 4
41
9
14
16
2A 4
8
2B 1
33
1B 3
43
6
13
35
1B 2
44
5
1A 4
1B 1
46
2 OE
36
2B 8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
APRIL 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4748/1
IDT74ALVCH162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
1 DIR
1
48
1 OE
1B 1
2
47
1A 1
Symbol
Description
VTERM(2)
Max
Terminal Voltage with Respect to GND
–0.5 to +4.6
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
–50 to +50
mA
±50
mA
IOUT
DC Output Current
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
Unit
1B 2
3
46
1A 2
GND
4
45
GND
IOK
Continuous Clamp Current, VO < 0
–50
mA
1B 3
5
44
1A 3
mA
6
43
1A 4
Continuous Current through each
VCC or GND
±100
1B 4
ICC
ISS
V CC
7
42
V CC
1B 5
8
41
1A 5
1B 6
9
40
1A 6
GND
10
39
GND
1B 7
11
38
1A 7
1B 8
12
37
1A 8
2B 1
13
36
2A 1
2B 2
14
35
2A 2
GND
15
34
GND
2B 3
16
33
2A 3
2B 4
17
32
2A 4
V CC
18
31
V CC
2B 5
19
30
2A 5
2B 6
20
29
2A 6
GND
21
28
GND
2B 7
22
27
2A 7
2B 8
23
26
2A 8
2 DIR
24
25
2 OE
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance
VOUT = 0V
7
9
pF
CI/O
I/O Port Capacitance
VIN = 0V
7
9
pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
Description
xOE
Output Enable Inputs (Active LOW)
DIR
Direction Control Inputs
xAx(1)
Side A Inputs or 3-State Outputs
xBx(1)
Side B Inputs or 3-State Outputs
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
SSOP/ TSSOP/ TVSOP
TOP VIEW
FUNCTION TABLE (EACH 8-BIT SECTION)(1)
Inputs
xOE
xDIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2
Outputs
IDT74ALVCH162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
IIH
Input HIGH Current
VCC = 3.6V
VI = VCC
—
—
±5
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = VCC
—
—
±10
µA
IOZL
(3-State Output pins)
VO = GND
—
—
±10
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
∆ICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
0.1
—
40
mV
µA
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
Min.
Typ.(2)
Max.
Unit
– 75
—
—
µA
VI = 0.8V
75
—
—
VI = 1.7V
– 45
—
—
VI = 0.7V
45
—
—
—
±500
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Bus-Hold Input Sustain Current
Test Conditions
VCC = 3V
VI = 2V
IBHL
IBHH
Bus-Hold Input Sustain Current
VCC = 2.3V
IBHL
IBHHO
Bus-Hold Input Overdrive Current
VCC = 3.6V
VI = 0 to 3.6V
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
—
µA
µA
IDT74ALVCH162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS (A PORT)
Symbol
VOH
Test Conditions(1)
Parameter
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
VCC = 2.7V
VCC = 3V
VOL
Output LOW Voltage
Min.
Max.
Unit
VCC – 0.2
—
V
IOH = – 4mA
1.9
—
IOH = – 6mA
1.7
—
IOH = – 4mA
2.2
—
IOH = – 8mA
2
—
IOH = – 6mA
2.4
—
IOH = – 12mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 4mA
—
0.4
IOL = 6mA
—
0.55
VCC = 2.7V
IOL = 4mA
—
0.4
IOL = 8mA
—
0.6
VCC = 3V
IOL = 6mA
—
0.55
IOL = 12mA
—
0.8
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS (B PORT)
Symbol
VOH
Test Conditions(1)
Parameter
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
IOH = – 6mA
VCC = 2.3V
IOH = – 12mA
VCC = 2.7V
VCC = 3V
VOL
Output LOW Voltage
Min.
Max.
Unit
VCC – 0.2
—
V
2
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA
—
0.4
IOL = 12mA
—
0.7
VCC = 2.7V
IOL = 12mA
—
0.4
VCC = 3V
IOL = 24mA
—
0.55
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance Outputs enabled
CPD
Power Dissipation Capacitance Outputs disabled
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Test Conditions
Typical
Typical
Unit
CL = 0pF, f = 10Mhz
23
30
pF
4
5
4
IDT74ALVCH162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS (A PORT)(1)
VCC = 2.5V ± 0.2V
Symbol
Parameter
tPLH
Propagation Delay
tPHL
xBx to xAx
tPZH
Output Enable Time
tPZL
xOE to xAx
tPHZ
Output Disable Time
tPLZ
xOE to xAx
tSK(o)
Output Skew(2)
VCC = 2.7V
VCC = 3.3V ± 0.3V
Min.
Max.
Min.
Max.
Min.
Max.
Unit
1
4.9
—
4.7
1
4.2
ns
1
6.8
—
6.7
1
5.6
ns
1
6.3
—
5.7
1
5.5
ns
—
—
—
—
—
500
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS (B PORT)(1)
VCC = 2.5V ± 0.2V
Symbol
Parameter
tPLH
Propagation Delay
tPHL
xAx to xBx
tPZH
Output Enable Time
tPZL
xOE to xBx
tPHZ
Output Disable Time
tPLZ
xOE to xBx
tSK(o)
Output Skew(2)
VCC = 2.7V
VCC = 3.3V ± 0.3V
Min.
Max.
Min.
Max.
Min.
Max.
Unit
1
3.7
—
3.6
1
3
ns
1
5.7
—
5.4
1
4.4
ns
1
5.2
—
4.6
1
4.1
ns
—
—
—
—
—
500
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
IDT74ALVCH162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
Symbol
VCC(2)= 2.5V±0.2V
Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
(1, 2)
tPHL
V IH
VT
0V
ALVC Link
DISABLE
ENABLE
CONTROL
INPUT
GND
tPZL
D.U.T.
OUTPUT
SW ITCH
NORMALLY
CLOSED
LOW
tPZH
OUTPUT
SW ITCH
NORMALLY
OPEN
HIGH
500 Ω
RT
tPLH
V OH
VT
V OL
Propagation Delay
V OUT
Pulse
Generator
tPHL
OPPOSITE PHASE
INPUT TRANSITION
Open
500 Ω
tPLH
OUTPUT
V LOAD
V CC
V IN
V IH
VT
0V
SAME PHASE
INPUT TRANSITION
CL
ALVC Link
Test Circuit for All Outputs
tPLZ
V IH
VT
0V
V LOAD/2
V LOAD/2
VT
V LZ
V OL
tPHZ
VT
V OH
V HZ
0V
0V
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
V IH
DATA
VT
INPUT
0V
tSU
tH
V IH
TIMING
VT
INPUT
0V
tREM
V IH
ASYNCHRONOUS
VT
CONTROL
0V
V IH
SYNCHRONOUS
VT
CONTROL
tSU
0V
tH
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High
GND
All Other Tests
Open
ALVC Link
V IH
INPUT
tPHL1
tPLH1
Set-up, Hold, and Release Times
VT
0V
V OH
OUTPUT 1
tSK (x)
LOW-HIGH-LOW
PULSE
VT
V OL
tSK (x)
tW
V OH
VT
V OL
OUTPUT 2
VT
HIGH-LOW -HIGH
PULSE
VT
ALVC Link
tPLH2
tPHL2
Pulse Width
tSK (x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74ALVCH162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
X
XX
XXX
XX
Bus-Hold
Fam ily
Device Type
Package
ALVC
Tem p. R ange
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245
16-Bit Bus Transceiver with 3-State O utputs
162
Double-Density with Resistors, ±12m A (A port)
±24m A (B port)
H
Bus-Hold
74
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7
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