IDT IDT59920A-5SOI

IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT59920A
LOW SKEW
PLL CLOCK DRIVER
TURBOCLOCK™ JR.
FEATURES:
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DESCRIPTION:
Eight zero delay outputs
Selectable positive or negative edge synchronization
Synchronous output enable
Output frequency: 15MHz to 100MHz
CMOS outputs
3 skew grades:
IDT59920A-2: tSKEW0<250ps
IDT59920A-5: tSKEW0<500ps
IDT59920A-7: tSKEW0<750ps
3-level inputs for PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA IOL high drive outputs
Low Jitter: <200ps peak-to-peak
Ω terminated lines
Outputs drive 50Ω
Pin-compatible with Cypress CY7B9920
Available in SOIC package
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The IDT59920A is a high fanout phase lock loop clock driver intended for high performance computing and data-communications applications. The IDT59920A has CMOS outputs.
The IDT59920A maintains Cypress CY7B9920 compatibility while
providing two additional features: Synchronous Output Enable (GND/
sOE), and Positive/Negative Edge Synchronization (VDDQ/PE). When
the GND/sOE pin is held low, all outputs are synchronously enabled
(CY7B9920 compatibility). However, if GND/sOE is held high, all outputs except Q2 and Q3 are synchronously disabled.
Furthermore, when the VDDQ/PE is held high, all outputs are synchronized with the positive edge of the REF clock input (CY7B9920 compatibility). When VDDQ/PE is held low, all outputs are synchronized with the
negative edge of REF.
The FB signal is compared with the input REF signal at the phase
detector in order to drive the VCO. Phase differences cause the VCO of
the PLL to adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
FUNCTIONAL BLOCK DIAGRAM
V DDQ /PE
G ND/sOE
Q0
Q1
Q2
Q3
FB
PLL
REF
Q4
Q5
FS
Q6
Q7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2001
1
c
2001
Integrated Device Technology, Inc.
DSC 5846/2
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
REF
1
24
GND
VDDQ
2
23
TEST
FS
3
22
NC
NC
4
21
GND/sOE
VDDQ/PE
5
20
VDDN
VDDN
6
19
Q7
Q0
7
18
Q6
Q1
8
17
GND
GND
9
16
Q5
Q2
10
15
Q4
Q3
11
14
VDDN
VDDN
12
13
FB
VI
Description
Max
Unit
Supply Voltage to Ground
–0.5 to +7
V
DC Input Voltage
–0.5 to +7
V
530
mW
–65 to +150
°C
Maximum Power Dissipation (TA = 85°C)
TSTG
Storage Temperature
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter
CIN
SOIC
TOP VIEW
Description
Input Capacitance
Typ.
Max.
Unit
5
7
pF
NOTE:
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not
production tested.
PIN DESCRIPTION
Pin Name
Type
REF
IN
Description
Reference Clock Input
FB
IN
Feedback Input
TEST (1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.
GND/ sOE(1)
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the
VDDQ/PE
IN
feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
FS(2)
IN
Frequency range select. 3 level input.
FS = GND: 15 to 35MHz
FS = MID (or open): 25 to 60MHz
FS = VDD: 40 to 100MHz
Q0 - Q7
OUT
Eight clock output
VDDN
PWR
Power supply for output buffers
VDDQ
PWR
Power supply for phase locked loop and other internal circuitry
GND
PWR
Ground
NOTES:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.
2. This input is wired to VDD, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional
lock time before all data sheet limits are achieved.
2
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
Symbol
IDT59920A-5, -7
IDT59920A-2
(Industrial)
(Commercial)
Description
Min.
Max.
Min.
Max.
Unit
VDD
Power Supply Voltage
4.5
5.5
4.75
5.25
V
TA
Ambient Operating Temperature
-40
+85
0
+70
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions
Min.
Max.
Unit
VDD−1.35
—
V
—
1.35
V
VDD−1
—
V
VIH
Input HIGH Voltage
Guaranteed Logic HIGH (REF, FB Inputs Only)
VIL
Input LOW Voltage
Guaranteed Logic LOW (REF, FB Inputs Only)
VIHH
Input HIGH Voltage(1)
3-Level Inputs Only
VIMM
Input MID Voltage
3-Level Inputs Only
VDD/2−0.5
VDD/2+0.5
V
VILL
Input LOW Voltage(1)
3-Level Inputs Only
—
1
V
IIN
Input Leakage Current
VIN = VDD or GND
—
±5
µA
HIGH Level
—
±200
VIN = VDD/2
MID Level
—
±50
VIN = GND
LOW Level
—
±200
VDD = Max., VIN = GND
—
±100
µA
(1)
(REF, FB Inputs Only)
VDD = Max.
VIN = VDD
I3
3-Level Input DC Current (TEST, FS)
IPU
Input Pull-Up Current (VDDQ/PE)
µA
IPD
Input Pull-Down Current (GND/sOE)
VDD = Max., VIN = VDD
—
±100
µA
VOH
Output HIGH Voltage
VDD = Min., IOH = −16mA
—
—
V
VDD−0.75
—
VOL
Output LOW Voltage
VDD = Min., IOL = 46mA
—
0.45
V
IOS
Output Short Circuit Current
VDD = Max., VO = GND
—
N/A
mA
VDD = Min., IOH = −40mA
(2)
NOTES:
1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
2. Outputs are not to be shorted.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
IDDQ
Quiescent Power Supply Current
Test Conditions(1)
VDD = Max., TEST = MID, REF = LOW,
Typ.
Max.
Unit
10
40
mA
GND/sOE = LOW, All outputs unloaded
∆IDD
Power Supply Current per Input HIGH
VDD = Max., VIN = 3.4V
0.4
1.5
mA
IDDD
Dynamic Power Supply Current per Output
VDD = Max., CL = 0pF
100
160
µA/MHz
ITOT
Total Power Supply Current
VDD = 5V, FREF = 25MHz, CL = 240pF(1)
53
—
VDD = 5V, FREF = 33MHz, CL = 240pF(1)
63
—
240pF(1)
117
—
VDD = 5V, FREF = 66MHz, CL =
NOTE:
1. For eight outputs, each loaded with 30pF.
3
mA
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Description (1)
Symbol
Min.
Max.
Unit
—
10
ns/V
tR, tF
Maximum input rise and fall times, 0.8V to 2V
tPWC
Input clock pulse, HIGH or LOW
3
—
ns
DH
Input duty cycle
10
90
%
REF
Reference Clock Input
15
100
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT59920A-2
Symbol Parameter
Min.
Typ.
IDT59920A-5
Max.
Min.
Typ.
IDT59920A-7
Max.
Min.
Typ.
Max.
Unit
FS = LOW
15
—
35
15
—
35
15
—
35
FS = MED
25
—
60
25
—
60
25
—
60
FS = HIGH
40
—
100
40
—
100
40
—
100
REF Pulse Width HIGH
3
—
—
3
—
—
3
—
—
ns
REF Pulse Width LOW(1,8)
3
—
—
3
—
—
3
—
—
ns
—
0.1
0.25
—
0.25
0.5
—
0.3
0.75
ns
—
—
0.75
—
—
1.25
—
—
1.65
ns
−0.25
−0.5
0
0.25
0
0.5
0.7
ns
0.5
0
1.2
−0.7
−1.5
0
0
−0.5
−1.2
0
1.5
ns
2
2.5
0.5
2
3.5
0.5
3
5
ns
FREF
REF Frequency Range
tRPWH
tRPWL
tSKEW0
Zero Output Skew (All Outputs)
(1,8)
(1,3,4)
tDEV
Device-to-Device Skew(1,2,5)
tPD
REF Input to FB Propagation Delay(1,7)
MHz
tODCV
Output Duty Cycle Variation from 50%
tORISE
Output Rise Time(1)
0.5
tOFALL
Output Fall Time(1)
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tLOCK
PLL Lock Time(1,6)
—
—
0.5
—
—
0.5
—
—
0.5
ms
RMS
—
—
25
—
—
25
—
—
25
ps
Peak-to-Peak
—
—
200
—
—
200
—
—
200
tJR
Cycle-to-Cycle Output Jitter(1)
(1)
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz. Guaranteed by design and characterization, not subject to production testing.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. tSKEW is the skew between all outlets. See AC TEST LOADS.
4. For IDT59920A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.45ns Max.
5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.)
6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
7. tPD is measured with REF input rise and fall times (from 0.2VDD to 0.8VDD ) of 1.5ns.
8. Refer to INPUT TIMING REQUIREMENTS for more detail.
4
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST LOADS AND WAVEFORMS
≤ 1.5ns
V DD
≤ 1.5ns
VD D
80%
Vth = 0.5V DD
100 Ω
20%
0V
Outpu t
100 Ω
CMOS Input Test Waveform
CL
C L = 50pF (C L = 30pF for -2 and -5 de vice s)
Test Load
t OF AL L
t O R ISE
0.8 V DD
0.2 V DD
CMOS Output Waveform
AC TIMING DIAGRAM
t R EF
t RP W L
t R PW H
REF
t PD
t OD CV
t O D CV
FB
t JR
Q
tS K E W
t SK E W
OTHER Q
NOTES:
Skew:
tSKEW:
The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5) and terminated with VDD/2.
The skew between all outputs.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.)
tODCV:
The deviation of the output from a 50% duty cycle.
tORISE and tOFALL are measured between 0.2VDD and 0.8VDD.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
5
IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device Type
XX
Package
X
Process
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
SO
Small Outline IC (300-mil)
59920A-2 Low Skew PLL Clock Driver TurboClock Jr.
59920A-5
59920A-7
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
6
for Tech Support:
[email protected]
(408) 654-6459