LatticeXP™ Advanced Evaluation Board User’s Guide September 2009 Revision: EB13_01.3 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Introduction Traditional SRAM-based FPGA solutions require additional non-volatile memory components be placed onto the printed circuit board (PCB), consuming additional resources and adding cost to the PCB solution. Alternatives to the SRAM-based FPGA include fuse based FPGAs or ASIC devices. While these solutions provide a non-volatile solution, they cannot be re-programmed. The LatticeXP is a non-volatile, re-programmable FPGA solution, including both SRAM-based FPGA cells for easy reconfiguration and Flash-based memory for non-volatility, all in one efficient package. The LatticeXP Advanced Evaluation Board is designed to help the user examine key features of the LatticeXP device and to aid in the development of custom designs. It is a ready-made, proven platform that includes a variety of industry-standard memory and communication interfaces. Please check the Lattice web site for updates to this user’s guide at: www.latticesemi.com/boards. Please note the revision number on the front of this document. Features • Single board solution for evaluation of the LatticeXP FPGA • LatticeXP FPGA in a 388-ball fpBGA package • DDR SODIMM socket and DDR power generation • FCRAM interface and memory • 10/100/1000 Mbps Ethernet PHY to an RJ45 connector • PCI plated finger connections • Seven-segment LED • Eight LEDs for visual feedback • Eight-position switch input • 1149.1 JTAG programming/boundary scan interface • Built-in power supply operating from 5V external supply (AC adapter included) • Selectable CORE voltage for the LatticeXP • Selectable voltages for all eight I/O banks • Built in oscillator for reference clocks • SMA connectors to LatticeXP clock input and general purpose I/O pins • 100mil center-center test point grid General Description The heart of the LatticeXP Advanced Evaluation board is the LatticeXP FPGA. Around this core device are several industry standard interfaces and protocol devices. The LatticeXP is manufactured to operate with multiple 1.2V to 5V voltage ranges. The LFXP10E device requires a core voltage supply at 1.2V and an auxiliary I/O supply at 3.3V. The LFXP10C device requires a core voltage supply at 1.5V-3.3V, and an auxiliary 3.3V supply. The LatticeXP Advanced Evaluation Board provides four supply voltages, all sourced from a 5V external source. The board provides fixed 1.2V, 2.5V and 3.3V power rails, and a single adjustable voltage that ranges from 1.2V to 3.3V. It is possible to use external power supplies to override the fixed output levels, if it is required. The voltage supplied to the LatticeXP core is selectable using shunts. 2 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Once a correct set of supply voltages has been applied to the LatticeXP FPGA, the device is ready for programming. The LatticeXP FPGA is typically programmed and verified from the 1149.1 JTAG interface. A JTAG download cable can be connected onto either a 1x10 SIP header or a 2x5 DIP header. The LatticeXP is typically programmed using the Lattice ispVM® System software. The ispVM System software can be downloaded from the Lattice web site at www.latticesemi.com/software. ispVM System 15.2 or later should be used to program the LatticeXP device. The ispVM System software can be used to program either the SRAM memory or the Flash cells. The internal Flash memory on the LatticeXP device can be reprogrammed in the background while the FPGA is operating. LatticeXP devices can also be programmed using either serial or parallel interfaces. The parallel interface permits either the SRAM or the Flash PROM memories to be programmed in the same manner as the JTAG port. The slave serial and master serial modes available on the LatticeXP only program the SRAM memory. The LatticeXP Advanced board does not support these alternate programming modes directly. Test points are provided on the board for connecting to the serial programming points. The parallel programming interface is inaccessible since it is connected to provide the FCRAM memory function. Once programmed, the LatticeXP device has access to several interfaces designed to highlight FPGA features. The LatticeXP directly interfaces to a set of switches, LEDs, a seven segment display, a prototype grid, a FCRAM chip, Double-data-rate DRAM, a set of SMA connectors, a PCI bus and an Ethernet PHY device. One of the key interfaces supported directly in the LatticeXP FPGA is easy support for DDR DRAM memories. The evaluation board provides a DDR SODIMM socket for inserting SODIMM DDR modules. The LatticeXP directly controls the address and memory strobes and connects to a 16-bit data bus. The data bus requires data qualification strobes (DQS) also be present. The LatticeXP FPGA series has an internal hardware assist for managing the DQS signals. These signals are connected to the DDR SODIMM. The DDR interface is capable of running at 167MHz (333 DDR). The FCRAM interface also uses the LatticeXP DQS hardware assist. The LatticeXP Advanced Evaluation board provides a single FCRAM device, providing an eight-bit data bus. Data rates to between the FCRAM and the LatticeXP are equivalent to the DDR interface. The evaluation board also provides a 3.3V 33MHz, 32-bit PCI interface. The board is designed to only be inserted into 3.3V PCI backplanes. It is not recommended to install the board into a 5V backplane. The LatticeXP FPGA is not directly 5V tolerant. In order for the device to be placed into a 5V system the PCI I/O clamp diodes must be enabled, and series current limiting resistors need to be on each 5V I/O. The evaluation board includes a 10/100/1000 Ethernet PHY device (National Semiconductor DP83865). All of the necessary support components are provided to connect to a 10/100/1000 Base-T network. The physical side of the PHY connects to an RJ45 connector with built-in isolation magnetics and a 3KV capacitor. The Media Independent Interface (MII) is connected to the LatticeXP FPGA. The LatticeXP must be programmed with a Media Access Controller (MAC) before Ethernet traffic can be routed across the interface. Additional features of the LatticeXP Advanced Evaluation board are described in detail in the following section. Additional Resources Additional resources related to this board can be downloaded from the web at www.latticesemi.com/boards. Click on the appropriate evaluation board, then see the blue “Resources” box on the right of the screen for items such as: updated documentation, software, sample designs, IP evaluation bitstreams, and more. LatticeXP Advanced Evaluation Board Functional Description The LatticeXP Advanced Evaluation Board is comprised of several primary functional blocks as shown in Figure 1. In the descriptions below, locations of components and board features will be described relative to a compass symbol placed adjacent to the Lattice logo. For example, the seven-segment LED is on the northwest corner of the board, and the trimmer potentiometer is on the southeast corner of the board. 3 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Figure 1. LatticeXP Advanced Evaluation Board Functional Blocks Seven-Segment LEDs and SMT LEDs Prototype Grid FCRAM Chip 0.1” Center Pins SMA Connectors 0.1” Center Pins Program/Reset Switches Configuration Switch OSC DIP Switches 5V/GND Posts RJ45 Connector DC Input Jack DDR SODIMM Ethernet PHY XP10 Device 0.1” Center Pins DC Input Connectors Trimmer POT Power Supply The LatticeXP Advanced Evaluation Board provides three locations to apply power. On the east side of the board are a pair of banana jacks (J18 and J17), and a coaxial DC connector (J19), which receive power from either a bench power supply or a brick style power supply. The third method for powering the board is to place it in a PCI host. Do not provide a supply voltage from the other DC input sources when the board is plugged into a PCI host backplane. In order to power the board, a DC source between 5V and 5.5V must be applied to the DC input jack or the 5V/GND banana connectors. Alternately 3.3V must be supplied from the PCI interface. The 5V DC input voltage is converted by DC-DC converters and switching power supplies to provide 3.3V, 2.5V, 1.2V, and an adjustable DC source. The output from these supplies travels through surface mounted fuse holders. Fuses are supplied and prevent over-current conditions from damaging the power supply circuitry. Each of the DC converters can be enabled and disabled independently. Jumpers JP15-18 control the conversion system. Table 1. Power Supply Enable/Disable Jumper Number Supply Rail Enabled/Disabled JP15 VADJ 1-2: Disable 2-3: Enable JP16 3.3V 1-2: Disable 2-3: Enable JP17 2.5V 1-2: Disable 2-3: Enable JP18 1.2V 1-2: Disable 2-3: Enable Function More banana jack inputs are located immediately next to (west of) the fuse blocks. These inputs provide an alternate means for applying DC voltage levels to the board. To apply voltages not supplied by the on-board power circuitry, simply remove the appropriate fuse from the fuse holder, then connect an alternate DC supply to the banana jack associated with that fuse. 4 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Table 2. Power Supply Fuses Fuse Number Supply Rail Enabled/Disabled Banana Jack Input F1 2.5V J6 F2 1.2V J7 F3 3.3V J8 F4 VADJ J9 A set of 2x4 100mil headers (JP7-JP11) are located next to (west of) the banana jacks (J13-J16). All but one of these headers control the LatticeXP core voltage setting. JP10 connects to the Ethernet PHY (U2) and does not connect to the core voltage of the LatticeXP device. JP10 is connected to VADJ on one side and to the PHY core supply on the other. When using the PHY, VADJ must be set to 1.8V. Do not remove power from the Ethernet PHY core. Doing so may damage the Ethernet PHY. The remaining jumper blocks must have only one supply rail connected to the LatticeXP core voltage. The jumpers placed on the jumper block must run in an east-west orientation. The jumper blocks assign the core voltage as follows: Table 3. LatticeXP Core Voltage Selection Jumper Block Voltage Supplied to the LatticeXP Core JP7 2.5V JP8 1.2V ‘E’ series LatticeXP only JP9 3.3V JP11 VADJ R29 is a trimmer potentiometer which controls the output level of the VADJ section of the power supply. R29 is located in the southeast corner of the board. The VADJ can be set between 1.2V and 3.3V. Programmability Components and logic related to programming the LatticeXP FPGA are located in the northeast corner of the board. These include a set of switches, jumpers, push buttons and header blocks that modify how the LatticeXP programs itself when power is applied. Figure 2. Programming Interface PCI JTAG Serial DIN FPGA Loader JTAG Programming Configuration Reset Done Program SW4 Configuration SW4 directs the LatticeXP to a programming data source used to configure the on-chip SRAM. SW4 is located on the east side of the board. Table 4 shows the mode for each switch setting. 5 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Table 4. LatticeXP Programming Configuration SW4 Setting CFG1:CFG0 Mode Up:up Self-download mode CPU Flash programming Up:down Slave parallel programming Down:up Master serial programming Down:down Slave serial programming SW4 is typically set with both switches up. The LatticeXP loads configuration data from the on-chip internal Flash memory. The LatticeXP Advanced Evaluation board does not support the Slave Parallel programming mode since the data bus and controls for this mode are dual-use pins, connected to the FCRAM interface. Slave and Master Serial programming modes are also available. The serial mode interface is available using JP5 (Serial DIN) and JP13 (FPGA Loader). See the LatticeXP Evaluation Board schematic at the end of this document for further details concerning the connectivity for the serial mode I/Os. Table 5. LatticeXP Serial DIN Header Settings Serial DIN Header Action 1:2 JP13 DIN to XP DIN 2:3 Reserved Open XP DIN available for general purpose I/O Push-buttons and Status LEDs There are two push-buttons and three LEDs in the northeast corner of the evaluation board (see Figure 2). The Program push-button asserts the PROGRAM pin on the LatticeXP device, erasing the SRAM and causing the LatticeXP to begin a programming sequence. Pushing the button also illuminates a yellow LED, giving confirmation the switch has been closed. The other push-button acts as a RESET input to the LatticeXP. The LatticeXP does not have a dedicated RESET input. RESET must be assigned an I/O when the device is programmed. This is done by instantiating the Global Reset macro in the HDL source. A red LED is illuminated whenever the RESET button is pushed. The third LED is connected through a small amount of control circuitry to the LatticeXP DONE I/O. DONE is driven high when the LatticeXP is successfully programmed. When DONE is driven high, this green LED turns on. This LED is active when the LatticeXP is programmed using the JTAG header. When a JTAG programming sequence is initiated, the LatticeXP I/Os are tristated. The tristated I/Os float high, which mimics the open-drain high assertion of DONE following a successful programming sequence. At the completion of a JTAG programming sequence, the DONE LED will stay illuminated if the programming sequence succeeded. It will turn off if the sequence did not succeed. Programming Headers The LatticeXP Advanced Evaluation Board provides two JTAG headers for programming the LatticeXP device. These headers are wired in parallel, and only differ in form factor. JP12 is a 1x10 100mil header, and JP14 is a 2x5 100mil header. Either can be used with a Lattice USB or parallel port download cable. The download cable used with ispVM System software may have either fly-wire JTAG wires, or the JTAG wires in a captive header. Figure 3 shows how the fly-wire JTAG wires are connected to the 1x10 header. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG 6 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor pins. Failure to follow these procedures can in result in damage to the LatticeXP FPGA device and render the board inoperable. Figure 3. JTAG Fly-wire Connections Pin 10 Pin 1 VCC RED TDI ORANGE TDO BROWN TMS PURPLE GND BLACK TCK TRST/DONE INIT WHITE GREEN BLUE TMS VCC TDO GND TDI TCK DONE INIT The 2x5 programming header only connects the four basic JTAG signals, and the VCC source. The silkscreen provided on the board shows the connection points for each wire. All of the remaining fly-wires are left unconnected. Regardless of which header is used, the ispVM System software is used to control the download cable. Configure the ispVM software to use the cable type connected to the evaluation board (parallel port or USB). Select the bitstream to download, and the memory space to which the data will be written (SRAM or FLASH). See the ispVM System Help for more information. Table 6. Programming Interface Connection Summary Function LatticeXP Pin Location JP 13 Pin BUSY C11 JP13 (3) CCLK G4 JP13 (1) DONE B1 JP13 (9) JP12 (9) INITN Y2 JP13 (8) JP12 (10) PROGRAMN F4 JP13 (10) JP 6 Pin JP 12 Pin JP 14 Pin Note D14 (Green LED) D15 (Yellow LED) TCK D18 JP6 (8) JP12 (8) JP14 (1) TDI D20 JP6 (4) JP12 (3) JP14 (5) TDO F19 JP6 (2) JP12 (2) JP14 (7) TMS D19 JP6 (6) JP12 (6) JP14 (3) Table 7. Supplemental Programming Interface Connection Summary Schematic Name LatticeXP Pin Location CFG0 C1 JP 5 Pin CFG1 B2 D0 D10 DIN_2_D0 C13 JP5 (3) DIN_2_SDIN A7 JP5 (1) Important: Use only ispVM System version 15.2 or later to program the LatticeXP device. 7 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor LatticeXP and Support Interfaces The LatticeXP Advanced Evaluation Board includes advanced interfaces such as DDR, PCI, FCRAM and Ethernet. These are complex either by the nature of the signaling interface, or by the internal programming required to operate them. Lattice provides bitstreams which can be used to evaluate the performance of the LatticeXP FPGA on several of these interfaces. Lattice also provides precompiled intellectual property cores for controlling the FCRAM, DDR, PCI and the Ethernet. These precompiled intellectual property cores can be used to design and simulate an integrated solution. An intellectual property license is required to generate customized programming bitstreams. Visit the Lattice web site at www.latticesemi.com/boards to find the latest available evaluation bitstreams for these interfaces. The LatticeXP Advanced Evaluation Board uses the following conventions. • Devices are numbered in a consistent fashion. Each device starts at reference designator ‘1’ in the northwest corner of the board (i.e. R1, C1, U1, L1, etc.). The component number increases by one in a columnar fashion (i.e. southward). When the south edge of the board is reached, the count resumes slightly east, and at the north side of the board. Thus the highest numbered components will always be in the southeast corner of the board. This same numbering sequence is applied to the reverse side of the printed circuit board. • Adjacent to the switch inputs, LED outputs, SMA connectors and test points is the alphanumeric position of the pin on the LatticeXP FPGA. For example, next to the DIP oscillators (pin 10 in the silkscreen) is the designator (A10). This indicates XU2 pin 10 is connected to the LatticeXP A10 pin. • SMA connectors have a solid white rectangular area near them denoting the positive side of a matched pair. The negative side of a matched pair has a white outline rectangle area. For detailed information concerning the pin connections for these interfaces, see the appropriate connection summary tables in the following pages, and the LatticeXP Advanced Evaluation Board schematics in Appendix A. VCCIO Power The LatticeXP provides eight banks for configuring different input/output voltages and different input/output protocols. The LatticeXP Advanced Evaluation board permits four of these I/O banks to be statically configured based on the requirements of the design. VCCIO bank 2/3 is fixed to 2.5V. These two banks interface to the DDR SODIMM socket. The DDR memory only operates at 2.5V, so making these two banks I/O voltage adjustable is not very useful. Banks 4/5 are set to 3.3V, which configures the I/O correctly for the PCI bus. Banks 0,1, 6, and 7 can be configured to different I/O voltage levels. VCCIO power selection is made using the header in the north-central section of the board (see Figure 4). Figure 4. VCCIO Voltage Selection Header VADJ 3.3V 1.2V 2.5V VCCIO0 VCCIO1 VCCIO6 VCCIO7 Figure 4 shows how VCCIO6 would be configured to use a 2.5V supply for the output buffer drive level. Prototype Grid The board provides a small 100mil center-center prototype area just to the west of the VCCIO power selection jumpers. This area is connected to FPGA I/Os primarily in banks 0, 1, 6 and 7. The silkscreen near the prototype grid provides a map describing the FPGA alphanumeric grid number and bank of the I/O. 8 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Please note that some of the bank 7 I/Os are connected in parallel with the seven-segment LED. Also, H21 is one of the PLL input pins, so an additional clock frequency can be injected into the FPGA from the prototype area. Refer to Table 8 for a complete description of the prototype area connections. Table 8. Prototype Area Connection Summary Board Location LatticeXP Pin Location Schematic Name J1 (1) A2 TP_A2 J1 (2) C5 TP_C5 J1 (3) B12 TP_B12 J1 (4) E2 SSEG_D J1 (5) G3 TP_G3 J2 (1) A3 TP_A3 J2 (2) D3 TP_D3 J2 (3) B13 TP_B13 J2 (4) E3 SSEG_DP J2 (5) H4 TP_H4 J4 (1) A4 TP_A4 J4 (2) D8 TP_D8 J4 (3) B22 TP_B22 J4 (4) F1 SSEG_C J4 (5) J4 TP_J4 J5 (1) B3 TP_B3 Note Also seven-segment display Also seven-segment display Also seven-segment display Also DIN_2_SDIN J5 (2) D9 TP_D9 J5 (3) D12 TP_D12 Also DIN_2_D0 J5 (4) F2 SSEG_G Also seven-segment display J5 (5) K4 TP_K4 J8 (1) B4 TP_B4 J8 (2) A12 TP_A12 J8 (3) D1 SSEG_F Also seven-segment display J8 (4) F3 SSEG_B Also seven-segment display J8 (5) R2 TP_R2 J9 (1) C3 TP_C3 J9 (2) A13 TP_A13 J9 (3) D2 SSEG_A J9 (4) G1 TP_G1 J9 (5) T2 TP_T2 J10 (1) C4 TP_C4 J10 (2) A18 TP_A18 J10 (3) E1 SSEG_E J10 (4) G2 TP_G2 J10 (5) H21 TP_H21 Also seven-segment display Also seven-segment display Also PLL input LED Displays In the northwest corner of the board are two different types of LEDs. Eight chip-style LEDs are connected to I/O pins dedicated to driving the LEDs. The silkscreen indicates the alphanumeric location of the driving I/O. These locations are also indicated in Table 9. The LEDs illuminate when the corresponding I/O is driven to VOL. 9 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Table 9. LED Connection Summary LED Number LatticeXP Pin Location Schematic Name D1 H1 TP_H1 D2 B16 TP_B16 D3 B18 TP_B18 D4 C18 TP_C18 D5 C19 TP_C19 D6 C20 TP_C20 D7 W16 TP_W16 D8 A16 TP_A16 A seven-segment LED is located in the northwest corner of the board. Unlike the chip LEDs, the I/Os driving the seven-segment display are not dedicated. These LED segments are also connected to the prototype grid. Illuminating one of the LED segments works in the same way as the chip LEDs. Each segment, when driven toward VOL, will illuminate. Refer to Table 10 for a complete description of the seven-segment display connections. Table 10. Seven-segment Display Connection Summary Display Segment LatticeXP Pin Location Alternate Header Connection Schematic Name SSEG_A D2 J9 (3) TP_D2 SSEG_B F3 J8 (4) TP_F3 SSEG_C F1 J4 (4) TP_F1 SSEG_D E2 J1 (4) TP_E2 SSEG_DP E3 J2 (4) TP_E3 SSEG_E E1 J10 (3) TP_E1 SSEG_F D1 J8 (3) TP_D1 SSEG_G F2 J5 (4) TP_F2 Switches A set of eight simple toggle switches is located at the west edge of the board. The silkscreen indicates the alphanumeric location of the I/O on the FPGA. When in the up position, the switch is pulled to 3.3V through a 10K resistor. When in the down position, the switch is tied to ground. Refer to Table 11 for a complete description of the switch connections. Table 11. Switch Connection Summary Board Location LatticeXP Pin Location Schematic Name SW1_1 C22 TP_C22 SW1_2 Y21 TP_Y21 SW1_3 AA22 TP_AA22 SW1_4 AA21 TP_AA21 SW1_5 AB21 TP_AB21 SW1_6 C21 TP_C21 SW1_7 W8 TP_W8 SW1_8 AB2 TP_AB2 10 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Oscillator and Clock Inputs FPGA designs are nearly always created with logic synchronous to some reference frequency. The FPGA has four PLLs and multiple primary clock inputs. Some of these clock inputs are dedicated to a particular interface on the evaluation board. There are several ways to input reference clock frequencies. LatticeXP pins U22 and T21 are connected to SMA connectors. These two SMAs are connected to the positive and negative pairs of one of the four PLLs provided by the FPGA. The characteristic impedance of the traces is 50 ohms. Two additional SMA connectors provide a matched pair (positive and negative) of traces to one of the Primary Clock inputs. This pair of traces enter the FPGA at pins AB13 (positive) and AA13 (negative). The characteristic impedance of the traces is 50 ohms. Table 12. SMA Connection Summary Board Location LatticeXP Pin Location Schematic Name J6 SMA AA13 PRI_CLK_N J7 SMA AB13 PRI_CLK_P J11 SMA U22 SMA_U22 J12 SMA T21 SMA_T21 The PLL input and the Primary Clock are also programmable as general purpose I/Os. This permits these I/Os to be evaluated in operation over coaxial cables. The board also provides a 14-pin 3.3V clock oscillator device. The oscillator is in a 16-pin DIP socket. Using a socket permits the use of an arbitrary input clock frequency and the use of oscillators with different accuracy and jitter characteristics. The oscillator socket is also wired to permit the use of either full-size or half-size DIP oscillators. Figure 5 shows the configuration options available. Figure 5. Oscillator Input Options Full-size to primary clock Half-size to primary clock Full-size to PLL Half-size to PLL OSC OSC OSC OSC The socket is wired such that pins 10 and 13 are connected to the same Primary Clock input (pin A10). Pin 9 is connected to a PLL input (pin J2) in bank 7 on the FPGA. The last location provided on the board for supplying external clock frequencies lies in the prototype area. FPGA pin H21 is the positive side of one of the four PLL inputs. An arbitrary clock frequency can be supplied to the FPGA from J10 pin 5 in the prototype grid. 11 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor 10/100/1000 Ethernet PHY In the southwest corner of the board is a National Semiconductor Gigabit Ethernet PHY (DP83865). The LatticeXP FPGA interacts with the PHY over a Media Independent Interface (MII). The PHY is connected to an RJ45 header on the Media Dependent Interface (MDI). The RJ45 connector has built-in magnetics and spark-gap capacitor. The PHY is available on the board in order to demonstrate the Lattice Ethernet Media Access (MAC) IP core. However, it is also possible to use the PHY to evaluate a custom MAC solution. Refer to the schematic and the National Semiconductor DP83865 Data Sheet for detailed information about the operation of the Ethernet PHY interface on this device. Refer to Table 13 for a description of the ethernet PHY connections. Table 13. 10/100/1000 Ethernet PHY Connection Summary Schematic Name LatticeXP Pin Location ETH_CLK_TO_MAC L4 ETH_COL W1 ETH_CRS W2 ETH_EGP0 J1 ETH_EGP2 K2 ETH_EGP4 K3 ETH_EGP5 J3 ETH_EGP6 K1 ETH_EGP7 L2 ETH_GTX_CLK N4 ETH_MAC_CLK_EN L3 ETH_MDC M1 ETH_MDIO L1 ETH_RESET_N Y1 ETH_RX_CLK P1 ETH_RX_D0 T3 ETH_RX_D1 N2 ETH_RX_D2 U4 ETH_RX_D3 U3 ETH_RX_D4 U2 ETH_RX_D5 P2 ETH_RX_D6 V4 ETH_RX_D7 V3 ETH_RX_DV V2 ETH_RX_ER V1 ETH_TX_CLK H2 ETH_TX_D0 M4 ETH_TX_D1 N3 ETH_TX_D2 R1 ETH_TX_D3 P4 ETH_TX_D4 P3 ETH_TX_D5 M3 ETH_TX_D6 T1 ETH_TX_D7 R4 ETH_TX_EN R3 ETH_TX_ER T4 12 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Required Board Modification The LatticeXP Advanced Evaluation Board uses the National Semiconductor DP83865 GigaPhyter Ethernet PHY to provide network access. Lattice has discovered that the circuit placed on the XP Advanced board prevents correct operation upon applying power to the board. In order for the Ethernet PHY to operate it is mandatory to modify the evaluation board. The tuned crystal oscillator circuit providing the 25MHz input clock to the GigaPhyter device is incorrect. A parallel termination resistor, R54, was placed according to guidelines published by National Semiconductor. The value selected for the termination resistor has been determined to be incorrect. The resistor attenuates the clock preventing the tuned circuit from providing sufficient output swing to the DP83865. This termination resistor is optional. R54 must be removed for the DP83865 to operate. Putting the PHY into GMII Mode Lattice has also determined the PHY device will power up in RGMII mode and the TX_CLK and RX_CLK signals will not oscillate. The PHY needs to be put into GMII mode. The DP83865 enters GMII mode in one of two ways. The first is by writing to the AUX_CTRL register using the MDIO interface. The second is by applying a pull-down resistor to the RGMII_EN[1] configuration pin. The configuration pin is read at power up, placing the DP83865 into GMII mode. To make the DP83865 enter GMII mode at power up tie the DP83865 side of R71 to ground through a current limiting resistor. This rework is not mandatory. You can use MDIO transactions to write into the DP83865’s registers, putting it into GMII mode. Using MDIO write the Auxiliary Control Register (AUX_CTRL) address 0x12, bits 13:12. The register description is as follows: RGMII ENABLE: These two bits control RGMII mode or MII/GMII mode. RGMII_EN[1:0] 11 = RGMII - 3COM mode 10 = RGMII - HP mode 01 = GMII mode 00 = GMII mode Lattice has tested putting a current-limiting pull-down resistor on the board. This will pull the TX_CLK / RGMII_SEL[1] bit to a ‘0’ on power-up, putting the device automatically into GMII mode. This is based on the data sheet: RGMII_SEL1 RGMII_SEL0 0 0 GMII MAC Interface 0 1 GMII 1 0 RGMII – HP 1 1 RGMII – 3COM In this example, a current limiting resistor of 2.2K was used. You can see the picture below of the fix. A resistor was soldered to R71 and a wire was soldered to the ground terminal of SMA J7. 13 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Figure 6. Board Fix, R71 to GND From the Ethernet PHY schematic in EB13, LatticeXP Advanced Evaluation Board User’s Guide, the fix would look like the figure below. Figure 7. Schematic Diagram of R71 Fix R71 [6] ETH_TX_CLK 33 CR0402 60 TX_CLK/RGMII_SEL0 PCI Interface The LatticeXP Advanced Evaluation Board includes a PCI bus interface. The PCI interface is capable of 33MHz operation, and provides a 32-bit data bus path. The board is designed to plug into 3.3V PCI systems exclusively since the LatticeXP I/O pins are not 5V tolerant. Figure 8 shows the PCI plated fingers and the notches used to prevent insertion into the wrong kind of backplane. Visit the Lattice web site at www.latticesemi.com/boards to download a test evaluation package for the PCI interface. Refer to Table 14 for a description of the PCI connections. Figure 8. PCI Backplane Keys 3.3V key slot 5V key slot perforated fiber filled By default, the board is fabricated with the 5V cutout filled. In order to allow the board to be inserted into all PCI backplanes the 5V cutout is fabricated to permit it to be cut away. If the 5V cutout fiberglass is removed, Lattice does not take responsibility for damage to the FPGA, the evaluation board or the system the evaluation board is inserted into, should it occur. 14 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor The PCI traces are routed to the bottom (banks 4 and 5) of the LatticeXP FPGA. The pins on the top and bottom of the FPGA have PCI clamp diodes integrated into the I/O pins. The PCI clock, however, is routed to one of the PLL input pins. The PLL input pins reside on the left and right sides of the FPGA. The left and right side of the device do not have clamp diodes. To compensate for this, the board includes space to install PCI clamp diodes, if desired. Visit the Lattice web site at www.latticesemi.com/boards to download a test evaluation package for the PCI interface. Refer to Table 14 for a description of the PCI connections. Table 14. PCI Connection Summary Schematic Name LatticeXP Pin Location PCI_ACK64_N AA20 PCI_AD0 AB18 PCI_AD1 AA18 PCI_AD10 AB15 PCI_AD11 AA15 PCI_AD12 W13 PCI_AD13 W12 PCI_AD14 AB14 PCI_AD15 AA14 PCI_AD16 AA12 PCI_AD17 AA10 PCI_AD18 Y8 PCI_AD19 AB8 PCI_AD2 Y18 PCI_AD20 AA8 PCI_AD21 Y7 PCI_AD22 AB7 PCI_AD23 AA7 PCI_AD24 Y10 PCI_AD25 Y9 PCI_AD26 AB6 PCI_AD27 AA6 PCI_AD28 AB5 PCI_AD29 AA5 PCI_AD3 AB17 PCI_AD30 AB4 PCI_AD31 W9 PCI_AD4 Y14 PCI_AD5 Y13 PCI_AD6 AA17 PCI_AD7 Y17 PCI_AD8 AB16 PCI_AD9 AA16 PCI_CBE0_N AA19 PCI_CBE1_N Y20 PCI_CBE2_N W14 PCI_CBE3_N W15 PCI_CLK U1 15 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Table 14. PCI Connection Summary (Continued) Schematic Name LatticeXP Pin Location PCI_DEVSEL_N AB10 PCI_FRAME_N AB11 PCI_GNT_N AB3 PCI_IDSEL AB19 PCI_INTA_N W6 PCI_INTB_N Y6 PCI_INTC_N Y4 PCI_INTD_N Y5 PCI_IRDY_N Y11 PCI_LOCK_N AA9 PCI_PAR W11 PCI_PERR_N W10 PCI_PRSNT1_N AB12 PCI_PRSNT2_N Y19 PCI_REQ64_N AB20 PCI_REQ_N AA3 PCI_RST_N AA4 PCI_SERR_N AB9 PCI_STOP_N AA11 PCI_TRDY_N Y12 Double Data Rate SDRAM The evaluation board includes a SODIMM DDR SDRAM socket. The LatticeXP is well suited to interfacing to DDR SDRAM memories. The LatticeXP FPGA family has dedicated I/O pins for controlling the Data Qualification Strobe (DQS) pin implemented in DDR. The DQS pin is used to signal valid data is present on the data bus. The FPGA provides a dedicated DQS I/O pin for each eight data bits on the DDR bus. Each DQS I/O spans 13 other LatticeXP I/O pins. Thus the eight data bits can be assigned to a wide range of FPGA pins. The high number of I/O pins available improves the likelihood of successfully routing the data bus on a PCB. A standard SODIMM socket provides 64 data bits. The LatticeXP Advanced Evaluation Board only connects to 16 data bus bits. This subset is chosen to provide a demonstration of the DDR capabilities of the LatticeXP while still permitting other interfaces to be showcased. All of the remaining DDR control signals, including the serial data bus, are connected to the LatticeXP FPGA. The DDR memory interface operates up to a 166MHz clock rate. The DDR specifies a fairly rigid set of requirements with respect to the reference and termination voltages. In order to meet these requirements the evaluation board uses a National Semiconductor LP2995 DDR power management chip. The LP2995 accepts a 2.5V input and provides a regulated VREF and VTT supply for the SODIMM socket. Visit the Lattice web site at www.latticesemi.com/boards to download a test evaluation package for the DDR SDRAM interface. Refer to Table 15 for a description of the DDR SDRAM connections. Table 15. DDR SDRAM Connection Summary Schematic Name LatticeXP Pin Location DDR_A0 R19 DDR_A1 R21 DDR_A10 T22 DDR_A11 M19 DDR_A12 M22 16 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Table 15. DDR SDRAM Connection Summary (Continued) Schematic Name LatticeXP Pin Location DDR_A2 P19 DDR_A3 R22 DDR_A4 P22 DDR_A5 P20 DDR_A6 N19 DDR_A7 P21 DDR_A8 M20 DDR_A9 N21 DDR_BA0 V22 DDR_BA1 T19 DDR_CAS_N T20 DDR_CK0 H19 DDR_CK0_N G19 DDR_CKE0 J20 DDR_CKE1 J19 DDR_DM0 D22 DDR_DM1 K21 DDR_DQ0 F21 DDR_DQ1 E22 DDR_DQ10 K22 DDR_DQ11 L22 DDR_DQ12 J21 DDR_DQ13 K19 DDR_DQ14 L19 DDR_DQ15 L20 DDR_DQ2 F22 DDR_DQ3 G22 DDR_DQ4 D21 DDR_DQ5 E21 DDR_DQ6 F20 DDR_DQ7 H20 DDR_DQ8 H22 DDR_DQ9 J22 DDR_DQS0 G21 DDR_DQS1 K20 DDR_RAS_N U19 DDR_S0_N W22 DDR_S1_N U20 DDR_SA0 V21 DDR_SA1 W21 DDR_SA2 Y22 DDR_SCL V19 DDR_SDA V20 DDR_WE_N U21 17 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor FCRAM Interface The LatticeXP FPGA is connected to a single eight-bit FCRAM device. The LatticeXP Advanced Evaluation Board always has a quantity of scratch RAM since the FCRAM memory, unlike the DDR memory, cannot be removed. With the addition of an FCRAM memory controller into the FPGA, the FCRAM memory can be used to store data. Operation of the FCRAM memory is similar, but not identical to, the DDR memory interface. Like DDR, FCRAM memories depend on a DQS to qualify when data is valid on the bus. This means the DQS hardware built into the LatticeXP can be used to improve data transfer reliability in the same way it is used in DDR. Visit the Lattice web site at www.latticesemi.com/boards to download a test evaluation package for the FCRAM interface. Refer to Table 16 for a description of the FCRAM connections. Table 16. FCRAM Connection Summary Schematic Name LatticeXP Pin Location FCRAM_PD_N B6 FC_A0 A21 FC_A1 A20 FC_A10 B14 FC_A11 C14 FC_A12 D14 FC_A13 D13 FC_A14 C12 FC_A2 B20 FC_A3 A19 FC_A4 B19 FC_A5 B17 FC_A6 A15 FC_A7 B15 FC_A8 D15 FC_A9 A14 FC_BA0 B7 FC_BA1 C6 FC_CLK C9 FC_CLK_N C10 FC_CS_N B5 FC_DQ0 C7 FC_DQ1 B8 FC_DQ2 C8 FC_DQ3 A9 FC_DQ4 D11 FC_DQ5 B10 FC_DQ6 A11 FC_DQ7 B11 FC_DQS B9 FC_FN A5 18 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Ordering Information Description Ordering Part Number LatticeXP10C Evaluation Board - Advanced China RoHS Environment-Friendly Use Period (EFUP) LFXP10C-H-EV 10 Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Change Summary July 2005 01.0 Initial release. March 2007 01.1 Added Ordering Information section. April 2007 01.2 Added important information for proper connection of ispDOWNLOAD (Programming) Cables. September 2009 01.3 © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 19 LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor Appendix A. Schematics 20 A B C D [ 6] [ 6] [ 8] V C C _ 3 .3 V TP _ W 8 TP _ A B 2 1 2 V C C _ 3 .3 V AB9 AA9 W 10 W 11 P C I _ P E R R_ N P C I _ PAR C5 5 0 .1 u F P C I _ I R D Y_ N P C I _ TR D Y _ N 5 RE S E RV E D C6 2 0 .1 u F PB21A PB21B PB30A PB30B PB29A PB29B PB28A PB28B PB27A PB27B PB39A PB38A PB38B PB37A PB37B PB36A PB36B V CCIO 4 _ R1 5 V CCIO 4 _ T1 2 V CCIO 4 _ T1 3 V CCIO 4 _ T1 4 V CCIO 4 _ T1 5 D Q S r each PB35A PB35B DQ S /P B 3 4 A PB34B PB33B PB32A V RE F2 _ 4 /P B 3 1 A PB31B D Q S r each DQ S / P B 2 6 A V RE F1 _ 4 /P B 2 6 B PB25B PB24A PB23A PB23B P CL K T4 _ 0 /P B 2 2 A P CL K C4 _ 0 /P B 2 2 B C7 6 10uF CC0 8 0 5 D Q S r each L FX P 1 0 C-4 F3 8 8 CE S V CCIO 5 _ R8 V CCIO 5 _ T1 0 V CCIO 5 _ T1 1 V CCIO 5 _ T8 V CCIO 5 _ T9 PB20A PB20B PB19A PB19B P B 1 8 A / DQ S PB18B PB17B PB16A PB15A PB15B PB14A PB14B PB13A PB13B PB12A P B 1 2 B /V RE F2 _ 5 D Q S r each PB11A PB11B P B 1 0 A /DQ S PB10B PB9B PB8A P B 7 A /V RE F1 _ 5 PB7B PB6A PB6B PB5A PB5B PB4A PB4B PB3A PB3B PB2A BANK 4 LFXP10C (fpBGA388) (2 OF 5) BANK 5 U4 B C6 1 0 .1 u F R8 T1 0 T1 1 T8 T9 Y1 1 Y1 2 P C I _ S TO P _ N A A 1 1 P C I _ F R A ME _ N A B 1 1 P C I _ DE V S E L _ NA B 1 0 P C I _ A D1 7 AA10 AB8 Y8 P C I _ A D2 1 P C I _ A D2 0 P C I _ A D1 9 P C I _ A D1 8 Y7 AA8 P C I _ A D2 3 P C I _ A D2 2 P C I _ S E R R_ N P C I _ L O CK _ N Y9 Y1 0 AA7 AB7 P C I _ A D2 5 P C I _ A D2 4 AA6 AB6 Y6 AB5 P C I _ A D2 7 P C I _ A D2 6 P C I _ I N TB _ N P C I _ A D2 8 W8 W9 AB4 AA5 P C I _ A D3 0 P C I _ A D2 9 AB3 AA4 P C I _ A D3 1 AB2 AA3 P C I _ R EQ_N P C I _ G NT_ N P C I _ R S T_ N Y4 Y5 P C I _ I N TC _ N P C I _ I N TD _ N W5 W6 5 P C I _ I N TA _ N R8 5 10K CR0 4 0 2 1 2 1 2 R1 5 T1 2 T1 3 T1 4 T1 5 W 16 AA22 Y2 1 AB21 AA21 P R I _ C LK_N P R I _ CL K _ P 4 [ 6] C7 3 0 .1 u F [ 8] TP _ W 1 6 [ 6] TP_A A 2 2 [ 6] TP _ Y2 1 C6 9 0 .1 u F 1 1 G ND G ND G ND G ND 2 3 4 5 G ND G ND G ND G ND 2 3 4 5 C8 7 10uF CC0 8 0 5 J6 S M A C o n n ector th _ sma S J7 S M A C o n n ector th _ sma S P R I _ C L K _ P a n d P R I _ C L K _N are matched l e n g t h p a i r e d traces. [ 6] TP_A B 2 1 [ 6] TP_A A 2 1 4 V C C _ 3 .3 V C7 2 0 .1 u F P C I _ R EQ64_N P C I _ A CK 6 4 _ N P C I _ C BE2_N P C I _ C BE3_N W 14 W 15 AB20 AA20 P C I _ I DS E L P C I _ C BE0_N P C I _ C BE1_N AB19 P C I _ P R S NT2 _ N P C I _ A D1 P C I _ A D0 P C I _ A D3 P C I _ A D2 P C I _ A D5 P C I _ A D4 P C I _ A D7 P C I _ A D6 AA19 Y2 0 Y1 9 AA18 AB18 AB17 Y1 8 Y1 3 Y1 4 Y1 7 AA17 P C I _ A D1 1 P C I _ A D1 0 P C I _ A D9 P C I _ A D8 AA16 AB16 P C I _ A D1 2 P C I _ A D1 3 P C I _ A D1 5 P C I _ A D1 4 AA15 AB15 W 13 W 12 AA14 AB14 AB13 AA13 AB12 AA12 P C I _ P R S NT1 _ N P C I _ A D1 6 1 2 1 2 V C C _ 3 .3 V [ 5] P C I _ C L K [ 5] P C I _ TDO P C I _ TCK [ 8] [ 5] [ 5] P C I _ T D I P CI_ TMS P C I _ CL K P C I _ TDO P C I _ TCK V C C _ 3 .3 V V C C _ 3 .3 V P C I _ TDI P CI_ TMS 3 3 P C I _ TR D Y _ N P C I _ F R A ME _ N P C I _ A D1 6 P C I _ A D1 8 P C I _ A D2 0 P C I _ A D2 2 P C I _ I DS E L P C I _ A D2 4 P C I _ A D2 6 P C I _ A D2 8 P C I _ A D3 0 P C I _ G NT_ N P C I _ R S T_ N P C I _ I N TC _ N P C I _ I N TA _ N 2 P C I _ C BE2_N P C I _ A D1 7 P C I _ A D1 9 P C I _ A D2 1 P C I _ A D2 3 P C I _ C BE3_N P C I _ A D2 5 P C I _ A D2 7 P C I _ A D2 9 P C I _ A D3 1 P C I _ R EQ_N P C I _ P R S NT2 _ N P C I _ P R S NT1 _ N P C I _ I N TD _ N P C I _ I N TB _ N J2 0 P C I E D G E C O N N S o l d er S id e [ 8] P C I _ G ND_ 5 7 1 2 3 4 5 6 7 8 9 10 11 TRST# +12V TMS TDI +5V_5 INTA# INTC# +5V_8 Reserved_9 +3.3V_10 Reserved_11 J3 P C I E D G E C O N N C o m p o n en t S id e 2 1 2 3 4 5 6 7 8 9 10 11 -12V TCK Ground_3 TDO +5V_5 +5V_7 INTB# INTD# PRSNT1# Reserved_10 PRSNT2# 1 2 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 3.3VAUX RST# +3.3V_16 GNT# Ground_18 PME# AD[30] +3.3V_21 AD[28] AD[26] Ground_24 AD[24] IDSEL +3.3V_27 AD[22] AD[20] Ground_30 AD[18] AD[16] +3.3V_33 FRAME# Ground_35 TRDY# Ground_37 STOP# +3.3V_39 Reserved_40 Reserved_41 Ground_42 PAR AD[15] +3.3V_45 AD[13] AD[11] Ground_48 AD[09] 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Reserved_14 Ground_15 CLK Ground_17 REQ# +3.3V_19 AD[31] AD[29] Ground_22 AD[27] AD[25] +3.3V_25 C/BE#[3] AD[23] Ground_28 AD[21] AD[19] +3.3V_31 AD[17] C/BE#[2] Ground_34 IRDY# +3.3V_36 DEVSEL# Ground_38 LOCK# PERR# +3.3V_41 SERR# +3.3V_43 C/BE#[1] AD[14] Ground_46 AD[12] AD[10] Ground_49 P C I _ S TO P _ N P C I _ PAR P C I _ A D1 5 P C I _ A D1 3 P C I _ A D1 1 P C I _ A D9 P C I _ C BE0_N P C I _ A D6 P C I _ A D4 P C I _ A D2 P C I _ A D0 P C I _ R EQ64_N 52 53 54 55 56 57 58 59 60 61 62 P C I _ I R D Y_ N P C I _ DE V S E L _ N P C I _ L O CK _ N P C I _ P E R R_ N P C I _ S E R R_ N P C I _ C BE1_N P C I _ A D1 4 P C I _ A D1 2 P C I _ A D1 0 P C I _ A D8 P C I _ A D7 P C I _ A D5 P C I _ A D3 P C I _ A D1 P C I _ A CK 6 4 _ N C/BE#[0] +3.3V_53 AD[06] AD[04] Ground_56 AD[02] AD[00] +3.3V_59 REQ64# +5V_61 +5V_62 52 53 54 55 56 57 58 59 60 61 62 21 1 F r i d a y, A p r i l 2 9 , 2 0 0 5 D o c u m e n t N u m b er < D o c> 32-Bit PCI 1 S h eet 2 of 9 Rev B L a t t i c e S e m i c o n d u c t o r C o r p o r a t i on D at e: Size C Ti tle AD[08] AD[07] +3.3V_54 AD[05] AD[03] Ground_57 AD[01] +3.3V_59 ACK64# +5V_61 +5V_62 A B C D Lattice Semiconductor LatticeXP Advanced Evaluation Board User’s Guide Figure 9. 32-Bit PCI A B C DDR_ S DA DDR_ S CL S O DIMM_ A 1 0 S O DIMM_ B A 0 S O DIMM_ W E _ N S O DIMM_ S 0 _ N S O DIMM_ A 7 S O DIMM_ A 5 S O DIMM_ A 3 S O DIMM_ A 1 S O DIMM_ A 1 2 S O DIMM_ A 9 S O DIMM_ CK E 1 S O DIMM_ CK 0 S O D I MM_ CK 0 _ N S O DIMM_ DQ 1 0 S O DIMM_ DQ 1 1 S O DIMM_ DQ 9 S O DIMM_ DQ S 1 S O DIMM_ DQ 3 S O DIMM_ DQ 8 S O DIMM_ DQ S 0 S O DIMM_ DQ 2 S O DIMM_ DQ 0 S O DIMM_ DQ 1 V RE F VSS DQ 0 DQ 1 V DD DQ S 0 DQ 2 VSS DQ 3 DQ 8 V DD DQ 9 DQ S 1 VSS DQ 1 0 DQ 1 1 V DD CK 0 CK 0 # VSS V RE F VSS DQ 4 DQ 5 V DD DM0 DQ 6 VSS DQ 7 DQ 1 2 V DD DQ 1 3 DM1 VSS DQ 1 4 DQ 1 5 V DD V DD VSS VSS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 DQ 1 6 DQ 1 7 V DD DQ S 2 DQ 1 8 VSS DQ 1 9 DQ 2 4 V DD DQ 2 5 DQ S 3 VSS DQ 2 6 DQ 2 7 V DD (CB 0 ) (CB 1 ) VSS (DQ S 8 ) (CB 2 ) V DD (CB 3 ) NC_ 8 5 VSS (CK 2 ) (CK 2 # ) V DD (CK E 1 ) NC_ 9 7 A12 A9 VSS A7 A5 A3 A1 V DD A10 BA0 W E# S0# NC_ 1 2 3 VSS DQ 3 2 DQ 3 3 V DD DQ S 4 DQ 3 4 VSS DQ 3 5 DQ 4 0 V DD DQ 4 1 DQ S 5 VSS DQ 4 2 DQ 4 3 V DD V DD VSS VSS DQ 4 8 DQ 4 9 V DD DQ S 6 DQ 5 0 VSS DQ 5 1 DQ 5 6 V DD DQ 5 7 DQ S 7 VSS DQ 5 8 DQ 5 9 V DD S DA S CL V DDS P D NC_ 1 9 9 DQ 2 0 DQ 2 1 V DD DM2 DQ 2 2 VSS DQ 2 3 DQ 2 8 V DD DQ 2 9 DM3 VSS DQ 3 0 DQ 3 1 V DD (CB 4 ) (CB 5 ) VSS (DM8 ) (CB 6 ) V DD (CB 7 ) NC_ 8 6 VSS VSS V DD V DD CK E 0 NC_ 9 8 A11 A8 VSS A6 A4 A2 A0 V DD BA1 RA S # CA S # (S 1 # ) NC_ 1 2 4 VSS DQ 3 6 DQ 3 7 V DD DM4 DQ 3 8 VSS DQ 3 9 DQ 4 4 V DD DQ 4 5 DM5 VSS DQ 4 6 DQ 4 7 V DD (CK 1 # ) (CK 1 ) VSS DQ 5 2 DQ 5 3 V DD DM6 DQ 5 4 VSS DQ 5 5 DQ 6 0 V DD DQ 6 1 DM7 VSS DQ 6 2 DQ 6 3 V DD SA0 SA1 SA2 (V S S ) 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 5 2 . 5 V D D R 2 0 0 - p i n S O -DIMM S ocket 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 X U2 B 2 . 5 V D D R 2 0 0 - p i n S O -DIMM S ocket 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 X U2 A 1 7 V DDQ D D R _ SA0 D D R _ SA1 D D R _ SA2 S O DIMM_ CK 0 S O D IMM_ CK 0 _ N S O DIMM_ DQ 1 1 S O DIMM_ DQ 1 5 S O DIMM_ DQ 3 S O DIMM_ DQ 7 S O DIMM_ DQ 1 4 S O DIMM_ DM1 S O DIMM_ DQ 1 3 S O DIMM_ DQ 1 2 S O DIMM_ DQ 1 0 S O DIMM_ DQ S 1 S O DIMM_ DQ 9 S O DIMM_ DQ 8 3 3 741X083 RN1 9 S O DIMM_ DQ 6 S O DIMM_ DM0 S O DIMM_ DQ 5 S O DIMM_ DQ 4 S O DIMM_ DQ 2 S O DIMM_ DQ S 0 S O DIMM_ DQ 1 S O DIMM_ DQ 0 3 3 741X083 RN1 8 V S E NS E V TT V RE F S O DIMM_ A 1 0 S O DIMM_ A 1 S O DIMM_ A 3 S O DIMM_ A 5 S O DI MM_ A 7 S O DIMM_ A 9 S O DIMM_ A 1 2 S O DIMM_ CK E 1 S O DIMM_ CK E 0 S O DIMM_ A 1 1 S O DIMM_ A 8 S O DIMM_ A 6 S O DIMM_ A 4 S O DIMM_ A 2 S O DIMM_ A 0 S O DIMM_ B A 1 S O D IMM_ RA S _ N S O D IMM_ CA S _ N S O DIMM_ S 1 _ N S O DIMM_ S 0 _ N S O DIMM_ W E _ N S O DIMM_ B A 0 ( L e f t e nd of V T T i s land) C9 6 2 2 0 u F S izeD 3 3 741X083 RN2 1 S O DI MM_ B A 1 S O D I MM_ RA S _ N S O D I MM_ CA S _ N S O DIMM_ S 1 _ N S O DIMM_ A 6 S O DIMM_ A 4 S O DIMM_ A 2 S O DI MM_ A 0 S O DIMM_ A 1 1 S O DIMM_ A 8 S O DI MM_ CK E 0 S O DIMM_ DQ 1 4 S O DIMM_ DQ 1 5 S O DIMM_ DQ 1 3 S O DIMM_ DM1 S O DIMM_ DQ 7 S O DIMM_ DQ 1 2 S O DIMM_ DM0 S O DIMM_ DQ 6 P V IN A V IN GND 2 6 C8 9 47uF S izeD S O DIMM_ DQ 4 S O DIMM_ DQ 5 2 4 3 8 1 2 4 22 22 RN1 7 1 2 3 4 R N7 1 2 3 4 22 22 741X083 DDR_ RA S _ N 8 DDR_ CA S _ N 7 D D R _ S 1 _N 6 5 741X083 D D R _ S 0 _N 8 D D R _ W E _N 7 D D R _ BA0 6 5 741X163 D D R _ C K E0 16 D D R _ A11 15 D D R _ A8 14 D D R _ A6 13 D D R _ A4 12 D D R _ A2 11 D D R _ A0 10 D D R _ BA1 9 741X163 D D R _ A10 16 D D R _ A1 15 D D R _ A3 14 D D R _ A5 13 D D R _ A7 12 D D R _ A9 11 D D R _ A12 10 D D R _ C K E1 9 2 2CR0 4 0 2D D R _ C K 0 2 2CR0 4 0 2D D R _ C K 0 _ N 2 2CR0 4 0 2D D R _ D Q 1 1 2 2CR0 4 0 2D D R _ D Q 1 5 2 2CR0 4 0 2D D R _ D Q 3 2 2CR0 4 0 2D D R _ D Q 7 D D R _ D Q 14 D D R _ D M1 D D R _ D Q 13 D D R _ D Q 12 741X083 D D R _ D Q 10 8 D D R _ D Q S1 7 DDR_ DQ 9 6 DDR_ DQ 8 5 RN1 5 1 2 3 4 22 3 3 741X083 RN1 1 V TT RN1 6 1 2 3 4 5 6 7 8 3 3 741X163 RN1 0 V TT R N6 1 2 3 4 5 6 7 8 3 3 741X163 RN2 0 V TT R1 7 R1 8 R1 6 R9 6 R9 9 R1 9 R1 0 0 R2 0 33 33 33 33 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 R1 5 R9 5 V TT 741X083 2 2 8 7 6 5 R N5 1 2 3 4 DDR_ DQ 6 D D R _ D M0 DDR_ DQ 5 DDR_ DQ 4 741X083 DDR_ DQ 2 8 D D R _ D Q S0 7 DDR_ DQ 1 6 DDR_ DQ 0 5 RN1 4 1 2 3 4 22 3 3 741X083 R N9 V TT 741X083 2 2 8 7 6 5 R N4 1 2 3 4 3 3 741X083 R N8 V TT C9 5 220uF S izeD ( R i g h t en d o f V T T i s land) V TT V R E F_ 2 .5 V 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 D 1 2 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 8 7 6 5 5 V TT 2 3 4 5 2 3 4 5 1 2 V C C _ 2 .5 V 3 S 1 1 SMA_ T2 1 R9 4 100 CR0 4 0 2 N o P o p u late S MA _ U2 2 C9 4 0 .1 u F CC0 4 0 2 3 C9 3 0 .1 u F CC0 4 0 2 C9 2 0 .1 u F CC0 4 0 2 D D R _ A11 D D R _ A8 2 D Q S r each D Q S r each 2 C7 8 0 .1 u F CC0 4 0 2 L FX P 1 0 C-4 F3 8 8 CE S V CCIO 3 _ M1 6 V CCIO 3 _ N1 6 V CCIO 3 _ P 1 6 V CCI O 3 _ R1 6 P R3 5 A P R3 5 B P R3 4 A /P L L 3 _ FB _ T P R3 4 B /P L L 3 _ FB _ C P R3 3 A /DQ S P R3 3 B P R3 2 B P R3 1 A /V RE F1 _ 3 P R3 0 A P R3 0 B P R2 9 A P R2 9 B P R2 8 A P R2 8 B P R2 6 A P R2 6 B P R2 5 A / P L L 3 _ IN_ T P R2 5 B / P L L 3 _ IN_ C P R2 4 A /DQ S P R2 4 B P R2 3 B P R2 2 A / V RE F2 _ 3 P R2 1 A P R2 1 B P R2 0 A P R2 0 B P R1 9 A P R1 9 B BANK 2 P R2 A P R2 B P R1 1 A P R1 1 B C8 6 10uF CC0 8 0 5 P R1 8 A P R1 8 B V CCIO 2 _ H1 6 V CCIO 2 _ J1 6 V CCIO 2 _ K 1 6 V CCI O 2 _ L 1 6 D Q S r each P CL K T2 _ 0 /P R1 7 A P CL K C2 _ 0 /P R1 7 B DQ S /P R1 6 A P R1 6 B P R1 5 B V RE F1 _ 2 /P R1 4 A P R1 3 A P R1 3 B P L L 4 _ IN_ T/P R1 2 A P L L 4 _ I N_ C/ P R1 2 B D Q S r each P R9 A P R9 B P R8 A P R8 B DQ S /P R7 A P R7 B P R6 B V RE F2 _ 2 /P R5 A P R4 A P R4 B P L L 4 _ FB _ T/P R3 A P L L 4 _ FB _ C/ P R3 B LFXP10C (fpBGA388) (3 OF 5) BANK 3 U4C C7 9 0 .1 u F CC0 4 0 2 M1 6 N1 6 P16 R1 6 T1 9 T2 0 D D R _ BA1 DDR_ CA S _ N V C C _ 2 .5 V V20 V19 U2 0 U1 9 DDR_ S DA DDR_ S CL R1 9 R2 0 Y2 2 W 21 D D R _ S 1 _N DDR_ RA S _ N D D R _ A0 V R E F_ 2 .5 V D D R _ SA2 D D R _ SA1 P20 P19 W 22 V21 D D R _ S 0 _N D D R _ SA0 D D R _ A5 D D R _ A2 V22 U2 1 U2 2 T2 1 T2 2 R2 1 D D R _ BA0 D D R _ W E _N D D R _ A10 D D R _ A1 N1 9 N2 0 V R E F_ 2 .5 V D D R _ A6 P22 R2 2 N2 1 P21 M1 9 M2 0 D D R _ A4 D D R _ A3 D D R _ A9 D D R _ A7 C4 0 .1 u F CC0 4 0 2 [ 8] R9 7 2K CR0 6 0 3 V R E F_ 2 .5 V C5 0 .1 u F CC0 4 0 2 R9 8 2K CR0 6 0 3 C9 1 0 .1 u F CC0 4 0 2 V C C _ 2 .5 V T r a c e s f r o m S M A _ U 2 2 and SMA_T21 a r e 5 0 o h m i m p e d e n c e , and are matched l e n g t h p a i r e d traces. J1 1 S M A C o n n ector th _ sma G ND G ND G ND G ND S J1 2 S M A C o n n ector th _ sma G ND G ND G ND G ND T e r m i n a t i o n r e s i s t o r s h ou ld be a s clo s e t o U 5 a s p ossible. 1 2 1 2 4 1 2 U5 LP2995 1 2 H1 6 J1 6 K16 L16 L22 M2 2 K21 K22 K20 L19 L20 L21 J2 1 J2 2 H2 1 H2 2 J1 9 K19 H2 0 J2 0 G19 H1 9 G21 G22 F2 0 G20 F2 1 F2 2 E21 E22 D2 1 D2 2 C7 5 0 .1 u F CC0 4 0 2 [ 8] C8 4 10uF CC0 8 0 5 V R E F_ 2 .5 V 1 C8 1 0 .1 u F CC0 4 0 2 TP _ H2 1 [ 6] C8 3 0 .1 u F CC0 4 0 2 F r i d a y, A p r i l 2 9 , 2 0 0 5 D o c u m e n t N u m b er < D o c> DDR SDRAM 1 S h eet 3 of 9 Rev B L a t t i c e S e m i c o n d u c t o r C o r p o r a t i on D at e: Size C Ti tle C7 4 0 .1 u F CC0 4 0 2 V C C _ 2 .5 V D D R _ D Q 11 D D R _ A12 D D R _ D M1 D D R _ D Q 10 D D R _ D Q S1 D D R _ D Q 14 D D R _ D Q 15 V R E F_ 2 .5 V D D R _ D Q 12 DDR_ DQ 9 DDR_ DQ 8 D D R _ C K E1 D D R _ D Q 13 DDR_ DQ 7 D D R _ C K E0 DDR_ CK 0 _ N DDR_ CK 0 D D R _ D Q S0 DDR_ DQ 3 DDR_ DQ 6 V R E F_ 2 .5 V DDR_ DQ 0 DDR_ DQ 2 DDR_ DQ 5 DDR_ DQ 1 DDR_ DQ 4 D D R _ D M0 1 5 1 2 1 2 1 2 1 2 22 2 A B C D Lattice Semiconductor LatticeXP Advanced Evaluation Board User’s Guide Figure 10. DDR SDRAM A B C D FC_ P D_ N FC_ B A 0 FC_ B A 1 FC_ A 1 0 FC_ A 0 FC_ A 1 FC_ A 2 FC_ A 3 FC_ A 1 4 FC_ A 1 3 F C _ FN FC_ CS _ N FC_ A 1 2 FC_ A 1 1 FC_ A 9 FC_ A 8 FC_ A 7 FC_ A 6 FC_ A 5 FC_ A 4 FC_ DQ S F C _ D Q7 F C _ D Q6 F C _ D Q5 F C _ D Q4 F C _ D Q0 F C _ D Q1 F C _ D Q2 F C _ D Q3 F C R A M_ B A 0 F C R A M_ B A 1 FCRA M_ A 1 0 F C R A M_ A 0 F C R A M_ A 1 F C R A M_ A 2 F C R A M_ A 3 FCRA M_ A 1 4 FCRA M_ A 1 3 FCRA M_ FN F C R A M _ C S_N R N1 1 2 3 4 5 R N3 1 2 3 4 5 6 7 8 R N2 1 2 3 4 22 VSS_66 DQ 7 VSSQ_64 NC_ 6 3 DQ 6 V DDQ _ 6 1 NC_ 6 0 DQ 5 VSSQ_58 NC_ 5 7 DQ 4 V DDQ _ 5 5 NC_ 5 4 NC_ 5 3 VSSQ_52 DQ S NC_ 5 0 V RE F VSS_48 NC_ 4 7 /CL K CL K /P D NC_ 4 3 A12 A11 A9 A8 A7 A6 A5 A4 VSS_34 22 22 C4 3 0 .1 u F CC0 4 0 2 FCRA M_ A 1 2 FCRA M_ A 1 1 F C R A M_ A 9 F C R A M_ A 8 F C R A M_ A 7 F C R A M_ A 6 F C R A M_ A 5 F C R A M_ A 4 F C R A M_ B A 0 F C R A M_ B A 1 FCRA M_ A 1 0 F C R A M_ A 0 F C R A M_ A 1 F C R A M_ A 2 F C R A M_ A 3 F C R A M _ P D_ N 741X163 16 15 14 13 12 11 10 9 741X083 FCRA M_ A 1 4 8 FCRA M_ A 1 3 7 FCRA M_ FN 6 F C R A M _ C S_N 5 RN1 3 1 2 3 4 5 6 7 8 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 C4 7 0 .1 u F CC0 4 0 2 F C R A M _ DQ S F C R A M _ DQ 7 F C R A M _ DQ 6 F C R A M _ DQ 5 F C R A M _ DQ 4 741X083 F C R A M _ DQ 0 8 F C R A M _ DQ 1 7 F C R A M _ DQ 2 6 F C R A M _ DQ 3 5 RN1 2 1 2 3 4 22 CR0 4 0 2 741X163 2 2 16 15 14 13 12 11 10 9 R7 0 U3 V DD_ 1 DQ 0 V DDQ _ 3 NC_ 4 DQ 1 VSSQ_6 NC_ 7 DQ 2 V DDQ _ 9 NC_ 1 0 DQ 3 VSSQ_12 NC_ 1 3 NC_ 1 4 V DDQ _ 1 5 NC_ 1 6 NC_ 1 7 V DD_ 1 8 NC_ 1 9 NC_ 2 0 A14 A13 FN /CS NC_ 2 5 BA0 BA1 A10 A0 A1 A2 A3 V DD_ 3 3 FCRA M TS O P II-6 6 -P -4 0 0 -0 .6 5 741X083 2 2 8 7 6 5 F C R A M _ DQ 3 F C R A M _ DQ 2 F C R A M _ DQ 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 1 2 1 2 1 2 1 2 C4 1 0 .1 u F CC0 4 0 2 C4 5 0 .1 u F CC0 4 0 2 C4 0 0 .1 u F CC0 4 0 2 C4 4 0 .1 u F CC0 4 0 2 V R E F_ 2 .5 V FCRA M_ A 1 2 FCRA M_ A 1 1 F C R A M_ A 9 F C R A M_ A 8 F C R A M_ A 7 F C R A M_ A 6 F C R A M_ A 5 F C R A M_ A 4 C3 9 0 .1 u F CC0 4 0 2 C4 2 0 .1 u F CC0 4 0 2 V R E F_ 2 .5 V R7 7 10K CR0 4 0 2 F C R A M _ CL K F C R A M _ CL K _ N F C R A M _ DQ S [ 3 ] , [ 8] F C R A M _ P D_ N R1 4 120 CR0 4 0 2 F C R A M _ DQ 4 F C R A M _ DQ 5 F C R A M _ DQ 6 F C R A M _ DQ 7 1 2 1 2 1 2 1 2 V C C _ 2 .5 V 4 4 1 2 3 HE A DE R 3 h d r3 x1 _ 1 0 0 m il JP 5 DIN_ 2 _ S DIN D I N _ 2 _ D0 D IN [ 5] TP _ B 1 2 TP _ A 1 6 TP _ B 1 6 TP _ D1 2 TP _ A 1 3 TP _ A 1 2 TP _ B 1 3 TP _ C2 2 TP _ C2 1 TP _ B 2 2 TP _ A 1 8 3 [ 6] [ 8] A15 B16 FC_ A 6 A19 B20 FC_ A 3 FC_ A 2 FC_ A 1 2 FC_ A 8 D Q S r each C7 0 0 .1 u F CC0 4 0 2 L FX P 1 0 C-4 F3 8 8 CE S FP B G A 3 8 8 C7 1 0 .1 u F CC0 4 0 2 D Q S r each V CCIO 1 _ G 1 2 V CCIO 1 _ G 1 3 V CCIO 1 _ G 1 4 V CCIO 1 _ G 1 5 V CCIO 1 _ H1 5 P T3 9 A P T3 8 A P T3 8 B P T3 7 A P T3 7 B P T3 6 A P T3 6 B P T3 5 A P T3 5 B P T3 4 A /DQ S P T3 4 B /V RE F1 _ 1 P T3 3 B P T3 2 A P T3 1 A P T3 1 B P T3 0 A /D0 P T3 0 B P T2 9 A /V RE F2 _ 1 P T2 9 B /D1 P T2 8 A /D2 P T2 8 B P T2 7 A P T2 7 B /D3 P T2 6 A /DQ S P T2 6 B P T2 5 B P T2 4 A /D4 P T2 3 A /D5 P T2 3 B P T2 2 A P T2 2 B /D6 P T2 1 A P T2 1 B /D7 BANK 0 P T9 B P T8 A P T7 A P T7 B P T6 A P T6 B P T5 A P T5 B P T4 A P T4 B P T3 A P T3 B P T2 A C8 0 10uF CC0 8 0 5 V CCIO 0 _ G 1 0 V CCIO 0 _ G 1 1 V CCIO 0 _ G 8 V CCIO 0 _ G 9 V CCIO 0 _ H8 CS 1 _ n /P T2 0 A B US Y/P T2 0 B P CL K T0 _ 0 /P T1 9 A P CL K C0 _ 0 /P T1 9 B DQ S /P T1 8 A P T1 8 B P T1 7 B DO UT/P T1 6 A W RITE _ n /P T1 5 A P T1 5 B V RE F1 _ 0 /P T1 4 A P T1 4 B DI/P T1 3 A P T1 3 B CS _ n /P T1 2 A P T1 2 B D Q S r each P T1 1 A P T1 1 B DQ S /P T1 0 A V RE F2 _ 0 /P T1 0 B LFXP10C (fpBGA388) (4 OF 5) BANK 1 U4D C6 4 0 .1 u F CC0 4 0 2 G12 G13 G14 G15 H1 5 C1 8 C2 0 C1 9 C2 2 C2 1 A21 B22 D1 4 D1 5 FC_ A 1 A20 V R E F_ 2 .5 V B 2 1 A18 B19 C1 3 C1 4 FC_ A 4 D I N _ 2 _ D0 FC_ A 1 1 A17 B18 A16 B17 A14 B15 FC_ A 5 D1 3 FC_ A 9 FC_ A 7 D1 2 A13 B14 A12 B13 C1 2 B12 FC_ A 1 3 FC_ A 1 0 FC_ A 1 4 FC_ A 0 TP _ B 2 2 V C C IO _ 1 TP _ C1 8 [ 6] TP _ C2 0 [ 6] TP _ C1 9 [ 6] [ 6] V R E F_ 2 .5 V [ 6] TP _ B 1 8 [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] 3 FC_ CS _ N 2 G10 G11 G8 G9 H8 B11 C1 1 A10 A11 B9 B10 D1 1 D1 0 C8 A9 A8 B8 A7 C7 C6 B7 C9 C1 0 B6 A6 A5 B5 A4 C5 F C _ D Q7 F C _ D Q6 FC_ DQ S F C _ D Q5 F C _ D Q4 DO UT F C _ D Q2 F C _ D Q3 V C C _ 3 .3 V C5 3 0 .1 u F CC0 4 0 2 1 2 3 4 5 6 7 R3 9 10K CR0 4 0 2 C2 0 0 .1 u F CC0 4 0 2 1 O S C_ CL K _ P L L F r i d a y, A p r i l 2 9 , 2 0 0 5 D o c u m e n t N u m b er < D o c> F C R AM 1 S h eet 4 of 9 Rev B L a t t i c e Semiconductor Corporatio n D at e: Size C 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 V C C _ 3 .3 V C6 3 10uF CC0 8 0 5 14 13 12 11 10 9 8 Y2 3 3 MHz DIP 1 4 Ti tle 14 13 12 11 10 9 8 16 15 14 13 12 11 10 9 X U1 DIP 1 6 DIP 1 6 F C R A M _ CL K F C R A M _ CL K _ N C5 6 0 .1 u F CC0 4 0 2 O S C _ C L K _ P RI O S C_ CL K _ P L L [ 5] [ 8] B USY V C C I O_0 V R E F_ 2 .5 V 1 2 0 CR0 4 0 2 1 2 0 CR0 4 0 2 [ 5] D0 V C C _ 3 .3 V R8 7 R8 6 [ 6] TP _ A 4 [ 6] TP _ C5 C5 4 0 .1 u F CC0 4 0 2 V R E F_ 2 .5 V F C _ D Q1 DIN_ 2 _ S DIN F C _ D Q0 FC_ B A 1 FC_ B A 0 F C _ C LK F C _ C L K _N FC_ P D_ N F C _ FN [ 6] TP _ A 2 [ 6] TP _ B 4 [ 6] TP _ D8 [ 6] TP _ D9 A2 B4 D8 D9 [ 6] TP _ B 3 [ 6] TP _ A 3 B3 A3 [ 6] [ 6] TP _ C3 [ 6] TP _ C4 TP _ D3 C3 C4 D3 2 1 1 2 F C R A M _ DQ 0 5 1 2 1 2 1 2 1 2 1 2 23 2 A B C D Lattice Semiconductor LatticeXP Advanced Evaluation Board User’s Guide Figure 11. FCRAM A B C D 1 2 3 4 5 6 7 8 9 10 TCK DO NE I N I TN TMS [ 6 ],[ 8] 1 3 5 7 9 JP 1 4 2 4 6 8 10 5 C8 2 0 .1 u F CC0 4 0 2 C7 7 0 .1 u F CC0 4 0 2 C5 8 0 .1 u F CC0 4 0 2 V C C _ 3 .3 V HE A DE R 5 X 2 h d r5 x2 _ 1 0 0 m il D o w n l o a d C a b le Header T DO i n p ut o u t put T DI o u t put T MS o u t put T CK V C C _ 3 .3 V V C C _ C O RE TCK TMS T DI TDO C5 0 0 .1 u F CC0 4 0 2 C9 7 0 .1 u F CC0 4 0 2 V C C _ 3 .3 V 1 2 TDO T DI 2x5 Download Cable Header H E A D E R 10 h d r1 0 x1 _ 1 0 0 m il JP 1 2 1x10 Download Cable Header 1 2 1 2 C6 7 0 .1 u F CC0 4 0 2 C6 5 0 .1 u F CC0 4 0 2 [ 4] [ 4] B U S Y D IN [ 4] D0 R1 0 1 10K CR0 4 0 2 C6 8 0 .1 u F CC0 4 0 2 4 C5 9 0 .1 u F CC0 4 0 2 JP 1 3 C5 7 0 .1 u F CC0 4 0 2 C6 6 0 .1 u F CC0 4 0 2 HE A DE R 5 X 2 d o _ n o t _ s t u ff 1 3 5 7 9 2 4 6 8 10 C6 0 0 .1 u F CC0 4 0 2 V C C _ 3 .3 V I N I TN P R O G RA MN 2x5 Loader Board Header CCL K B U SY D IN X P _ DO UT DO NE 4 1 5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 24 2 C8 8 10uF CC0 8 0 5 3 3 [ 8] V CC_ CO RE V C C _ 3 .3 V T DI TMS TCK TDO JP 6 1 3 5 7 HE A DE R 4 X 2 d o n o t s t u ff 2 4 6 8 H9 J1 5 J8 K15 K8 L15 L8 M1 5 M8 N1 5 N8 P15 P8 R9 G16 G7 T1 6 T7 M2 M2 1 E20 D2 0 D1 9 D1 8 F1 9 P C I _ TCK P CI_ TMS P C I _ TD I P C I _ TDO [ 2] [ 2] [ 2] [ 2] L FX P 1 0 C-4 F3 8 8 CE S FP B G A 3 8 8 V CC_ H9 V CC_ J1 5 V CC_ J8 V CC_ K 1 5 V CC_ K 8 V CC_ L 1 5 V CC_ L 8 V CC_ M1 5 V CC_ M8 V CC_ N1 5 V CC_ N8 V CC_ P 1 5 V CC_ P 8 V CC_ R9 V CCA UX _ G 1 6 V CCA UX _ G 7 V CCA UX _ T1 6 V CCA UX _ T7 R1 1 0 1 0 K CR0 4 0 2 CFG 0 2 G NDP 0 G NDP 1 G ND_ A 1 G ND_ A 2 2 G ND_ A B 1 G ND_ A B 2 2 G ND_ H1 0 G ND_ H1 1 G ND_ H1 2 G ND_ H1 3 G ND_ H1 4 G ND_ J1 0 G ND_ J1 1 G ND_ J1 2 G ND_ J1 3 G ND_ J1 4 G ND_ J9 G ND_ K 1 0 G ND_ K 1 1 G ND_ K 1 2 G ND_ K 1 3 G ND_ K 1 4 G ND_ K 9 G ND_ L 1 0 G ND_ L 1 1 G ND_ L 1 2 G ND_ L 1 3 G ND_ L 1 4 G ND_ L 9 G ND_ M1 0 G ND_ M1 1 G ND_ M1 2 G ND_ M1 3 G ND_ M1 4 G ND_ M9 G ND_ N1 0 G ND_ N1 1 G ND_ N1 2 G ND_ N1 3 G ND_ N1 4 G ND_ N9 G ND_ P 1 0 G ND_ P 1 1 G ND_ P 1 2 G ND_ P 1 3 G ND_ P 1 4 G ND_ P 9 G ND_ R1 0 G ND_ R1 1 G ND_ R1 2 G ND_ R1 3 G ND_ R1 4 DO NE P RO G RA MN INITN CCL K N1 N2 2 A1 A22 AB1 AB22 H1 0 H1 1 H1 2 H1 3 H1 4 J1 0 J1 1 J1 2 J1 3 J1 4 J9 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M1 0 M1 1 M1 2 M1 3 M1 4 M9 N1 0 N1 1 N1 2 N1 3 N1 4 N9 P10 P11 P12 P13 P14 P9 R1 0 R1 1 R1 2 R1 3 R1 4 B1 F4 Y2 G4 C1 B2 DO NE P R O G RA MN I N I TN CCL K R1 0 9 1 0 K CR0 4 0 2 CFG 1 CFG 0 CFG 1 LFXP10C (fpBGA388) (5 OF 5) V CCP 0 V CCP 1 V CCJ TDI TMS TCK TDO U4 E P C I _ TCK P CI_ TMS P C I _ TDI P C I _ TDO V C C _ 3 .3 V 2 1 2 3 4 S W D IP -2 261m ilX 4 2 5 m il SW 4 SW 3 S W P U S H B UTTO N 4 .7 m m X 3 .5 m m 1 2 DO NE R2 8 10K CR0 4 0 2 Q1 BSS138 S O T2 3 D1 4 G R E E N_ L E D CR0 6 0 3 R2 3 470 CR0 4 0 2 V C C _ 3 .3 V D escription S l a v e S e r i a l , External Device M a s t e r S e r i a l, External Device S l a v e P a r a l l e l, External Device I n t ernal Flash F r i d a y, A p r i l 2 9 , 2 0 0 5 D o c u m e n t N u m b er < D o c> 1 S h eet 5 J TAG and FPGA Programming of 9 Rev B L a t t i c e S e m i c o n d u c t o r C o r p o r a t i on D at e: Size C Ti tle D1 5 YE L L OW _LED CR0 6 0 3 R2 4 470 CR0 4 0 2 CFG0 0 1 0 1 D o w n = 0 , Up = 1 CFG1 0 0 1 1 1 A B C D Lattice Semiconductor LatticeXP Advanced Evaluation Board User’s Guide Figure 12. JTAG and FPGA Programming A B C D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 V C C I O_7 [ 8] S e ve n S e g m e n t L E D 738m ilX 3 8 6 m il cath od e A cath od e F an n od e1 NC1 NC2 NC3 cath od e E cath od e D cath od e DP cath od e C cath od e G NC4 cath od e B an n od e2 5 D1 G R E E N_ L E D CR0 6 0 3 R8 4 220 CR0 4 0 2 V C C I O_1 R5 470 CR0 4 0 2 D8 G R E E N_ L E D CR0 6 0 3 R9 3 220 CR0 4 0 2 R7 470 CR0 4 0 2 R8 470 CR0 4 0 2 R3 470 CR0 4 0 2 R1 470 CR0 4 0 2 TP _ D2 TP _ E 1 TP _ E 3 TP _ F2 TP _ D1 TP _ E 2 TP _ F1 TP _ F3 D2 G R E E N_ L E D CR0 6 0 3 R8 8 220 CR0 4 0 2 D3 G R E E N_ L E D CR0 6 0 3 R8 9 220 CR0 4 0 2 D4 G R E E N_ L E D CR0 6 0 3 R9 0 220 CR0 4 0 2 R3 0 R3 1 R3 2 R3 3 R3 4 R3 5 R3 6 R3 7 10K 10K 10K 10K 10K 10K 10K 10K CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 R6 470 CR0 4 0 2 SW 1 S W D IP -8 861m ilX 4 2 5 m il V C C _ 3 .3 V R4 470 CR0 4 0 2 V C C _ 3 .3 V R2 470 CR0 4 0 2 SSEG_B SSEG_E SSEG_D S S E G _ DP SSEG_C SSEG_G SSEG_A SSEG_F V C C _ 3 .3 V 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 U1 7 segment display 4 D5 G R E E N_ L E D CR0 6 0 3 R9 1 220 CR0 4 0 2 TP _ C2 2 TP _ Y2 1 TP_A A 2 2 TP_A A 2 1 TP_A B 2 1 TP _ C2 1 TP _ W 8 TP _ A B 2 [ 4] [ 2] [ 2] [ 2] [ 2] [ 4] [ 2] [ 2] [ 4] [ 4] TP _ A 2 [ 4] TP _ C5 TP _ B 1 2 D6 G R E E N_ L E D CR0 6 0 3 R9 2 220 CR0 4 0 2 1 2 3 4 5 6 [ 4] [ 4] [ 4] TP _ A 3 TP _ D3 TP _ B 1 3 TP _ H1 TP _ A 1 6 TP _ B 1 6 TP _ B 1 8 TP _ C1 8 TP _ C1 9 TP _ C2 0 TP _ W 1 6 D7 G R E E N_ L E D CR0 6 0 3 R3 8 220 CR0 4 0 2 V C C _ 3 .3 V J1 HE A DE R 6 h d r6 x1 _ 1 0 0 m il P op u late TP _ E 2 TP _ G 3 [ 4] [ 2] [ 4] [ 4] [ 4] [ 4] [ 4] J2 HE A DE R 6 h d r6 x1 _ 1 0 0 m il P o p u late 1 2 3 4 5 6 [ 4] [ 4] [ 4] 3 O S C_ CL K _ P L L SW 2 S W P U S H B UTTO N 4 .7 m m X 3 .5 m m 2 1 TP _ E 3 TP _ H4 [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] V C C I O_7 E TH _ MDIO E TH _ MDC E TH _ MA C_ CL K _ E N E TH_ CL K _ TO _ MA C E TH_ E G P 6 E TH_ E G P 7 E TH_ E G P 5 E TH_ E G P 4 E TH_ E G P 0 E TH_ E G P 2 [ 8] 1 2 3 4 5 6 A4 D8 B22 J4 K4 G1 H2 TP _ J4 TP _ K 4 TP _ G 1 TP _ H1 F1 E1 TP _ B 4 TP _ A 1 2 BANK 6 [ 4] [ 4] PL19A PL19B PL30A PL30B PL13A PL13B PL15B PL32B V CCIO 7 _ H7 V CCIO 7 _ J7 V CCIO 7 _ K 7 V CCIO 7 _ L 7 PL35A PL35B PL18A PL18B C4 8 0 .1 u F CC0 4 0 2 C4 6 10uF CC0 8 0 5 2 V CCIO 6 _ M7 V CCIO 6 _ N7 V CCIO 6 _ P 7 V CCIO 6 _ R7 D Q S r each P L L 2 _ FB _ T/P L 3 4 A P L L 2 _ FB _ C/P L 3 4 B DQ S /P L 3 3 A PL33B PL17A PL17B D Q S r each P L 1 6 A / DQ S PL16B V RE F2 _ 6 /P L 3 1 A PL29A PL29B P L 1 2 A /P L L 1 _ IN_ T P L 1 2 B /P L L 1 _ IN_ C P L 1 4 A /V RE F2 _ 7 PL28A PL28B PL11A PL11B D Q S r each PL26A PL26B D Q S r each P L L 2 _ IN_ T/P L 2 5 A P L L 2 _ IN_ C/P L 2 5 B PL9A PL9B DQ S /P L 2 4 A PL24B PL8A PL8B P L 7 A /DQ S PL7B V RE F1 _ 6 /P L 2 3 B PL22A PL5A P L 6 B /V RE F1 _ 7 PL21A PL21B PL4A PL4B M7 N7 P7 R7 U4 U3 V4 V3 T3 T4 R4 R3 Y1 W2 P3 P4 1 2 3 4 5 6 C5 1 0 .1 u F CC0 4 0 2 [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] [ 7] D at e: Size C Ti tle C5 2 0 .1 u F CC0 4 0 2 [ 8] E TH_ RX _ D2 E TH_ RX _ D3 E TH_ RX _ D6 E TH_ RX _ D7 E TH_ RX _ D0 E TH_ TX _ E R E TH_ TX _ D7 E TH_ TX _ E N [ 7] E TH_ RE S E T_ N[ 7] E TH _ CRS E TH_ TX _ D4 E TH_ TX _ D3 E TH_ COL E TH_ RX _ DV E TH_ RX _ E R E TH_ RX _ D4 E TH_ TX _ D6 E TH_ G TX _ CL K E TH_ TX _ D1 E TH_ TX _ D2 E TH_ RX _ D5 1 2 3 4 5 6 TP _ C4 TP _ A 1 8 1 S h eet D9 D I O D E S C H O TTK Y S Min i2 -F1 N o P o p u late 1 2 3 4 5 6 6 of P C I _ CL K J1 0 HE A DE R 6 h d r6 x1 _ 1 0 0 m il P o p u late TP _ E 1 TP _ G 2 D1 0 D I O D E S C H O TTK Y S Min i2 -F1 N o P o p u late F r i d a y, A p r i l 2 9 , 2 0 0 5 D o c u m e n t N u m b er < D o c> 1 TP _ H2 1 V C C _ 3 .3 V [ 3] [ 4] [ 4] Ethernet Phy C8 5 10uF CC0 8 0 5 J9 HE A DE R 6 h d r6 x1 _ 1 0 0 m il P op u late TP _ D2 TP _ G 1 TP _ T2 [ 7] E TH_ RX _ CL K [ 7] E TH_ RX _ D1 E TH_ TX _ D5 E TH_ TX _ D0 [ 4] [ 4] TP _ C3 TP _ A 1 3 V C C I O_6 P C I _ CL K TP _ T2 TP _ R2 J8 HE A DE R 6 h d r6 x1 _ 1 0 0 m il P op u late W1 V2 V1 U2 U1 T2 T1 R2 N4 N3 R1 P2 P1 N2 M3 M4 TP _ D1 TP _ F3 TP _ R2 Bank 2 H 21 Bank 6 R 2 , T2 Bank 7 D 1 , D 2 , E 1 , E 2 , E 3 , F1, F2, F3 G 1 , G 2 , G 3 , H 2 , H4, J4, K4 Bank 1 A 1 2 , A 1 3 , A 1 8 , B 12, B13, B22 D 12 Bank 0 A 2 , A 3 , A 4 , B 3 , B4, C3, C4 C 5 , D 3 , D8, D9 P CL K T6 _ 0 /P L 2 0 A P CL K C6 _ 0 /P L 2 0 B LFXP10C (fpBGA388) (1 OF 5) P L 3 A /P L L 1 _ FB _ T P L 3 B /P L L 1 _ FB _ C PL2A PL2B 1 2 3 4 5 6 J5 HE A DE R 6 h d r6 x1 _ 1 0 0 m il P o p u late L FX P 1 0 C-4 F3 8 8 CE S FP B G A 3 8 8 C4 9 0 .1 u F CC0 4 0 2 H7 J7 K7 L7 L1 M1 L3 L4 K1 L2 J3 K3 J1 K2 J2 H1 G3 G2 TP _ G 3 TP _ G 2 TP _ F1 TP _ E 1 H3 F3 F2 H4 TP _ H4 E2 E3 TP _ F3 TP _ F2 D2 D1 TP _ F2 TP _ K 4 BANK 7 U4 A TP _ B 3 TP _ D9 TP _ D1 2 TP _ E 2 TP _ E 3 [ 4] [ 4] [ 4] . ... . ... . ... TP _ D2 TP _ D1 J4 HE A DE R 6 h d r6 x1 _ 1 0 0 m il P o p u late E TH_ TX _ CL K G S RN O S C_ CL K _ P L L [ 7] TP _ F1 TP _ J4 I .e.: A2 A3 C5 D3 B12 B13 D1 3 R E D _ LED CR0 6 0 3 R2 1 470 CR0 4 0 2 V C C _ 3 .3 V TP _ A 4 TP _ D8 TP _ B 2 2 Bank 0 2 T h e 1 x 6 h e a d e r s f o r m a t e s t p o i n t g r i d 100mil c e n t e r - c e n t e r i n t h e o r i e n t a t i o n s h o w n b elow. T h e s i l k s c r e e n w i l l c o n t a i n a n i n d e p e ndent s e c t i o n t h a t d e s c r i b e s t h e p i n s e q u e n c e. The p i n s e q u e n c e a r e a w i l l b e " b o x e d " a n d have t e x t i n d i c a t i n g w h i c h b a n k t h e I O ' s b e l ong to. 1 2 3 1 2 4 1 2 5 1 25 2 9 [ 2] Rev B A B C D Lattice Semiconductor LatticeXP Advanced Evaluation Board User’s Guide Figure 13. Ethernet PHY A B C V C C _ 2 .5 V [ 6] E TH_ MDIO [ 6] E TH _ MDC T h e s e t r a c e s m u s t be 50 ohm i m p e d e nce. P l a c e t e r m i n a t i o n resistors T X _ D 0 - 7 , T X _ E R, TX_EN, T X _ C L K , G TX_CLK a s c l o s e t o U 5 a s possible. N O T E: P l a c e t e r m i n a t i o n resistors R X _ D 0 - 7 , R X _ E R, RX_DV, R X _ C L K , T X _ C L K , CRS, COL a s c l o s e t o U 3 a s possible. R5 5 2K CR0 6 0 3 5 [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] [ 6] E TH_ G TX _ CL K E TH _ C RS E TH_ CO L E TH_ TX _ CL K E TH_ TX _ E N E TH_ TX _ E R E TH_ TX _ D0 E TH_ TX _ D1 E TH_ TX _ D2 E TH_ TX _ D3 E TH_ TX _ D4 E TH_ TX _ D5 E TH_ TX _ D6 E TH_ TX _ D7 E TH_ RX _ CL K E TH_ RX _ DV E TH_ RX _ E R E TH_ RX _ D0 E TH_ RX _ D1 E TH_ RX _ D2 E TH_ RX _ D3 E TH_ RX _ D4 E TH_ RX _ D5 E TH_ RX _ D6 E TH_ RX _ D7 33 2 5 MHz H C -4 9 / U Y1 R7 8 33 33 33 R7 1 R5 9 R6 0 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 R7 6 R8 3 R7 2 R7 9 R7 3 R8 0 R7 4 R8 1 R7 5 R8 2 R6 1 R5 8 R6 7 R6 8 R6 2 R6 3 R6 9 R6 4 R6 5 R6 6 R5 7 1 33pF CC0 6 0 3 C2 4 X1 X0 R1 3 2K CR0 6 0 3 23 27 28 31 32 24 87 86 80 81 79 40 39 60 62 61 76 75 72 71 68 67 66 65 57 44 41 56 55 52 51 50 47 46 45 4 DP 8 3 8 6 5 TM0 TMS TDO TDI TRS T TCK CL O CK _ O UT CL O CK _ IN MDIO MDC G TX _ CL K / RG MII_ TX C CRS / RG MII_ S E L 1 CO L TX _ CL K / RG MII_ S E L 0 TX _ E N / RG MII_ TX _ CTL TX _ E R TX D0 / RG MII_ TX D0 TX D1 / RG MII_ TX D1 TX D2 / RG MII_ TX D2 TX D3 / RG MII_ TX D3 TX D4 TX D5 TX D6 TX D7 RX _ CL K RX _ DV / RG MII_ RX C RX _ E R / RG MII_ RX _ CTL RX D0 RX D1 RX D2 RX D3 RX D4 RX D5 RX D6 RX D7 / RG MII_ RX D0 / RG MII_ RX D1 / RG MII_ RX D2 / RG MII_ RX D3 22uF 1 S izeB C1 2 U2 0 .0 1 u F 1 CC0 6 0 3 C2 2 P l a c e c a p s c l o se to GPHY P U L L _ DN R5 4 33 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 CR0 4 0 2 P l a c e x t a l c l o se to GPHY P l a c e R c l o s e t o CLOCK_IN 33pF CC0 6 0 3 C2 1 TX_D0 TX_D1 TX_D2 TX_D3 TX_D4 TX_D5 TX_D6 TX_D7 RX _ D0 RX _ D1 RX _ D2 RX _ D3 RX _ D4 RX _ D5 RX _ D6 RX _ D7 1 R9 18 CR0 6 0 3 101 BG_VDD 98 PGM_VDD0 3 G i g a P hyter 10/100/1000 Giga Phyter V R X _ VDD C3 4 0 .1 u F CC0 4 0 2 C3 2 C3 1 0 .1 u F CC0 4 0 2 C3 3 0 .0 1 u F CC0 6 0 3 C3 8 0 .1 u F CC0 4 0 2 B y p a s s f o r I O _ V D D p i n s . Bypass every other I O _ V D D p a i r , a l t e r n a t i n g 0 . 1 and 0.01uF caps. 0 .0 1 u F CC0 6 0 3 C2 5 0 .0 1 u F CC0 6 0 3 3 E TH_ E G P 4 E TH_ E G P 5 E TH_ E G P 6 E TH_ E G P 7 E TH_ E G P 2 E TH_ E G P 0 R1 0 2K CR0 6 0 3 R5 6 2K CR0 6 0 3 H a r d R eset [ 8] C9 0 B y p a s s f o r BG_VDD 0 .0 1 u F CC0 6 0 3 [ 6] [ 6] [ 6] 0 .0 1 u F CC0 6 0 3 C3 0 R5 3 2K CR0 6 0 3 V C C _ 2 .5 V C3 5 0 .1 u F CC0 4 0 2 C3 6 0 .0 1 u F CC0 6 0 3 2 0 .1 u F CC0 4 0 2 C3 7 C2 9 0 .0 1 u F CC0 4 0 2 R5 1 R4 9 R5 0 R5 2 49_9 49_9 49_9 49_9 CR0 6 0 3 CR0 6 0 3 CR0 6 0 3 CR0 6 0 3 R4 5 R4 7 R4 8 R4 6 49_9 49_9 49_9 49_9 CR0 6 0 3 CR0 6 0 3 CR0 6 0 3 CR0 6 0 3 B y p a s s f o r V D D _ C O R E a n d V D D pins. Bypass every o t h e r V D D p a i r , a l t e r n a t i n g 0.1 and 0.01uF caps. 0 .1 u F CC0 4 0 2 C2 7 E TH_ CL K _ TO _ MA C E TH_ RE S E T_ N C2 8 0 .0 1 u F CC0 4 0 2 V C C _ 2 .5 V E TH _ MA C_ CL K _ E N G i g a P h y t e r a d d ress = 01h R1 2 4 7 0 1 2 CR0 4 0 2 R1 1 4 7 0 1 2 P UL L _ UP CR0 4 0 2 B G R EF R4 4 9 _ 7 6 K 1 2 CR0 6 0 3 P l a c e c a p s c l o se to GPHY V C C _ 2 .5 V 0 .1 u F CC0 4 0 2 C2 3 85 33 13 14 17 18 95 94 89 88 1 2 3 6 7 8 9 10 34 84 102 MDI_ P 4 M D I _ N4 MDI_ P 3 M D I _ N3 120 121 126 127 MDI_ P 2 M D I _ N2 MDI_ P 1 M D I _ N1 MDI IO traces must be 50 ohm impedence. 114 115 108 109 Decoupling Caps CL K _ TO _ MA C RE S E T_ N G P 0 (P HYA D0 / DUP L E X _ L E D) G P 1 (P HYA D1 ) G P 2 (P HYA D2 ) G P 3 (P HYA D3 ) G P 4 (P HYA D4 ) G P 5 (MUL TI_ E N) G P 6 (MDIX _ E N) G P 7 (MA C_ CL K _ E N) E G P 0 (NC_ MO DE ) EGP1 E G P 2 (In terru p t) E G P 3 (TX _ TCL K ) E G P 4 (S P E E D0 / A CT_ L E D) E G P 5 (S P E E D1 / L INK 1 0 ) E G P 6 (DUP L E X _ E N / L INK 1 0 0 ) E G P 7 (A N_ E N / L INK 1 0 0 0 ) V DD_ S E L RE F_ S E L B G _ RE F MDID_ P MDID_ N MDIC_ P MDIC_ N MDIB _ P MDIB _ N MDIA _ P MDIA _ N V C C _ 2 .5 V V C C _ 2 .5 V Place 49 ohm termination resistors as close as possible to U3. The associated 0.01uF capacitor should be placed close to the 49 ohm resistors. 2 C2 2 Ti tle MDID+ MDDCT MDID- MDIC+ MDCCT MDIC- MDIB + MDB CT MDIB - [ 8] 19 20 16 15 14 13 1 1 R4 0 2K CR0 6 0 3 R4 2 324 CR0 4 0 2 R4 3 2K CR0 6 0 3 R4 1 324 CR0 4 0 2 1 2 2 2 2 S h eet 7 MH2 MH1 MHO L E _ 1 MHO L E _ 1 0 .1 0 0 _ P TH 0 .1 0 0 _ P TH E TH_ E G P 4 1 C1 9 0 .0 1 u F CC0 4 0 2 0 . 1 0 0 " d iameter plated t h rough hole E TH_ E G P 7 1 F r i d a y, A p r i l 2 9 , 2 0 0 5 D o c u m e n t N u m b er < D o c> C1 8 0 .0 1 u F CC0 4 0 2 Ethernet PHY Chip C3 10uF S izeC L E D2 + L E D2 L E D1 + L E D1 - S HL D1 S HL D2 7 8 4 5 3 6 1 2 RJ45 V C C _ 1 .8 V D at e: Size C TX1 MDIA + MDA CT MDIA - RJ4 5 0 .0 1 u F CC0 6 0 3 8 7 9 3 1 2 4 6 5 11 12 10 C2 6 0 .0 1 u F CC0 4 0 2 P l a c e c a p s c lose to R J 4 5 j a ck TX1 1 1 2 V C C _ 1 .8 V 1 2 1 2 1 2 RJ45 11 19 25 35 48 63 73 92 CORE_VDD1 CORE_VDD2 CORE_VDD3 CORE_VDD4 CORE_VDD5 CORE_VDD6 CORE_VDD7 CORE_VDD8 1 2 1 2 1 2 100 103 105 111 117 123 VDD0 RX_DVDD0 VDD1 VDD2 VDD3 VDD4 VSS0 PGM_VSS0 IO_VSS1 CORE_VSS1 CORE_VSS2 IO_VSS2 CORE_VSS3 IO_VSS3 CORE_VSS4 IO_VSS4 IO_VSS5 CORE_VSS5 IO_VSS6 IO_VSS7 CORE_VSS6 IO_VSS8 CORE_VSS7 IO_VSS9 O_VSS0 IO_VSS10 CORE_VSS8 IO_VSS11 RX_DVSS0 VSS1 CD_VSS1 CD_VSS2 VSS2 CD2_VSS1 CD2_VSS2 VSS3 CD3_VSS1 CD3_VSS2 VSS4 CD4_VSS1 CD4_VSS2 1 2 4 15 21 29 37 42 53 58 69 83 77 90 2 1 2 96 VDD25_0 99 97 5 12 20 16 26 22 36 30 38 49 43 54 64 59 74 70 82 78 93 91 104 106 107 110 112 113 116 118 119 122 124 125 128 1 2 IO_VDD1 IO_VDD2 IO_VDD3 IO_VDD4 IO_VDD5 IO_VDD6 IO_VDD7 IO_VDD8 IO_VDD9 O_VDD0 IO_VDD10 IO_VDD11 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 4 1 D 5 1 26 2 of 9 Rev B C1 7 0 .0 1 u F CC0 4 0 2 A B C D Lattice Semiconductor LatticeXP Advanced Evaluation Board User’s Guide Figure 14. Ethernet PHY Chip A B C J1 9 P W R J A CK RAPC712 1 2 3 J1 8 C O NN_ RE D J1 7 C O N N _ B L A CK 5 5 D1 8 1 N5 8 2 0 2 6 7 -0 5 D1 1 [ 6] 1 2 3 V C C _ 3 .3 V 1 2 3 JB 1 9 JB L O CK h d r3 x1 _ 1 0 0 m il V C C I O_1 V C C IO _ 7 [ 3] R2 6 10K CR0 4 0 2 1 2 3 1 2 3 SW V IN IS E NS E SW V IN IS E NS E S O T2 3 -6 TP S 6 4 2 0 3 DV B /E N G ND FB U9 S O T2 3 -6 TP S 6 4 2 0 3 DV B /E N G ND FB U8 JP 1 HE A DE R 8 h d r8 x1 _ 1 0 0 m il Q5 S i2 3 2 3 DS S O T2 3 2 6 .2 u H 7m m X7m m V C C I O_0 V C C I O_6 V C C _ 3 .3 V V CC_ A DJ V C C _ 2 .5 V V C C _ 1 .2 V V C C I O_6 D R A I N _ 1 .2 R1 0 8 10 CR0 4 0 2 G A TE _ 1 .2 b i g g e r trace 2 6 .2 u H 7m m X7m m JP 2 HE A DE R 8 h d r8 x1 _ 1 0 0 m il D1 7 B320A S MA 1 L2 Q3 S i5 4 4 7 DC 1 2 0 6 -8 V C C _ 3 .3 V V CC_ A DJ V C C _ 2 .5 V V C C _ 1 .2 V V C C I O_0 4 S e l e c t o n l y o n e v o l t a g e f o r e a c h VCCIO [ 3] G 1 D1 6 B320A S MA L1 [ 6] R2 5 3 6 _ 0 K /1 % CR0 4 0 2 V C C _ 2 .5 V 3 V C C _ C O RE C1 2 100uF S izeD 3 P W R_ 1 .2 V 2 4 6 8 2 4 6 8 HE A DE R 4 X 2 hdr4X2 _ 1 0 0 m il HE A DE R 4 X 2 hdr4X2 _ 1 0 0 m il 1 3 5 7 JP 7 1 3 5 7 2 4 6 8 1 3 5 7 JP 1 1 2 4 6 8 JP 9 HE A DE R 4 X 2 hdr4X2 _ 1 0 0 m il V CC_ A DJ V C C _ 1 .2 V 2 P C I _ G ND_ 5 7 JB 2 0 JB L O CK [ 7] V C C _ 1 .8 V R1 0 2 10K CR0 4 0 2 R1 0 5 10K CR0 4 0 2 1 2 2 1 FB V O UT EN V IN 2 4 6 8 2 5 4 5 4 1 3 5 7 V C C _ 3 .3 V JB 2 + JB 3 C1 3 2 .2 u F CC1 2 1 0 F3 1 .5 A JB 6 JB 7 JB 4 JB 8 JB 1 0 JB 1 1 JB 1 2 JB 1 4 JB 1 5 JB 1 6 J B L O CK J B L O CK JB L O CK JB L O CK JB 1 3 J B L O CK J B L O CK JB L O CK JB L O CK JB 9 J B L O CK J B L O CK JB L O CK JB L O CK JB 5 J B L O CK J B L O CK JB L O CK JB L O CK JB 1 V C C _ 3 .3 V C1 0 2 .2 u F CC1 2 1 0 J1 5 C O NN_ RE D + F4 1 .5 A J1 6 C O NN_ RE D F r i d a y, A p r i l 2 9 , 2 0 0 5 D o c u m e n t N u m b er < D o c> Power 1 S h eet 8 of 9 Rev B L a t t i c e Semiconductor Corporation D at e: Size C Ti tle V CC_ A DJ R1 0 3 3 0 _ 1 K /1 % CR0 4 0 2 R1 0 4 5 1 _ 0 K /1 % CR0 4 0 2 P W R_ 3 .3 V [ 5 ],[ 6] R1 0 6 3 0 _ 1 K /1 % CR0 4 0 2 R2 9 50K POT 5 .6 m m X 3 .6 m m P W R _ A DJ 2 HE A DE R 4 X 2 hdr4X 2 _ 1 0 0 m il JP 1 0 FB V O UT U6 TPS78 6 0 1 K TT D D P AK EN V IN U7 TPS78 6 0 1 K TT D D P AK 1 V CC_ A DJ S e t t o 1 . 8 V i f U 3 i s i n s t a l led. S e l e c t o n l y o n e v o l t a g e f o r t h e core V C C _ 2 .5 V 3 2 1 JP 1 6 HE A DE R 3 h d r3 x1 _ 1 0 0 m il C8 4 .7 u F CC1 2 1 0 JB 1 7 JB L O CK 3 2 1 JP 1 5 HE A DE R 3 h d r3 x1 _ 1 0 0 m il C9 4 .7 u F CC1 2 1 0 V C C _ 3 .3 V [ 2] V CC_ IN V CC_ IN HE A DE R 4 X 2 hdr4X2 _ 1 0 0 m il 1 3 5 7 C7 1uF S izeA F2 3A J1 4 C O NN_ RE D C6 1uF S izeA F1 3A J1 3 C O NN_ RE D JP 8 V C C _ 1 .2 V C1 1 100uF S izeD P W R_ 2 .5 V V C C _ 2 .5 V C1 4 R2 2 4 .7 p F 3 9 _ 0 K /1 % CC0 4 0 2 CR0 4 0 2 [ 5] V C C _ C O RE A n o t h e r P - C h a n n e l M O S F E T o p t ion in SOT23 package D R A I N _ 1 .2 G A TE _ 1 .2 V CC_ IN D R A I N _ 2 .5 b i g g e r tra ce R1 0 7 1 0 CR0 4 0 2 G A TE _ 2 .5 Q2 S i5 4 4 7 DC 1 2 0 6 -8 JP 4 HE A DE R 8 h d r8x1 _ 1 0 0 m il [ 6] 6 5 4 6 5 4 C1 5 10uF S izeC Q4 S i2 3 2 3 DS S O T2 3 JP 3 HE A DE R 8 h d r8 x1 _ 1 0 0 m il V C C _ 3 .3 V V CC_ A DJ V C C _ 2 .5 V V C C _ 1 .2 V V C C I O_1 V C C _ 3 .3 V V CC_ A DJ V C C _ 2 .5 V V C C _ 1 .2 V V C C I O_7 R2 7 10K CR0 4 0 2 PCI_3.3V JP 1 8 HE A DE R 3 JB 1 8 J B L O CK h d r3 x1 _ 1 0 0 m il JP 1 7 HE A DE R 3 C1 6 10uF S izeC 1 N5 8 2 0 2 6 7 -0 5 D1 2 1 N5 8 2 0 2 6 7 -0 5 V CC_ IN V CC_ IN G S A n o t h e r P - C h a n n e l M O S F E T o p t ion in SOT23 package D R A I N _ 2 .5 G A TE _ 2 .5 V CC_ IN 4 S D 5 6 7 8 S D D D 1 2 S 1 2 1 D S 1 1 S 1 2 1 2 1 2 3 4 5 6 7 8 GND 3 G D D D 1 2 3 4 5 6 7 8 3 1 1 2 1 1 2 4 3 2 1 S D 5 6 7 8 S D D D G D D D 4 3 2 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 1 2 1 2 1 2 S 1 2 1 1 2 GND S 1 2 1 27 3 A B C D Lattice Semiconductor LatticeXP Advanced Evaluation Board User’s Guide Figure 15. Power