MACH Endurance Characteristics & Input/Output Structure February 2002 The MACH® families are manufactured using Lattice’s advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Parameter Symbol tDR N Parameter Description Min Pattern Data Retention Time Max Reprogramming Cycles Value Unit Test Conditions 20 Years Max Operating Temperature 10 Years Max Storage Temperature 100 Cycles Normal Programming Conditions Input/Output Equivalent Schematics VCC 100 kΩ 1 kΩ VCC To Array Logic Input VCC VCC 100 kΩ 1 kΩ Preload Circuitry Feedback Input I/O Figure 1. Bus-Friendly™ Latch I www.latticesemi.com 1 dbend_2 Lattice Semiconductor MACH Endurance Characteristics & Input/Output Structure VCC VCC > 50 kΩ ESD Protection and Clamping Programming Voltage Detection Programming Pins only Positive Overshoot Filter Input VCC VCC > 50 kΩ Provides ESD Protection and Clamping I/O Figure 2. Pull-up Resistor 2 Preload Circuitry Feedback Input Programming Circuitry