IDT74LVCR162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O IDT74LVCR162245A DESCRIPTION: FEATURES: This 16-bit bus transceiver is built using advanced dual metal CMOS technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate this device as either two independent 8-bit transceivers or one 16-bit transceiver. The direction control pin (DIR) controls the direction of data flow. The output enable pin (OE) overrides the direction control and disables both ports. All inputs are designed with hysteresis for improved noise margin. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCR162245A has series resistors in the device output structure which will significantly reduce line noise when used with light loads. The driver has been designed to drive ±12mA at the designated threshold levels. • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP, TSSOP, and TVSOP packages DRIVE FEATURES: • Balanced Output Drivers: ±12mA • Low switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1DIR 24 1 2DIR 25 48 1OE 1A1 2OE 47 2A1 2 36 13 1B1 1A2 2A2 3 14 1B2 1A3 2A3 16 1B3 2B3 32 43 2A4 6 17 1B4 1A5 2B4 41 2A5 30 8 19 1B5 1A6 40 2A6 20 1B6 38 2A7 22 1B7 2B7 37 2A8 12 2B6 27 11 1A8 2B5 29 9 1A7 2B2 33 44 5 1A4 2B1 35 46 26 23 1B8 2B8 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE APRIL 1999 1 © 1999 Integrated Device Technology, Inc. DSC-4691/2 IDT74LVCR162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION 1DIR 1 48 1B1 2 47 1B2 3 46 GND 4 1B3 5 1B4 6 1OE 1A1 Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +6.5 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to +6.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA 1A2 Continuous Clamp Current, VI < 0 or VO < 0 –50 mA 45 IIK IOK GND Continuous Current through each VCC or GND mA 1A3 ICC ISS ±100 44 43 1A4 VCC 7 42 VCC 1B5 8 41 1A5 1B6 9 40 1A6 GND 10 39 GND 1B7 11 38 1A7 1B8 12 37 1A8 2B1 13 36 2A1 2B2 14 35 2A2 GND 15 34 GND 2B3 16 33 2A3 2B4 17 32 2A4 VCC 18 31 VCC 2B5 19 30 2A5 2B6 20 29 2A6 GND 21 28 GND 2B7 22 27 2A7 2B8 23 26 2A8 2DIR 24 25 2OE NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description xOE Output Enable Input (Active LOW) xDIR Direction Control Input xAx Side A Inputs or 3-State Outputs xBx Side B Inputs or 3-State Outputs FUNCTION TABLE (EACH 8-BIT SECTION)(1) Inputs SSOP/ TSSOP/ TVSOP TOP VIEW xOE xDIR L L Bus B Data to Bus A L H Bus A Data to Bus B H X Isolation NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level 2 Outputs IDT74LVCR162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV µA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 µA IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Unit V IOH = – 0.1mA VCC – 0.2 — VCC = 2.3V IOH = – 4mA 1.9 — IOH = – 6mA 1.7 — VCC = 3V Output LOW Voltage Max. VCC = 2.3V to 3.6V VCC = 2.7V VOL Min. VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = – 4mA 2.2 — IOH = – 8mA 2 — IOH = – 6mA 2.4 — IOH = – 12mA 2 — IOL = 0.1mA — 0.2 IOL = 4mA — 0.4 IOL = 6mA — 0.55 IOL = 4mA — 0.4 IOL = 8mA — 0.6 IOL = 6mA — 0.55 IOL = 12mA — 0.8 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74LVCR162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Transceiver Outputs enabled CPD Power Dissipation Capacitance per Transceiver Outputs disabled Test Conditions Typical Unit CL = 0pF, f = 10Mhz 39 pF 4 SWITCHING CHARACTERISTICS(1) Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xAx to xBx, xBx to xAx Output Enable Time xOE to xAx or xBx Output Disable Time xOE to xAx or xBx Output Skew(2) Min. — NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 VCC = 2.7V Max. 5.7 VCC = 3.3V ± 0.3V Min. Max. 1.5 4.8 Unit ns — 7.9 1.5 6.3 ns — 8.3 2.2 7.4 ns — — — 500 ps IDT74LVCR162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF Pulse (1, 2) Generator VIN DISABLE tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω CL DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Switch VLOAD TIMING INPUT Disable High Enable High GND ASYNCHRONOUS CONTROL All Other Tests Open SYNCHRONOUS CONTROL tSK (x) tPLH2 VOH VT VOL tH tREM tSU tH LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE VT LVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V Set-up, Hold, and Release Times VOH VT VOL OUTPUT 2 VOH VOH-VHZ 0V VT 0V LVC Link VIH VT 0V tSK (x) tPHZ Enable and Disable Times DATA INPUT tPHL1 VLOAD/2 VOL+VLZ VOL NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Open Drain Disable Low Enable Low tPLZ VLOAD/2 VT LVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test VIH VT 0V CONTROL INPUT Test Circuit for All Outputs OUTPUT 1 VIH VT 0V ENABLE GND VOUT tPLH1 tPHL Propagation Delay LVC Link INPUT tPLH LVC Link D.U.T. RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVCR162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION X LVC IDT XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA PF Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 245A 16-Bit Bus Transceiver R162 Double-Density with Resistors, ±12mA Blank No Bus-hold 74 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459