® ® ispGDXV, ispGDX and ispGDS Architectural Description ® January 2002 The ispGDX Family Introduction The ispGDX Family is available in core voltages of 5V and 3.3V. The 3.3V ispGDXV Family is a functional superset of the 5V ispGDX, adding new features, greater I/O options, a core voltage of 3.3V and individual programmable 3.3V or 2.5V output levels. Architecture The architecture of the ispGDX device families consists of a series of programmable I/O cells interconnected by a Global Routing Pool (GRP). The GRP is a proprietary interconnect structure from Lattice Semiconductor, pioneered in the ispLSI® Family, that allows any input to be connected to any one or more outputs on the device. Unlike ispLSI devices, there are no programmable logic arrays on ispGDX devices. Control signals for Output Enables (OE), Clocks and MUX Controls must come from designated sets of I/O pins. Control Data VCC I/O A 0 I/O A 1 I/O A 2 I/O A 3 GND I/O A 4 I/O A 5 I/O A 6 I/O A 7 I/O A 8 I/O A 9 I/O A 10 I/O A 11 GND I/O A 12 VCC I/O A 13 I/O A 14 I/O A 15 I/O A 16 I/O A 17 I/O A 18 I/O A 19 GND I/O A 20 I/O A 21 I/O A 22 I/O A 23 I/O A 24 I/O A 25 I/O A 26 VCC I/O A 27 GND I/O A 28 I/O A 29 I/O A 30 I/O A 31 I/O A 32 I/O A 33 I/O A 34 I/O A 35 GND I/O A 36 I/O A 37 I/O A 38 I/O A 39 VCC I/O B 0 I/O B 1 I/O B 2 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 Data — CLK/CLKEN OE MUXsel1 MUXsel2 — CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 — CLK/CLKEN — OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 — CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 — MUXsel2 — CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 — CLK/CLKEN OE MUXsel1 MUXsel2 — CLK/CLKEN OE MUXsel1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 ispGDX160V/VA Top View 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 Data Control VCCIO/VCC2 I/O D1 I/O D 0 VCC I/O C 39 I/O C 38 I/O C 37 I/O C 36 GND I/O C 35 I/O C 34 I/O C 33 I/O C 32 I/O C 31 I/O C 30 I/O C 29 I/O C 28 GND I/O C 27 VCC I/O C 26 I/O C 25 I/O C 24 I/O C 23 I/O C 22 I/O C 21 I/O C 20 GND I/O C 19 I/O C 18 I/O C 17 I/O C 16 I/O C 15 I/O C 14 I/O C 13 VCC I/O C 12 GND I/O C 11 I/O C 10 I/O C 9 I/O C 8 I/O C 7 I/O C 6 I/O C 5 I/O C 4 GND I/O C 3 I/O C 2 I/O C 1 I/O C 0 VCC — OE CLK/CLKEN — MUXsel2 MUXsel1 OE CLK/CLKEN — MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN — MUXsel2 — MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN — MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE — CLK/CLKEN — MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN — MUXsel2 MUXsel1 OE CLK/CLKEN — Data Control www.latticesemi.com I/O B 3 MUXsel2 GND — I/O B 4 CLK/CLKEN I/O B 5 OE I/O B 6 MUXsel1 I/O B 7 MUXsel2 I/O B 8 CLK/CLKEN I/O B 9 OE I/O B 10 MUXsel1 I/O B 11 MUXsel2 GND — I/O B 12 CLK/CLKEN VCC — I/O B 13 OE I/O B 14 MUXsel1 I/O B 15 MUXsel2 I/O B 16 CLK/CLKEN I/O B 17 OE I/O B 18 MUXsel1 I/O B 19 MUXsel2 1NC — 1NC — CLK_EN0/Y0 — CLK_EN1/Y1 — GND — TDO — TMS — TCK — TDI — I/O B 20 CLK/CLKEN I/O B 21 OE I/O B 22 MUXsel1 I/O B 23 MUXsel2 I/O B 24 CLK/CLKEN I/O B 25 OE I/O B 26 MUXsel1 VCC — I/O B 27 MUXsel2 GND — I/O B 28 CLK/CLKEN I/O B 29 OE I/O B 30 MUXsel1 I/O B 31 MUXsel2 I/O B 32 CLK/CLKEN I/O B 33 OE I/O B 34 MUXsel1 I/O B 35 MUXsel2 GND — I/O B 36 CLK/CLKEN I/O B 37 OE I/O B 38 MUXsel1 I/O B 39 MUXsel2 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Control I/O D 39 MUXsel2 I/O D 38 MUXsel1 I/O D 37 OE I/O D 36 CLK/CLKEN GND — I/O D 35 MUXsel2 I/O D 34 MUXsel1 I/O D 33 OE I/O D 32 CLK/CLKEN I/O D 31 MUXsel2 I/O D 30 MUXsel1 I/O D 29 OE I/O D 28 CLK/CLKEN GND — I/O D 27 MUXsel2 VCC — I/O D 26 MUXsel1 I/O D 25 OE I/O D 24 CLK/CLKEN I/O D 23 MUXsel2 I/O D 22 MUXsel1 I/O D 21 OE I/O D 20 CLK/CLKEN RESET — VCC — EPEN — GND — Y3/CLK_EN3 — Y2/CLK_EN2 — NC1 — TOE — I/O D 19 MUXsel2 I/O D 18 MUXsel1 I/O D 17 OE I/O D 16 CLK/CLKEN I/O D 15 MUXsel2 I/O D 14 MUXsel1 I/O D 13 OE VCC — I/O D 12 CLK/CLKEN GND — I/O D 11 MUXsel2 I/O D 10 MUXsel1 I/O D 9 OE I/O D 8 CLK/CLKEN I/O D 7 MUXsel2 I/O D 6 MUXsel1 I/O D 5 OE I/O D 4 CLK/CLKEN GND — I/O D 3 MUXsel2 I/O D 2 MUXsel1 Figure 1. ispGDX160V/VA Pinout 1 gdxarch_08 ispGDXV, ispGDX and ispGDS Architectural Description Lattice Semiconductor Each I/O cell drives a unique pin. The I/O cells include a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. Each I/O cell has individual, programmable tri-state control (OE), register or latch clock (CLK) and programmable polarity. The OE control for each I/O pin is independent and may be driven via the GRP by one of the designated I/O-OE pins. Using the individual tri-state control, it is possible to emulate open-drain output functionality for wired-OR bus applications. Each I/O cell also contains a 4:1 dynamic MUX controlled by two select lines called MUX0 and MUX1. As shown in Figure 2, when both register/latch control muxes select the “A” path, the register/latch gets its inputs from the 4:1 mux and drives the I/O output. When selecting the “B” path the register/latch is directly driven by the I/O input while its output feeds the GRP. The programmable polarity clock to the latch or register can be connected to any I/O in the I/O clock set (one-quarter of total I/Os) or to one of the dedicated clock input pins (Yx). Use of the dedicated clock inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Combinatorial output mode may be implemented by a dedicated architecture bit and bypass MUX. I/O cell polarity can be programmed as active high or active low. Finally, outputs may be set to fixed HIGH or LOW logic levels to simulate Jumper or DIP Switch functions. Figure 2. ispGDX/V I/O Cell and GRP Detail (160-I/O Device) Logic “0” Logic “1” 160 I/O Inputs I/OCell 0 I/O Cell 159 I/O Cell 1 I/O Cell 158 E2CMOS Programmable Interconnect To 2 Adjacent I/O Cells above From MUX Outputs of 2 Adjacent I/O Cells I/O Group A I/O Group B I/O Group C I/O Group D N+1 N-1 Register or Latch M0 M1 M2 M3 MUX0 MUX1 4x4 Crossbar Switch N-2 From MUX Outputs of 2 Adjacent I/O Cells Prog. Prog. Pull-up Bus Hold Latch (VCCIO) Bypass Option 4-to-1 MUX N+2 A B D Q CLK To 2 Adjacent I/O Cells below CLK_EN Reset I/O Pin C R Prog. Open Drain 2.5V/3.3V Output Prog. Slew Rate Boundary Scan Cell I/O Cell N I/O Cell 78 I/O Cell 81 I/O Cell 79 80 I/O Cells I/O Cell 80 80 I/O Cells 160 Input GRP Inputs Vertical Outputs Horizontal Global Y0-Y3 Reset Global Clocks / Clock_Enables ispGDXV/VA architecture enhancements over ispGDX (5V) Device output buffers have 24mA IOL drive as well as independently programmable output slew rate to reduce overall ground bounce and switching noise. IEEE1149.1-compliant Boundary Scan test is supported by dedicated registers at each I/O pin (Figure 3). ispGDX in-system programming is supported through the Test Access Port (TAP) via a special set of private commands (Boundary Scan protocol) or through the Lattice ISP protocol. The programming protocol is selected by the BSCAN/ispEN pin. ispGDXVA programming is supported through the TAP controller port. The EPEN signal, when high, enables the TAP controller port for programming and test for ispGDXVA devices. The ispGDXV Family offers a programmable MUX width for MUX chaining and allows up to 16:1 multiplexing. Other features include a bus hold latch and clock enable. 2 ispGDXV, ispGDX and ispGDS Architectural Description Lattice Semiconductor Figure 3. ispGDX Boundary Scan I/O Register Cell SCANIN (from previous cell) Normal Function OE M U X D Q M U X Q D TOE EXTEST Normal Function OE M U X D Q M U X Q D I/O Pin Update DR M U X Shift DR D Q SCANOUT (to next cell) Clock DR The ispGDS Family The ispGDS architecture features a programmable switch matrix surrounded by two banks of programmable I/O macrocells. The I/O cells in each device are divided equally into two banks (Bank A and Bank B). Each I/O macrocell can be configured as an input, an inverting or non-inverting output or a fixed TTL HIGH or LOW output. The switch matrix connects the I/O banks, allowing an I/O cell in one bank to be connected to any of the I/O cells in the other bank. A single I/O cell configured as an input can drive one or more I/O cells in the other bank. inputs to the MUX (called MUXA, MUXB, MUXC, and MUXD) come from I/O signals found in the GRP. Each MUX data input can be accessed by one quarter of the total I/Os. MUX0 and MUX1 can be driven by designated I/O pins called the MUXsel pins. MUXsel inputs can be chosen from designated pins (Figure 4). I/O Cell I/O Cell I/O Cell B1 B0 I/O Cell B2 I/O Cell B3 I/O Cell I/O Cell I/O Cell A10 B4 I/O Cell A9 I/O Cell I/O Cell A8 B5 A7 PROGRAMMABLE SWITCH MATRIX I/O Cell I/O Cell B6 I/O Cell A6 I/O Cell I/O Cell A5 B7 I/O Cell A4 I/O Cell I/O Cell A3 B8 I/O Cell A2 I/O Cell I/O Cell A1 B9 A0 B10 Bank A Figure 4. ispGDS22 Functional Block Diagram Bank B I/O Cell Closed only when C0=1 and C1=0 4:1 MUX Vcc 01 10 Switch Matrix 11 C0 00 C2 3 C1