ispLSI® 1048 Device Datasheet September 2010 All Devices Discontinued! Product Change Notification (PCN) #13-10 has been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line ispLSI 1048 Ordering Part Number ispLSI 1048-50LQ ispLSI 1048-70LQ ispLSI 1048-80LQ ispLSI 1048-50LQI Product Status Reference PCN Discontinued PCN#13-10 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: http://www.latticesemi.com ispLSI 1048 ® In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, Ten Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Security Cell Prevents Unauthorized Copying • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 80 MHz Maximum Operating Frequency — fmax = 50 MHz for Industrial Devices — tpd = 15 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested • IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging • COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 D Q A2 A3 Logic D6 D5 D Q D4 A D LL IS C DE O N VIC TI N ES U ED Output Routing Pool A0 A1 A4 Global Routing Pool (GRP) Array D Q GLB D3 D2 A5 D Q A6 D1 A7 Output Routing Pool Features D0 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool Output Routing Pool CLK Description The ispLSI 1048 is a High-Density Programmable Logic Device which contain 288 Registers, 96 Universal I/O pins, ten Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1048 devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 (see figure 1). There are a total of 48 GLBs in the ispLSI 1048 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 1048_07 1 January 2002 Specifications ispLSI 1048 Functional Block Diagram Figure 1. ispLSI 1048 Functional Block Diagram I/O I/O I/O I/O 95 94 93 92 I/O I/O I/O I/O 91 90 89 88 I/O I/O I/O I/O 87 86 85 84 I/O I/O I/O I/O 83 82 81 80 IN IN 11 10 I/O I/O I/O I/O 79 78 77 76 I/O I/O I/O I/O 75 74 73 72 I/O I/O I/O I/O 71 70 69 68 I/O I/O I/O I/O 67 66 65 64 IN 8 RESET Generic Logic Blocks (GLBs) Input Bus Output Routing Pool (ORP) Output Routing Pool (ORP) F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 A D LL IS C DE O N VIC TI N ES U ED F7 Input Bus I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 A0 D6 A1 D5 Global Routing Pool (GRP) A2 A3 A4 D4 D3 D2 A5 D1 A6 D0 lnput Bus Output Routing Pool (ORP) I/O 4 I/O 5 I/O 6 I/O 7 Input Bus I/O 0 I/O 1 I/O 2 I/O 3 Output Routing Pool (ORP) D7 IN 7 IN 6 I/O 6 I/O 6 I/O 6 I/O 6 I/O 5 I/O 5 I/O 5 I/O 5 I/O 5 I/O 5 I/O 5 I/O 5 I/O 5 I/O 5 I/O 4 I/O 4 A7 SDI/IN 0 MODE/IN 1 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus Input Bus C6 C7 Clock Distribution Network CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 Megablock ispEN SDO/ IN3 I/O I/O I/O I/O 16 17 18 19 I/O I/O I/O I/O 20 21 22 23 I/O I/O I/O I/O 24 25 26 27 I/O I/O I/O I/O 28 29 30 31 IN SCLK/ I/O I/O I/O I/O 4 IN 5 32 33 34 35 I/O I/O I/O I/O 36 37 38 39 I/O I/O I/O I/O 40 41 42 43 I/O I/O I/O I/O 44 45 46 47 Y Y Y Y 0 1 2 3 0139F(1)-48-isp The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. The device also has 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Clocks in the ispLSI 1048 device are selected using the Clock Distribution Network. Four dedicated clockpins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0 on the ispLSI 1048 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Eight GLBs, 16 I/O cells, two dedicated inputs (one dedicated input in Megablock B and E) and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The ispLSI 1048 device contains six of these Megablocks. 2 Specifications ispLSI 1048 Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C A D LL IS C DE O N VIC TI N ES U ED Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions SYMBOL PARAMETER MIN. MAX. UNITS Commercial TA = 0°C to +70°C 4.75 5.25 Industrial TA = -40°C to +85°C 4.5 5.5 Input Low Voltage 0 0.8 V Input High Voltage 2.0 Vcc + 1 V VCC Supply Voltage VIL VIH V Capacitance (TA=25oC, f=1.0 MHz) SYMBOL PARAMETER C1 C2 Dedicated Input Capacitance I/O and Clock Capacitance 1 MAXIMUM UNITS TEST CONDITIONS 8 pf VCC=5.0V, VIN=2.0V 10 pf VCC=5.0V, VI/O, VY=2.0V 1. Guaranteed but not 100% tested. Data Retention Specifications PARAMETER MINIMUM MAXIMUM 20 — Years 10000 — Cycles Data Retention Erase/Reprogram Cycles UNITS Table 2- 0008B 3 Specifications ispLSI 1048 Switching Test Conditions Input Pulse Levels Figure 2. Test Load GND to 3.0V Input Rise and Fall Time ≤ 3ns 10% to 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 5V R1 See figure 2 Device Output Test Point A D LL IS C DE O N VIC TI N ES U ED 3-state levels are measured 0.5V from steady-state active level. Table 2- 0003 CL* R2 Output Load Conditions (see figure 2) Test Condition R1 R2 CL 470Ω 390Ω 35pF Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF Active High to Z at VOH - 0.5V ∞ 390Ω 5pF Active Low to Z 470Ω 390Ω 5pF A B C *CL includes Test Fixture and Probe Capacitance. at VOL + 0.5V DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER CONDITION MIN. TYP.3 MAX. – 0.4 V UNITS VOL VOH IIL IIH IIL-isp IIL-PU IOS1 Output Low Voltage IOL =8 mA – Output High Voltage IOH =-4 mA 2.4 – – V Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) – – -10 μA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 μA isp Input Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) – – -150 μA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 μA Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA ICC2,4 Operating Power Supply Current VIL = 0.5V, VIH = 3.0V Commercial – 165 235 mA fTOGGLE = 1 MHz Industrial – 165 260 mA 1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using twelve 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25oC. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of this Lattice Semiconductor Data Book or CD-ROM to estimate maximum Table 2- 0007A-48-isp ICC. 4 Specifications ispLSI 1048 External Timing Parameters Over Recommended Operating Conditions 5 2 PARAMETER TEST # COND. -70 -50 UNITS MIN. MAX. MIN. MAX. MIN. MAX. A 1 Data Propagation Delay, 4PT bypass, ORP bypass – 15 – 18 – 24 ns A 2 Data Propagation Delay, Worst Case Path – 20 – 23 – 30.7 ns 80 – 71.4 – 53.6 – MHz A 3 Clock Frequency with Internal Feedback3 1 tsu2 + tco1 – 4 Clock Frequency with External Feedback ( – 5 Clock Frequency, Max Toggle4 – 6 A 50 – 41.7 – 31.3 – MHz 100 – 83 – 71.4 – MHz GLB Reg. Setup Time before Clock, 4PT bypass 7 – 9 – 12 – ns 7 GLB Reg. Clock to Output Delay, ORP bypass – 10 – 12 – 16 ns – 8 GLB Reg. Hold Time after Clock, 4 PT bypass 0 – 0 – 0 – ns – 9 GLB Reg. Setup Time before Clock 10 – 12 – 16 – ns – 10 GLB Reg. Clock to Output Delay – 12 – 14 – 18.7 ns – 11 GLB Reg. Hold Time after Clock 0 – 0 – 0 – ns A 12 Ext. Reset Pin to Output Delay – 17 – 17 – 22.7 ns – 13 Ext. Reset Pulse Duration 10 – 10 – 13 – ns B 14 Input to Output Enable – 18 – 20 – 26.7 ns C 15 Input to Output Disable – 18 – 20 – 26.7 ns – 16 Ext. Sync. Clock Pulse Duration, High 5 – 6 – 7 – ns – 17 Ext. Sync. Clock Pulse Duration, Low 5 – 6 – 7 – ns – 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) 2 – 2 – 2.7 – ns – 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 6.5 – 6.5 – 8.7 – ns ) A D LL IS C DE O N VIC TI N ES U ED tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5 -80 DESCRIPTION1 1. 2. 3. 4. 5. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit loadable counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section. Table 2- 0030A-48/80,70,50 5 Specifications ispLSI 1048 Internal Timing Parameters1 PARAMETER 2 -80 DESCRIPTION -70 -50 MIN. MAX. MIN. MAX. MIN. MAX. UNITS 20 I/O Register Bypass – 2.5 – 3.0 – 4.0 ns 21 I/O Latch Delay – 3.3 – 4.0 – 5.3 ns 22 I/O Register Setup Time before Clock 5.3 – 6.0 – 8.1 – ns A D LL IS C DE O N VIC TI N ES U ED Inputs tiobp tiolat tiosu tioh tioco tior tdin # GRP tgrp1 tgrp4 tgrp8 tgrp12 tgrp16 tgrp48 GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp 1.5 – 0.5 – 23 I/O Register Hold Time after Clock 0.9 – ns 24 I/O Register Clock to Out Delay – 2.5 – 3.0 – 3.9 ns 25 I/O Register Reset to Out Delay – 2.9 – 3.5 – 4.6 ns 26 Dedicated Input Delay – 5.0 – 6.0 – 8.0 ns 27 GRP Delay, 1 GLB Load – 2.1 – 2.5 – 3.3 ns 28 GRP Delay, 4 GLB Loads – 2.5 – 3.0 – 4.0 ns 29 GRP Delay, 8 GLB Loads – 3.3 – 4.0 – 5.3 ns 30 GRP Delay, 12 GLB Loads – 4.2 – 5.0 – 6.7 ns 31 GRP Delay, 16 GLB Loads – 5.0 – 6.0 – 8.0 ns 32 GRP Delay, 48 GLB Loads – 13.3 – 16.0 – 21.3 ns 33 4 Product Term Bypass Path Delay – 5.4 – 6.5 – 8.6 ns 34 1 Product Term/XOR Path Delay – 6.5 – 7.0 – 9.3 ns 35 20 Product Term/XOR Path Delay – 7.6 – 7.5 – 10.0 ns – 8.4 – 9.5 – 12.7 ns Delay3 36 XOR Adjacent Path 37 GLB Register Bypass Delay – 0.8 – 1.0 – 1.3 ns 38 GLB Register Setup Time before Clock 0.8 – 1.5 – 2.0 – ns 39 GLB Register Hold Time after Clock 5.0 – 6.0 – 8.0 – ns 40 GLB Register Clock to Output Delay – 2.1 – 2.5 – 3.3 ns 41 GLB Register Reset to Output Delay – 2.1 – 2.5 – 3.3 ns 42 GLB Product Term Reset to Register Delay – 8.3 – 10.0 – 13.3 ns 43 GLB Product Term Output Enable to I/O Cell Delay – 8.8 – 9.0 – 11.9 ns 44 GLB Product Term Clock Delay 2.9 6.3 3.5 7.5 4.6 9.9 ns 45 ORP Delay – 3.2 – 3.5 – 4.7 ns 46 ORP Bypass Delay – 1.3 – 1.5 – 2.0 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 6 Table 2- 0036A-48/80,70,50.eps Specifications ispLSI 1048 Internal Timing Parameters1 PARAMETER -80 DESCRIPTION -70 -50 MIN. MAX. MIN. MAX. MIN. MAX. UNITS 47 Output Buffer Delay – 2.5 – 3.0 – 4.0 ns 48 I/O Cell OE to Output Enabled – 4.2 – 5.0 – 6.7 ns 49 I/O Cell OE to Output Disabled – 4.2 – 5.0 – 6.7 ns A D LL IS C DE O N VIC TI N ES U ED Outputs tob toen todis 2 # Clocks tgy0 tgy1/2 tgcp tioy2/3 tiocp 50 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 4.2 4.2 5.0 5.0 6.7 6.7 ns 51 Clock Delay, Y1 or Y2 to Global GLB Clock Line 3.3 5.0 4.0 6.0 5.3 8.0 ns 52 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 4.2 1.0 5.0 1.3 6.6 ns 53 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 3.3 5.0 4.0 6.0 5.3 8.0 ns 54 Clock Delay, Clock GLB to I/O Cell Global Clock Line 0.8 4.2 1.0 5.0 1.3 6.6 ns – 9.2 – 8.0 – 10.6 ns Global Reset tgr 55 Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 7 Specifications ispLSI 1048 ispLSI 1048 Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In I/O Pin (Input) 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #28 #33 #37 #46 Input D Register Q RST #21 - 25 GRP Loading Delay #27, 29, 30, 31, 32 20 PT XOR Delays GLB Reg Delay ORP Delay GRP 4 #34, 35, 36 D Q #47 I/O Pin (Output) #48, 49 #45 A D LL IS C DE O N VIC TI N ES U ED #55 #26 I/O Reg Bypass #55 Reset Clock Distribution Y1,2,3 RST #51, 52, 53, 54 #38, 39, 40, 41 Control RE PTs OE #42, 43, CK 44 #50 Y0 Derivations of tsu, th and tco from the Product Term Clock1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) = (#20 + #28 + #35) + (#38) - (#20 + #28 + #44) 5.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (3.0 + 3.0 + 3.5) th = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#20 + #28 + #44) + (#39) - (#20 + #28 + #35) 6.0 ns = (3.0 + 3.0 + 7.5) + (6.0) - (3.0 + 3.0 + 7.5) tco = Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) = (#20 + #28 + #44) + (#40) + (#45 + #47) 22.5 ns = (3.0 + 3.0 +7.5) + (2.5) + (3.5 + 3.0) Derivations of tsu, th and tco from the Clock GLB1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) = (#20 + #28 + #35) + (#38) - (#50 + #40 + #52) 6.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (5.0 + 2.5 + 1.0) th = Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#50 + #40 + #52) + (#39) - (#20 + #28 + #35) 5.0 ns = (5.0 + 2.5 + 5.0) + (6.0) - (3.0 + 3.0 + 7.5) tco = Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) = (#50 + #40 + #52) + (#40) + (#45 + #47) 21.5 ns = (5.0 + 2.5 + 5.0) + (2.5) + (3.5 + 3.0) 1. Calculations are based upon timing specifications for the ispLSI 1048-70. 8 Specifications ispLSI 1048 Maximum GRP Delay vs GLB Loads ispLSI 1048-50 8 7 ispLSI 1048-70 5 ispLSI 1048-80 4 3 A D LL IS C DE O N VIC TI N ES U ED GRP Delay (ns) 6 2 1 0 4 8 GLB Loads 12 16 0126A-48-80-isp Power Consumption Power consumption in the ispLSI 1048 device depends on two primary factors: the speed at which the device is operating, and the number of Product Terms used. Fig- ure 3 shows the relationship between power and operating speed. Figure 3. Typical Device Power Consumption vs fmax ICC (mA) 250 ispLSI 1048 200 150 100 50 0 10 20 30 40 50 60 70 80 fmax (MHz) Notes: Configuration of Twelve 16-bit Counters Typical Current at 5V, 25¡C ICC can be estimated for the ispLSI 1048 using the following equation: ICC = 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127A-48-80-isp 9 Specifications ispLSI 1048 Pin Description NAME 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103, 109,110,111,112,113,114, 115,116,117,118,119,120, 1, 2, 3, 4 5, 6, 7, 8, 9, 10, 11, 12 DESCRIPTION Input/Output Pins - These are the general purpose I/O pins used by the logic array. A D LL IS C DE O N VIC TI N ES U ED I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 PQFP PIN NUMBERS IN 4 IN 6 - IN 11 48, 79,104,105, – 108, 13 ispEN 17 SDI/IN 01 19 MODE/IN 11 44 SDO/IN 31 47 SCLK/IN 51 73 RESET 18 Y0 14 Y1 78 Y2 75 Y3 74 GND VCC 46, 76,106, 16 15, 45, 77, 107 Dedicated input pins to the device. (IN 2 and IN 9 not available) Input – Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input – This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. Ground (GND) VCC 1. Pins have dual function capability. Table 2- 0002C-48-isp 10 Specifications ispLSI 1048 Pin Configuration 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 IN 10 VCC GND IN 8 IN 7 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 ispLSI 1048 120-Pin PQFP Pinout Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 Y1 VCC GND Y2 Y3 IN 5/SCLK1 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 A D LL IS C DE O N VIC TI N ES U ED I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 IN 11 Y0 VCC GND 1ispEN RESET 1SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 ispLSI 1048 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 1MODE/IN 1 VCC GND 1SDO/IN 3 IN 4 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Top View 1. Pins have dual function capability. 0124 -48-isp 11 Specifications ispLSI 1048 Part Number Description ispLSI 1048 — XX X X Device Family X Grade Blank = Commercial I = Industrial Package Q = PQFP Power L = Low Device Number A D LL IS C DE O N VIC TI N ES U ED Speed 80 = 80 MHz fmax 70 = 70 MHz fmax 50 = 50 MHz fmax 0212-80B-isp1048 ispLSI 1048 Ordering Information COMMERCIAL Family ispLSI fmax (MHz) tpd (ns) Ordering Number Package 80 15 ispLSI 1048-80LQ 120-Pin PQFP 70 18 ispLSI 1048-70LQ 120-Pin PQFP 50 24 ispLSI 1048-50LQ 120-Pin PQFP INDUSTRIAL Family ispLSI fmax (MHz) tpd (ns) 50 24 Ordering Number Package ispLSI 1048-50LQI 120-Pin PQFP Table 2- 0041A-48-isp 12