ICSSSTUB32864A Integrated Circuit Systems, Inc. Advance Information 25-Bit Configurable Registered Buffer for DDR2 Pin Configuration Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97U877 • Ideal for DDR2 400, 533, 667 and 800 1 2 3 4 5 6 A B C D Product Features: • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on C0, C1 and RESET# inputs • Low voltage operation VDD = 1.7V to 1.9V • Available in 96 BGA package • Drop-in replacement for ICSSSTUB32866 • Green packages available E F G H J K L M N P R T 96 Ball BGA (Top View) Ball Assignments Truth Table I nputs RST# DCS# CSR# Outputs CK CK# Dn, DODT, DCK E Qn QCS# QODT, QCKE H L L L L L L H L L H H L H A DCKE NC V REF V DD QCKE B D2 D15 GND GND Q2 NC Q15 C D3 D16 V DD V DD Q3 Q16 D DODT NC GND GND QODT NC D5 D17 V DD V DD Q5 Q17 H L L X Q0 Q0 Q0 E H L H L L L L GND GND Q6 Q18 L H H H L H Q0 F D6 G NC D18 H RST# V DD V DD C1 C0 H CK DCS# GND GND QCS# NC J K D8 CSR# V DD V DD ZOH ZOL D19 GND GND Q8 Q19 L D9 M D10 D20 V DD V DD Q9 Q20 D21 GND GND Q10 Q21 N D11 D22 V DD V DD Q11 Q22 P D12 D23 GND GND Q12 Q23 D13 D24 V DD V DD Q13 Q24 T D14 D25 V REF V DD Q14 L or H L or H H L H X Q0 Q0 H H L L L H L H H L H H H H X Q0 Q0 Q0 L Q0 H L H H L H H H L or H L or H L or H L or H H H H H Q0 H H H H H L or H L or H X Q0 Q0 Q0 L X or Floating X or Floating X or Floating X or Floating X or Floating L L L CK# R 1 2 3 4 Q25 5 1:1 Register (C0 = 0, C1 = 0) 1166—10/05/05 6 ICSSSTUB32864A Advance Information Ball Assignments Ball Assignments A D1 NC V REF V DD Q1A Q1B D2 NC GND GND Q2A Q2B C D3 D D4 NC V DD V DD Q3A Q3B QODTB NC GND GND Q4A Q4B Q5A Q5B E D5 NC V DD V DD Q5A Q5B Q6A Q6B F D6 NC GND GND Q6A Q6B NC RST# V DD V DD C1 C0 A DCKE NC V REF V DD QCKEA QCKEB D2 NC GND GND Q2A Q2B B C D3 D DODT NC V DD V DD Q3A Q3B NC GND GND QODTA E D5 NC V DD V DD F D6 NC GND GND B G NC RST# V DD V DD C1 C0 G H CK DCS# GND GND QCSA# QCSB# H CK DCS# GND GND QCSA# QCSB# J CK# CSR# V DD V DD ZOH ZOL J CK# CSR# V DD V DD ZOH ZOL K D8 NC GND GND Q8A Q8B K D8 NC GND GND Q8A Q8B D9 L M D10 NC V DD V DD Q9A Q9B L D9 NC V DD V DD Q9A Q9B NC GND GND Q10A Q10B M D10 NC GND GND Q10A Q10B N D11 NC V DD V DD Q11A Q11B N DODT NC V DD V DD QODTA QODTB P D12 NC GND GND Q12A Q12B P D12 NC GND GND Q12A Q12B R D13 NC V DD V DD Q13A Q13B R D13 NC V DD V DD Q13A Q13B T D14 NC V REF V DD Q14A Q14B T DCKE NC V REF V DD QCKEA QCKEB 5 6 1 2 3 4 1 1:2 Register A (C0 = 0, C1 = 1) 2 3 4 5 6 1:2 Register B (C0 = 1, C1 = 1) General Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUB32864A operates from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RST# must be held in the low state during power up. In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until the input receivers are fully enabled, the design of the ICSSSTUB32864A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS# and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST input has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not desired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC). 1166—10/05/05 2 ICSSSTUB32864A Advance Information Ball Assignment Terminal Name GND Description Electrical Characteristics Ground Ground input VDD Power supply voltage 1.8V nominal VREF Input reference voltage 0.9V nominal ZOH Reserved for future use Input ZOL Reserved for future use Input CK Positive master clock input Differential input CK# Negative master clock input Differential input C0, C1 Configuration control inputs LVCMOS inputs RST# Asynchronous reset input - resets registers and disables VREF data and clock differential-input receivers LV C M O S i n p u t CSR#, DCS# Chip select inputs - disables D1 - D24 outputs switching when both inputs SSTL_18 input are high Data input - clock in on the crossing of the rising edge of CK and the falling edge of CK# SSTL_18 input DODT The outputs of this register bit will not be suspended by the DCS# and CSR# control SSTL_18 input DCKE The outputs of this register bit will now be suspended by the DCS# and CSR# control SSTL_18 input Data ouputs that are suspended by the DCS# and CSR# control 1.8V CMOS Data output that will not be suspended by the DCS# and CSR# control 1.8V CMOS D1 - D25 Q1 - Q25 QCS# QODT Data output that will not be suspended by the DCS# and CSR# control 1.8V CMOS QCKE Data output that will not be suspended by the DCS# and CSR# control 1.8V CMOS 1166—10/05/05 3 ICSSSTUB32864A Advance Information Block Diagram for 1:1 mode (positive logic) RST# CK CK# VREF DCKE D C1 QCKEA C1 QODTA R DODT D R DCS# 1D C1 QCSA# R CSR# D1 0 1 1D Q1A C1 R To 21 Other Channels *Note: Disabled in 1:1 configuration 1166—10/05/05 4 Q1B* ICSSSTUB32864A Advance Information Block Diagram for 1:2 mode (positive logic) RST# CK CK# VREF DCKE 1D QCKEA C1 DODT R QCKEB* 1D QODTA C1 DCS# R QODTB* 1D QCSA# C1 R QCSB#* 1D Q1A CSR# D1 0 1 C1 R To 10 Other Channels *Note: Disabled in 1:1 configuration 1166—10/05/05 5 Q1B* ICSSSTUB32864A Advance Information Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDD or GND Current/Pin . . . . . . . . . . . . . . . . –65°C to +150°C -0.5V to 2.5V -0.5V to +2.5V -0.5V to VDD + 0.5V ±50 mA ±50mA ±50mA ±100mA Package Thermal Impedance3 36°C ............... Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 2.5V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions PARAMETER V DD VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (AC) VIH VIL VICR VID IOH IOL TA DESCRIPTION I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage RESET#, Input High Voltage Level C0, C1 Input Low Voltage Level Common mode Input Range CLK, CLK# Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature 1 MIN TYP 1.7 1.8 0.49 x VDD 0.5 x V DD V REF - 0.04 VREF 0 VREF + 0.125 VREF + 0.250 MAX 1.9 0.51 x VDD VREF + 0.04 VDD VREF - 0.125 VREF - 0.250 UNITS V 0.65 x VDD 0.675 0.600 0 0.35 x VDD 1.125 -8 8 70 mA °C Guaranteed by design, not 100% tested in production. Note: Reset# and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless Reset# is low. 1166—10/05/05 6 ICSSSTUB32864A Advance Information Electrical Characteristics - DC TA = 0 - 70°C; V DD = 1.8 +/-0.1V (unless otherwise stated) SYMBOL PARAMETERS V IK V OH V OL All Inputs II Standby (Static) I DD Operating (Static) I DDD Ci CONDITIONS I I = -18mA I OH = -6mA I OL = 6mA V I = V DD or GND RESET# = GND V I = V IH(AC) or V IL(AC), RESET# = VDD RESET# = VDD, Dynamic operating V I = V IH(AC) or V IL(AC), (clock only) CLK and CLK# switching 50% duty cycle. IO = 0 Dynamic Operating RESET# = VDD, (per each data input) V I = V IH(AC) or V IL (AC), CLK and CLK# switching 1:1 mode 50% duty cycle. One data Dynamic Operating input switching at half (per each data input) clock frequency, 50% 1:2 mode duty cycle Data Inputs V I = V REF ±350mV CLK and CLK# V ICR = 1.25V, V I(PP) = 360mV RESET# V I = V DD or GND Notes: 1 - Guaranteed by design, not 100% tested in production. 1166—10/05/05 7 VDD MIN 1.7V 1.7V 1.9V 1.2 TYP 1.8V UNITS V 0.5 5 100 -5 1.9V MAX -1.2 µA µA 40 mA 39 µ/clock MHz 19 µA/ clock MHz/data 35 2.5 2 3.5 3 2.5 pF ICSSSTUB32864A Advance Information Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) MIN MAX SYMBOL PARAMETERS Clock frequency 410 f clock Pulse duration, CK, CK High or Low tW 1 Differential inputs active time (See notes 1 and 2) tACT 10 Differential inputs inactive time (See notes 1 and 3) 15 t INACT DCS before CK, CK↓, 0.6 Setup time CSR high; CSR before CK, CK↓, DCS high DCS before CK, CK↓, 0.5 CSR Low Setup time tSU DODT, DCKE and data 0.5 before CK, CK↓ DCS, DODT, DCKE and 0.4 th Hold time data after CK, CK↓ PAR_IN after CK, CK↓ 0.4 1 - Guaranteed by design, not 100% tested in production. Notes: 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK# signal input slew rate of 1V/ns. UNITS MHz ns ns ns Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) From To VDD = 1.8V ±0.1V UNITS SYMBOL MIN TYP MAX (Input) (Output) fmax 410 MHz CLK, CLK# Q 1.1 1.5 ns t PDM1 Q t PDMSS2 CLK, CLK# RESET# Q tphl Notes: 1. Includes 350ps test-load transmission-line delay 2. Guaranteed by design, not 100% tested in production. 1.6 3 ns Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range (See figure 7) VDD = 1.8V ± 0.1V PARAMETER UNIT MIN MAX dV/dt_r 1 4 V/ns dV/dt_f 1 4 V/ns 1 dV/dt_∆ 1 V/ns 1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate) 1166—10/05/05 8 ns ns ns ns ns ICSSSTUB32864A Advance Information VDD DUT TL=50Ω CK Inputs CK# CK RL = 1000Ω TL=350ps, 50Ω Out Test Point CL = 30 pF (see Note 1) Test Point RL = 1000Ω RL = 100Ω LOAD CIRCUIT Test Point VCMOS RST# Inp ut VDD VDD/2 VDD/2 t in act IDD (see Note 2) V ID 0V CK CK t PLH 90% t PHL 10% VOH Output VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES VICR V TT VTT VICR VOLTAGE WAVEFORMS – PULSE DURATION LVCMOS RST# Input VID CK VIH VDD /2 VIL VICR t RPHL CK t su Inpu t VOL VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES VID tw Inpu t VICR VICR t act VREF VOH th Output VREF VIH VTT V OL VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES VIL VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES Figure 6 — Parameter Measurement Information (V DD = 1. 8 V ± 0.1 V) Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD/2 6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600 mV 9. tPLH and tPHL are the same as tPDM. 1166—10/05/05 9 ICSSSTUB32864A Advance Information VDD DUT RL = 50Ω Out Test Point C L = 10 pF (see Note 1) LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT Output VOH 80% 20% dv _f VOL dt _f VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT DUT Out Test Point CL = 10 pF (see Note 1) RL = 50Ω LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT dt _r dv _r 80% VOH 20% Output VOL VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT Figure 7 — Output Slew-Rate Measurement Information (V DD = 1.8V ± 0.1V) Notes: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 1166—10/05/05 10 ICSSSTUB32864A Advance Information C Seating Plane A1 T Numeric Designations for Horizontal Grid b REF 4 3 2 1 A B C D D Alpha Designations for Vertical Grid (Letters I, O, Q & S not used) d TYP D1 - e - TYP TOP VIEW E c REF h TYP 0.12 C - e - TYP E1 ALL DIMENSIONS IN MILLIMETERS ----- BALL GRID ----Max. T e HORIZ VERT TOTAL d Min/Max Min/Max 13.50 Bsc 5.50 Bsc 1.30/1.50 0.80 Bsc 6 16 96 0.40/0.50 11.50 Bsc 5.00 Bsc /1.2 0.65 Bsc 6 16 96 0.38/0.48 Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. D E h Min/Max 0.25/0.41 0.27/0.37 REF. DIMENSIONS b c 0.75 0.875 * Source Ref.: JEDEC Publication 95, 10-0055C Ordering Information ICSSSTUB32864Az(LF)T Example: ICS XXXX y z (LF) - T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type H = LFBGA (standard size: 5.5 x 13.50) HM = TFBGA (reduced size: 5.0 x 11.50) Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 1166—10/05/05 11 0.75 0.875 MO-205 ICSSSTUB32864A Advance Information Revision History Rev. 0.1 Issue Date Description 10/5/2005 Initial release Page # - 1166—10/05/05 12