IN-SYSTEM PROGRAMMABLE SUPERWIDE CPLDS TM ispLSI 5000VE PLDs for a 64-Bit World. BFW II: The Next Generation of SuperWIDE PLDs is Here! The ispLSI® 5000VE Family is the second generation of Lattice’s highly successful in-system programmable BFW CPLDs. An innovative SuperWIDE architecture supports the widest logic funcions, including 64-bit applications, in a single logic level, boosting complex logic speed by up to 60%. With 32 macrocells and 68 inputs per logic block, the ispLSI 5000VE delivers optimum performance for advanced system designs. The 3.3V ispLSI 5000VE family offers 5ns Tpd, 180MHz Fmax and user selectable 3.3V/ 2.5V outputs. The ispLSI 5000VE family is available in a wide range of densities, I/Os and packages. Choose from 128 to 512 macrocells and up to 256 I/Os. Advanced packaging includes space-saving TQFP, BGA and fine-pitch BGA packages. The new ispLSI 5000VE family is fully supported by Lattice’s easy-to-use and powerful ispLEVER™ design software, plus a wide range of popular third-party tools. Designing with ispLSI 5000VE devices is quick and easy using leading synthesis and simulation tools from Exemplar Logic, Model Technology, Synopsys, Synplicity, and Innoveda. Key Features and Benefits ■ The Industry’s Widest PLDs! • SuperWIDE Logic Blocks Deliver up to 60% Performance Boost SuperWIDE • Ideal for I/O Intensive Applications ■ • 32 Macrocells per GLB SuperWIDE CPLDs Deliver Superior Performance! Average Benchmarked Speed 60MHz 25% Faster • Up to 35 Product Terms Per Output ■ 3.3V Family with 4 Members Ranging from 128 to 512 Macrocells ■ 5ns Pin-to-Pin Delay and 180MHz System Performance ■ User Selectable 3.3V/2.5V I/O ■ TQFP, BGA and Fine-Pitch BGA Package Options ■ IEEE 1149.1 Boundary Scan Testable ■ ispJTAG™ In-System Programmable 60% Faster 40MHz 20MHz Typical Logic Functions Complex Logic Functions (1 to 68 Inputs) (Greater than 36 Inputs) 68 Input Logic Block 36 Input Logic Block Enhanced Generic Logic Blocks (GLB) • 68 Inputs per GLB ispLSI 5000VE Family FAMILY MEMBER MACROCELLS SPEED: Tpd SPEED: Fmax Vccio I/Os PIN/PACKAGE ispLSI 5128VE 128 5.0 ns 180 MHz 3.3V/2.5V 96 128-pin TQFP ispLSI 5256VE 256 6.0 ns 165 MHz 3.3V/2.5V 72 96 144 144 100-pin TQFP 128-pin TQFP 256-ball fpBGA* 272-ball BGA ispLSI 5384VE 384 6.0 ns 165 MHz 3.3V/2.5V 192 192 256-ball fpBGA* 272-ball BGA ispLSI 5512VE 512 6.5 ns 155 MHz 3.3V/2.5V 192 192 256 256 256-ball fpBGA* 272-ball BGA 388-ball fpBGA* 388-ball BGA * fpBGA = Fine Pitch BGA (1.0mm ball pitch) ispLSI 5000VE Advanced Packaging ispLSI 5000VE Block Diagram Generic Logic Block Generic Logic Block I N PUT B U S INPUT BUS Generic Logic Block Generic Logic Block Global Routing Pool (GRP) Generic Logic Block INPUT BUS Generic Logic Block Generic Logic Block INPUT BUS Boundary Scan Interface Generic Logic Block Generic Logic Block INPUT BUS I N PUT B U S Generic Logic Block INPUT BUS I N PUT B U S Generic Logic Block INPUT BUS I N PUT B U S Generic Logic Block I N PUT B U S I N PUT B U S ispLSI 5000VE Macrocell Global PTOE 0 Global PTOE 1 Global PTOE 2 Global PTOE 3 PTOE GOE0 GOE1 TOE PTSA bypass Product Term Sharing Array D Q Clk En PT Clock Shared PT Clock CLK0 CLK1 CLK2 CLK3 R/L Clk R P PT Reset Shared PT Reset Packages are shown actual size. Dimensions refer to package body size. Global Reset PT Preset Programmable Speed/Power Option Applications Support 1-800-LATTICE (528-8423) (408) 826-6002 [email protected] www.latticesemi.com Copyright © 2001 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), ISP, ispLSI, ispLEVER, ispJTAG and SuperWIDE are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. April 2001 Order #: I0121