7238

NTE7238 & NTE7238SM
Integrated Circuit
Video Sync Separator
Description:
The NTE7238 (8−Lead DIP) and NTE7238SM (SIOC−8) video sync separators extract timing information including composite and vertical sync, burst/back porch timing, and odd/even field information
from standard negative going sync NTSC, PAL(Note 1), and SECAM video signals with amplitude from
0.5V to 2Vp−p. These integrated circuits are also capable of providing sync separation for non−standard, faster horizontal rate video signals. The vertical output is produced on the rising edge of the first
serration in the vertical sync period. A default vertical output is produced after a time delay if the rising
edge mentioned above does not occur within the externally set delay period, such as might be the
case fo a non−standard video signal.
Features:
D AC Coupled Composite Input Signal
D > 10k Input Resistance
D < 10mA Power Supply Drain Current
D Composite Sync and vertical Outputs
D Odd/Even Field Output
D Burst Gate/Back Porch Output
D Horizontal Scan Rates to 150kHz
D Edge Triggered Vertical Output
D Default Triggered Vertical Output for Non−Standard Video Signal (Video Games−Home Computers)
Absolute Maximum Ratings: (Note 2)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V
Input Voltage (VCC = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Vp−p
Input Voltage (VCC  8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Vp−p
Output Sink Currents, Pin1, Pin3, and Pin5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Output Sink Current, Pin7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA
Package Dissipation (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100mW
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to +150C
Note 1. PAL in this datasheet refers to European broadcast TV standard “Phase Alternating Line”,
and not to Programmable Array Logic.
Note 2. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Note 3. For operation in ambient temperatures above +25C, the device must be derated based on a
+150C maximum junction temperature an a package thermal resistance of 110C/W, junction−
to−ambient.
Absolute Maximum Ratings (Cont’d): (Note 2)
ESD Susceptibility (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
ESD Susceptibility (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Soldering Information, 8−Lead DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260C
Soldering Information, SOIC−8
Vapor Phase (60sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +215C
Infrared (15sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
Note 2. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Note 4. ESD susceptibility test uses the “human body model, 100pF discharged through a 1.5k
resistor”.
Note 5. Machine Model, 220pF − 240pF discharged through all pins.
Electrical Characteristics: (VCC = 5V, RSET = 680k, TA = 0 to +70C by correlation with 100%
electrical testing at TA = +25C, Note 6)
Parameter
Supply Current
Test Conditions
Outputs at Logic 1
Min
Typ
Max
Unit
VCC = 5V
−
5.2
10
mA
VCC = 12V
−
5.5
12
mA
DC Input Voltage
Pin2
1.3
1.5
1.8
V
Input Threshold Voltage
Note 7
55
70
85
mV
Input Discharge Current
Pin2, VIN = 2V
6
11
16
A
Input Clamp Charge Current
Pin2, VIN = 1V
0.2
0.8
−
mA
RSET Pin Reference Voltage
Pin6, Note 8
1.10
1.22 1.35
V
Composite Sync & Vertical Outputs
IOUT = 40A, Logic 1
4.0
4.5
−
V
−
−
V
3.6
−
V
−
−
V
4.5
−
V
−
−
V
VCC = 5V
VCC = 12V 11.0
IOUT = 1.6mA, Logic 1
VCC = 5V
2.4
VCC = 12V 10.0
Burst Gate & Odd/Even Outputs
IOUT = 40A, Logic 1
VCC = 5V
4.0
VCC = 12V 11.0
Composite Sync Output
IOUT = −1.6mA, Logic 0, Pin1
−
0.2
0.8
V
Vertical Sync Output
IOUT = −1.6mA, Logic 0, Pin3
−
0.2
0.8
V
Burst Gate Output
IOUT = −1.6mA, Logic 0, Pin5
−
0.2
0.8
V
Odd/Even Output
IOUT = −1.6mA, Logic 0, Pin7
−
0.2
0.8
V
190
230
300
s
Vertical Sync Width
Burst Gate Width
2.7k from Pin5 to VCC
2.5
4.0
4.7
s
Vertical Default Time
Note 9
32
65
90
s
Note 6. Typicals are at TJ = +25C and represent the most likely parametric norm.
Note 7. Relative difference between the input clamp voltage and the minimum input voltage which
produces a horizontal output pulse.
Note 8. Careful attention should be made to prevent parasitic capacitance coupling from any output
pin (Pins 1, 3, 5, and 7) to the RSET pin (Pin6).
Note 9. Delay time between the start of vertical sync (at input) and the vertical output pulse.
Pin Connection Diagram
Composite Sync Output 1
8 VCC
Composite Video Input 2
Vertical Sync Output 3
7 Odd/Even Output
6 RSET
GND 4
8
5
5 Burst/Back Porch Output
NTE7238
.280 (7.1)
1
4
.400 (10.16)
Max
.300
(7.62)
.200
(5.08)
.100 (2.54)
.125 (3.17) Min
NTE7238SM
.192 (4.9)
8
1
5
4
.050 (1.27)
.236
(5.99)
.154
(3.91)
.016
(.406)
061
(1.53)
.006 (.152)
NOTE: Pin1 on Beveled Edge
.198 (5.03)