NTE40107B Integrated Circuit CMOS − Dual 2 Input NAND Buffer/Driver Description: The NTE40107B is a dual, 2−input, NAND buffer/driver in an 8−Lead DIP type package containing two independent 2−input NAND buffers with open−drain single N−Channel transistor outputs. This device features a wired−OR capability and high output sink current capability (136mA Typ. at VDD = 10V, VDS = 1V). Features: D 32 Times Standard B−Series Output Current Drive Sinking Capability: 136mA Typ. at VDD = 10V, VDS = 1V D 100% Tested for Quescient Current at 20V D Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25°C D 5V, 10V, and 15V Parametric Ratings D Noise margin, Full Package Temperature Range, RL to VDD = 10kΩ: 1V at VDD = 5V 2V at VDD = 10V 2.5V at VDD = 15V Applications: D Driving Relays, Lamps, and LEDs D Line Driver D Level Shifter (Up of Down) Absolute Maximum Ratings: DC Supply Voltage Range (Voltages Referenced to VSS Terminal), VDD . . . . . . . . . −0.5V to +2.0V Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Power Dissipation Per Package, PD For TA = −55° to +100°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW For TA = +100° to +125°C . . . . . . . . . . . . . . . . . . . . . Derate Linearity at 12mW/°C to 200mW Device Dissipation Per Output Transistor (TA = Full Package Temperature Range) . . . . . . 100mW Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55° to +125°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C Lead Temperature (During Soldering, 1/16” from Case for 10sec Max), TL . . . . . . . . . . . . . . +265°C Recommended Operating Conditions: (Note 1) Parameter Supply Voltage Range Symbol VDD Test Conditions TA = −55° to +125°C Min Typ Max Unit 3 − 18 V Note 1. For maximum reliability, nominal operating conditions should be selected so that operation is always within the above ranges. Dynamic Electrical Characteristics: (TA = +25°C, CL = 50pF, Input tr, tf = 20ns unless otherwise specified) Parameter Symbol Propagation Delay, High−to−Low tPHL Propagation Delay, Low−to−High Unit VDD = 5V − 100 200 ns VDD = 10V − 45 90 ns VDD = 15V − 30 60 ns VDD = 5V − 100 200 ns VDD = 10V − 60 120 ns VDD = 15V − 50 100 ns VDD = 5V − 50 100 ns VDD = 10V − 20 40 ns VDD = 15V − 10 20 ns VDD = 5V − 50 100 ns VDD = 10V − 35 70 ns VDD = 15V − 25 50 ns Any Input − 5.0 7.5 pF Any Output − 30 − pF RL = 120Ω, Note 2 CIN Average Output Capacitance Max RL = 120Ω, Note 2 tTLH Average Input Capacitance Typ RL = 120Ω, Note 2 tTHL Transition Time, Low−to−High Min RL = 120Ω, Note 2 tPLH Transition Time, High−to−Low Test Conditions COUT Note 2. RL is external pull−up resistor to VDD. Static Electrical Characteristics: Conditions Parameter Quiescent Device Current Output Low (Sink) Current Symbol IDDMax IOLMin Output High (Source) Current IOHMin Input Low Voltage (Note 3) VILMax Input High Voltage (Note 3) Input Current Output Leakage Current VIHMin IINMax IOZMax Limits at Indicated Temperatures (5C) +25 Unit VO (V) VIN (V) VDD (V) −55 −40 +85 +125 Min Typ Max − 0.5 5 1 1 30 30 − 0.02 1 μA − 0,10 10 2 2 60 60 − 0.02 2 μA − 0,15 15 4 4 120 120 − 0.02 4 μA − 0,20 20 20 20 600 600 − 0.04 20 μA 0.4 0,5 5 21 20 14 12 16 32 − mA 1 0,5 5 44 42 30 25 34 68 − mA 0.5 0,10 10 49 46 32 28 37 74 − mA 1 0,10 10 89 85 60 51 68 136 − mA 0.5 0,15 15 66 63 44 38 50 100 − mA No Internal Pull−Up Devices mA 4.5 − 5 − 1.5 − − 1.5 V 9 − 10 − 3.0 − − 3.0 V 13.5 − 15 − 4.0 − − 4.0 V 0.5,4.5 − 5 − 3.5 3.5 − − V 1,9 − 10 − 7 7 − − V 1.5,13.5 − 15 − 11 11 − − V − ±10−5 ±0.1 μA − 10−4 2 μA − 18 0,18 0,18 18 18 ±0.1 ±0.1 2 2 ±1 20 Note 3. Measured with external pull−up resistor, RL = 10kΩ to VDD. ±1 20 Special Considerations: Limiting Capacitive Currents for CL > 500pF, VDD > 15V. For VDD > 15V, and load capacitance (CL) from output to GND > 500pF, an external 25Ω series limiting resistor should be inserted between the output terminal and CL. No external resistor is necessary if CL < 500pF of VDD < 15V. Driving Inductive Loads. When using the NTE40107B to drive inductive loads, the load should be shunted with a diode to prevent high voltages from developing across the device output. Truth Table: A B C 0 0 1* Z# 1 0 1* Z# 0 1 1* Z# 1 1 0 * Requires external pull−up resistor (RL) to VDD. # Without pull−up resistor (3−state). Pin Connection Diagram (Top View) A 1 8 VDD B 2 7 D C=A⋅B 3 6 E VSS 4 8 5 F=D⋅E 5 .260 (6.6) Max 1 4 .400 (10.6) Max .325 (8.62) Max .200 (5.08) Max .100 (2.54) .125 (3.18) Min .300 (7.62)