IDT IDT5V993-7QI

IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK™
IDT5V993A
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT5V993A is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V993A has six programmable skew outputs
and two zero skew outputs. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate HIGH-MID-LOW levels.
When the GND/sOE pin is held low, all the outputs are synchronously
enabled. However, if GND/sOE is held high, all the outputs except 3Q0 and
3Q1 are synchronously disabled.
Furthermore, when the VCCQ/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input. When VCCQ/
PE is held low, all the outputs are synchronized with the negative edge of
REF. Both devices have LVTTL outputs with 12mA balanced drive outputs.
Ref input is 5V tolerant
3 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75MHz to 85MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
IDT5V993A-2: tSKEW0<250ps
IDT5V993A-5: tSKEW0<500ps
IDT5V993A-7: tSKEW0<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <200ps peak-to-peak
Available in QSOP package
•
•
•
•
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
GND/sO E
1Q 0
Skew
Select
1Q 1
3
3
1F1:0
V CCQ /PE
2Q 0
Skew
Select
2Q 1
3
3
REF
PLL
2F1:0
FB
3
FS
3Q 0
Skew
Select
3
3Q 1
3
3F1:0
4Q 0
4Q 1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2001
1
c
2001
Integrated Device Technology, Inc.
DSC 5408/1
IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
PIN CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
REF
1
28
Description
Supply Voltage to Ground
G ND
VI
–0.5 to +7
V
–0.5 to VCC+0.5
V
–0.5 to +5.5
V
0.66
W
–65 to +150
°C
2
27
TEST
FS
3
26
2F 1
REF Input Voltage
Maximum Power Dissipation (TA = 85°C)
3F 0
4
25
2F 0
5
24
G ND/sOE
V CCQ /PE
6
23
1F 1
V C CN
7
22
1F 0
4Q 1
8
21
V CC N
4Q 0
9
20
1Q 0
G ND
10
19
1Q 1
3Q 1
11
18
G ND
3Q 0
12
17
G ND
V C CN
13
16
2Q 0
FB
14
15
2Q 1
TSTG
Unit
DC Input Voltage
V C CQ
3F 1
Max
Storage Temperature
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter
CIN
QSOP
TOP VIEW
Description
Input Capacitance
Typ.
Max.
Unit
4
6
pF
NOTE:
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not
production tested.
PIN DESCRIPTION
Pin Name
Type
Description
REF
IN
Reference Clock Input
FB
IN
Feedback Input
TEST (1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control
Summary Table) remain in effect. Set LOW for normal operation.
GND/
sOE(1)
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level and GND/ sOE is HIGH, the nF[1:0] pins act as output disable
controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation.
VCCQ/PE
IN
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
nF[1:0]
IN
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.)
FS
IN
nQ[1:0]
OUT
VCCN
PWR
Power supply for output buffers
VCCQ
PWR
Power supply for phase locked loop and other internal circuitry
GND
PWR
Ground
Three output banks of two outputs with programmable skew (1Q:3Q), and 4Q output has fixed zero skew outputs.
NOTE:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit tU which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF1:0 control pins. In order
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF1:0 control pins.
2
IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
EXTERNAL FEEDBACK
By providing external feedback, the IDT5V993A gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW
FS = MID
FS = HIGH
Comments
Timing Unit Calculation (tU)
1/(44 x FNOM)
1/(26 x FNOM)
1/(16 x FNOM)
VCO Frequency Range (FNOM)(1,2)
15 to 35MHz
25 to 60MHz
40 to 85 MHz
±9.09ns
±9.23ns
±9.38ns
ns
±49°
±83°
±135°
Phase Degrees
% of Cycle Time
Skew Adjustment Range(3)
Max Adjustment:
±14%
±23%
±37%
Example 1, FNOM = 15MHz
tU = 1.52ns
—
—
Example 2, FNOM = 25MHz
tU = 0.91ns
tU = 1.54ns
—
Example 3, FNOM = 30MHz
tU = 0.76ns
tU = 1.28ns
—
Example 4, FNOM = 40MHz
—
tU = 0.96ns
tU = 1.56ns
Example 5, FNOM = 50MHz
—
tU = 0.77ns
tU = 1.25ns
Example 6, FNOM = 80MHz
—
—
tU = 0.78ns
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on
input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected
to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided
output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4t U in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
Skew (Pair #1, #2)
Skew (Pair #3)
LL(1)
–4tU
Divide by 2
LM
–3tU
–6tU
LH
–2tU
–4tU
ML
–1tU
–2tU
MM
Zero Skew
Zero Skew
MH
1tU
2tU
HL
2tU
4tU
HM
3tU
6tU
HH
4tU
Divide by 4
NOTE:
1. LL disables outputs if TEST = MID and GND/sOE = HIGH.
3
IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
Symbol
Description
VCC
Power Supply Voltage
TA
Ambient Operating Temperature
IDT5V993A-5, -7
IDT5V993A-2
(Industrial)
(Commercial)
Min.
Max.
Min.
Max.
Unit
3
3.6
3
3.6
V
-40
+85
0
+70
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
VIH
Input HIGH Voltage
Conditions
Min.
Max.
Unit
Guaranteed Logic HIGH (REF, FB Inputs Only)
2
—
V
—
0.8
V
VCC−0.6
—
V
VIL
Input LOW Voltage
Guaranteed Logic LOW (REF, FB Inputs Only)
VIHH
Input HIGH Voltage(1)
3-Level Inputs Only
VIMM
Input MID Voltage(1)
3-Level Inputs Only
VCC/2−0.3
VCC/2+0.3
V
VILL
Input LOW Voltage(1)
3-Level Inputs Only
—
0.6
V
IIN
Input Leakage Current
VIN = VCC or GND
—
±5
µA
—
±200
(REF, FB Inputs Only)
VCC = Max.
VIN = VCC
I3
3-Level Input DC Current (TEST, FS)
IPU
Input Pull-Up Current (VCCQ/PE)
HIGH Level
VIN = VCC/2
MID Level
—
±50
VIN = GND
LOW Level
—
±200
—
±100
µA
VCC = Max., VIN = GND
µA
IPD
Input Pull-Down Current (GND/sOE)
VCC = Max., VIN = VCC
—
±100
µA
VOH
Output HIGH Voltage
VCC = Min., IOH = −12mA
2.4
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 12mA
—
0.55
V
NOTE:
1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
ICCQ
Quiescent Power Supply Current
Test Conditions(1)
VCC = Max., TEST = MID, REF = LOW,
Typ.(2)
Max.
Unit
8
25
mA
VCC/PE = LOW, GND/sOE = LOW,
All outputs unloaded
∆ICC
Power Supply Current per Input HIGH
VCC = Max., VIN = 3V
1
30
µA
ICCD
Dynamic Power Supply Current per Output
VCC = Max., CL = 0pF
55
90
µA/MHz
ITOT
Total Power Supply Current
VCC = 3.3V, FREF = 20MHz, CL = 160pF(1)
29
—
VCC = 3.3V, FREF = 33MHz, CL = 160pF(1)
42
—
CL = 160pF(1)
76
—
VCC = 3.3V, FREF = 66MHz,
NOTE:
1. For eight outputs, each loaded with 20pF.
4
mA
IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Description (1)
Symbol
Min.
Max.
Unit
—
10
ns/V
tR, tF
Maximum input rise and fall times, 0.8V to 2V
tPWC
Input clock pulse, HIGH or LOW
3
—
ns
DH
Input duty cycle
10
90
%
REF
Reference Clock Input
3.75
85
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5V993A-2
Symbol Parameter
Min.
FNOM
VCO Frequency Range
tRPWH
REF Pulse Width HIGH(11)
tRPWL
tU
REF Pulse Width LOW
Typ.
IDT5V993A-5
Max.
Min.
Typ.
IDT5V993A-7
Max.
Min.
Typ.
Max.
Unit
See PLL Programmable Skew Range and Resolution Table
(11)
3
—
—
3
—
—
3
—
—
ns
3
—
—
3
—
—
3
—
—
ns
Programmable Skew Time Unit
See Control Summary Table
tSKEWPR
Zero Output Matched-Pair Skew (xQ0, xQ1)(1,2,3)
—
0.05
0.2
—
0.1
0.25
—
0.1
0.25
ns
tSKEW0
Zero Output Skew (All Outputs)(1,4)
—
0.1
0.25
—
0.25
0.5
—
0.3
0.75
ns
tSKEW1
Output Skew
—
0.25
0.5
—
0.6
0.7
—
0.6
1
ns
—
0.3
1.2
—
0.5
1.2
—
1
1.5
ns
—
0.25
0.5
—
0.5
0.7
—
0.7
1.2
ns
—
0.5
0.9
—
0.5
1
—
1.2
1.7
ns
—
—
0.75
—
—
1.25
—
—
1.65
ns
0
0.5
0
0.7
ns
0
1.2
0
1.2
ns
(Rise-Rise, Fall-Fall, Same Class Outputs)
tSKEW2
(1,6)
Output Skew
(1,6)
(Rise-Fall, Divided-Divided)
tSKEW3
Output Skew
(Rise-Rise, Fall-Fall, Different Class Outputs)
tSKEW4
(1,6)
Output Skew
(Rise-Fall, Nominal-Divided)(1,2)
tDEV
Device-to-Device Skew(1,2,7)
tPD
REF Input to FB Propagation Delay(1,9)
tODCV
(1)
Output Duty Cycle Variation from 50%
(1,10)
−0.25
−1.2
0
0.25
0
1.2
−0.5
−1.2
−0.7
−1.2
—
—
2
—
—
2.5
—
—
3
ns
—
—
1.5
—
—
3
—
—
3.5
ns
tPWH
Output HIGH Time Deviation from 50%
tPWL
Output LOW Time Deviation from 50%(1,11)
tORISE
Output Rise Time(1)
0.15
1
1.2
0.15
1
1.8
0.15
1.5
2.5
ns
tOFALL
Output Fall Time(1)
0.15
1
1.2
0.15
1
1.8
0.15
1.5
2.5
ns
—
—
0.5
—
—
0.5
—
—
0.5
ms
RMS
—
—
25
—
—
25
—
—
25
ps
Peak-to-Peak
—
—
200
—
—
200
—
—
200
tLOCK
tJR
PLL Lock Time
(1,8)
Cycle-to-Cycle Output Jitter
(1)
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t U delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
5. For IDT5V993A-2 tSKEW0 is measured with CL = 0pF; for CL = 20pF, tSKEW0 = 0.35ns Max.
6. There are 2 classes of outputs: Nominal (multiple of tU delay), and Divided (3Qx only in Divide-by-2 or Divide-by-4 mode).
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until t PD is within specified limits.
9. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.
10. Measured at 2V.
11. Measured at 0.8V.
5
IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST LOADS AND WAVEFORMS
V CC
150 Ω
Output
150 Ω
20pF
t ORISE
2.0V
0.8V
t OFALL
t PWH
t PWL
LVTTL Output Waveform
≤ 1ns
3.0V
2.0V
Vth = 1.5V
0.8V
0V
LVTTL Input Test Waveform
6
≤ 1ns
IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TIMING DIAGRAM
t R EF
t R PW L
t R PW H
RE F
t PD
t OD C V
t OD C V
FB
t JR
Q
t SKEW P R
t SKEW 0 , 1
t SKEW P R
t SKEW 0 , 1
O TH ER Q
t SKEW 3 , 4
t SKEW 3
t SKEW 3
REF D IVIDE D B Y 2
t SKEW 1 , 3, 4
t SKEW 2
REF D IVIDE D B Y 4
NOTES:
VCCQ/PE: The AC Timing Diagram applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the
negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same t U delay has been selected when all are loaded with 20pF and terminated
with 75Ω to VCC/2.
tSKEWPR:
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0:
The skew between outputs when they are selected for 0tU.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
tODCV:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 2V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
7
IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXX
XX
Device Type
Package
X
Process
Blank
I
Com m ercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Q
Quarter-Size Sm all outline Package
5V993A-2
5V993A-5
5V993A-7
3.3V Program mable Skew PLL Clock Driver TurboClock
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
8
for Tech Support:
[email protected]
(408) 654-6459