IDT IDT5T2010BBGI

IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
IDT5T2010
2.5V ZERO DELAY PLL
CLOCK DRIVER TERACLOCK™
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The IDT5T2010 is a 2.5V PLL clock driver intended for high performance computing and data-communications applications. The IDT5T2010
has ten outputs in five banks of two, plus a dedicated differential feedback.
The redundant input capability allows for a smooth change over to a
secondary clock source when the primary clock source is absent.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
The IDT5T2010 features a user-selectable, single-ended or differential
input to ten single-ended outputs. The clock driver also acts as a translator from
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs.
Selectable interface is controlled by 3-level input signals that may be hard-wired
to appropriate high-mid-low levels. The outputs can be synchronously
enabled/disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF.
2.5 VDD
5 pairs of outputs
Low skew: 50ps same pair, 100ps all outputs
Selectable positive or negative edge synchronization
Tolerant of spread spectrum input clock
Synchronous output enable
Selectable inputs
Input frequency: 4.17MHz to 250MHz
Output frequency: 12.5MHz to 250MHz
1.8V / 2.5V LVTTL: up to 250MHz
HSTL / eHSTL: up to 250MHz
Hot insertable and over-voltage tolerant inputs
3-level inputs for selectable interface
3-level inputs for feedback divide selection with multiply ratios
of(1-6, 8, 10, 12)
Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
Selectable differential or single-ended inputs and ten singleended outputs
PLL bypass for DC testing
External differential feedback, internal loop filter
Low Jitter: <75ps cycle-to-cycle
Power-down mode
Lock indicator
Available in BGA and VFQFPN packages
•
•
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
TxS
1sOE
OMODE
1Q0
Divide
Select
1Q1
1F2:1
2sOE
PD
PE
FS
LOCK
2Q0
Divide
Select
PLL_EN
FB
3
FB/
VREF2
2F2:1
3
DS1:0
3sOE
3Q0
Divide
Select
PLL
3Q1
0
REF0
REF0/
VREF0
2Q1
/N
3F2:1
4sOE
0
1
RxS
4Q0
Divide
Select
4Q1
1
REF1
REF1/
VREF1
4F2:1
5sOE
REF_SEL
Divide
Select
5Q0
5Q1
5F2:1
Divide
Select
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
QFB
QFB
INDUSTRIAL TEMPERATURE RANGE
FBF2:1
MARCH 2006
1
c
2006
Integrated Device Technology, Inc.
DSC 5981/29
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
1sOE
1Q0
1Q1
GND
GND
2Q1
2Q 0
2sOE
2F2
VDDQ
A
A
VDD
1F2
B
VDD
VDD
VDD
NC
1F1
GND
GND
2F1
NC
VDDQ
VDDQ
3F2
B
C
OMODE
VDD
VDD
VDD
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
3sOE
C
D
REF_
SEL
GND
VDD
VDD
GND
GND
GND
GND
VDDQ
VDDQ
NC
3Q 0
D
E
REF1
REF1
/VREF1
NC
VDD
GND
GND
GND
GND
VDDQ
VDDQ
3F1
3Q 1
E
F
REF0
REF0
/VREF0
VDD
VDD
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
F
G
FB
FB
/VREF2
VDD
VDD
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
G
H
PD
PLL_
EN
PE
VDD
GND
GND
GND
GND
VDDQ
VDDQ
4F1
4Q1
H
J
RxS
TxS
VDD
VDD
GND
GND
GND
GND
VDDQ
VDDQ
NC
4Q0
J
K
LOCK
VDD
VDD
VDD
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
4sOE
K
L
VDD
VDD
FS
NC
FBF1
GND
GND
5F1
NC
VDDQ
VDDQ
4F2
L
M
DS1
DS0
FBF2
QFB
QFB
GND
GND
5Q1
5Q0
5sOE
5F2
VDDQ
M
1
2
3
4
5
6
7
8
9
10
11
12
BGA
TOP VIEW
2
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
VDDQ
2sOE
2F 2
53
52
VDD
59
54
1F 1
60
VDDQ
1Q1
61
55
1Q0
62
2Q0
VDDQ
63
56
VDDQ
64
2Q1
1sOE
65
57
1F2
66
2F 1
VDD
67
58
OMODE
68
PIN CONFIGURATION
REF_SEL
1
51
VDD
VDD
2
50
3F 2
REF1
3
49
3sOE
REF1/VREF1
4
48
VDDQ
REF0
5
47
VDDQ
REF0/VREF0
6
46
3Q0
FB
7
45
3Q1
FB/VREF2
8
44
3F1
VDD
9
43
VDD
PE
10
42
4F 1
PD
11
41
4Q1
PLL_EN
12
40
4Q0
VDD
13
39
VDDQ
RxS
14
38
VDDQ
TxS
15
37
4sOE
LOCK
16
36
4F2
VDD
17
35
VDD
30
31
32
33
34
5Q0
VDDQ
VDDQ
5sOE
5F2
QFB
29
25
QFB
5Q 1
24
VDDQ
28
23
VDDQ
5F1
22
FBF2
27
21
FS
VDD
20
DS0
26
19
FBF1
18
DS1
GND
VFQFPN
TOP VIEW
3
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
VDDQ, VDD Power Supply
Voltage(2)
Max
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter
Unit
Description
Min.
Typ.
Max.
Unit
–0.5 to +3.6
V
CIN
Input Capacitance
2.5
3
3.5
pF
VI
Input Voltage
–0.5 to +3.6
V
COUT
Output Capacitance
—
6.3
7
pF
VO
Output Voltage
–0.5 to VDDQ +0.5
V
VREF
Reference Voltage(3)
–0.5 to +3.6
V
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature
–65 to +165
°C
NOTE:
1. Capacitance applies to all inputs except RxS, TxS, nF[2:1], FBF[2:1], and DS[1:0].
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDDQ and VDD internally operate independently. No power sequencing requirements
need to be met.
3. Not to exceed 3.6V.
RECOMMENDED OPERATING RANGE
Symbol
TA
VDD(1)
Description
Ambient Operating Temperature
Internal Power Supply Voltage
HSTL Output Power Supply Voltage
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage
2.5V LVTTL Output Power Supply Voltage
Termination Voltage
VDDQ(1)
VT
Min.
–40
2.3
1.4
1.65
Typ.
+25
2.5
1.5
1.8
VDD
VDDQ / 2
Max.
+85
2.7
1.6
1.95
Unit
°C
V
V
V
V
V
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
PIN DESCRIPTION
Symbol
REF[1:0]
REF[1:0]/
VREF[1:0]
I/O
I
I
Type
Adjustable(1)
Adjustable(1)
FB
FB/VREF2
I
I
Adjustable(1)
Adjustable(1)
Description
Clock input. REF[1:0] is the "true" side of the differential clock input. If operating in single-ended mode, REF[1:0] is the clock input.
Complementary clock input. REF[1:0]/VREF[1:0] is the "complementary" side of REF[1:0] if the input is in differential mode. If operating
in single-ended mode, REF[1:0]/VREF[1:0] is left floating. For single-ended operation in differential mode, REF[1:0]/VREF[1:0] should be set
to the desired toggle voltage for REF[1:0]:
2.5V LVTTL
VREF = 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL
VREF = 900mV
HSTL
VREF = 750mV
LVEPECL
VREF = 1082mV
Clock input. FB is the "true" side of the differential feedback clock input. If operating in single-ended mode, FB is the feedback clock input.
Complementary feedback clock input. FB/VREF2 is the "complementary" side of FB if the input is in differential mode. If operating in singleended mode, FB/VREF2 is left floating. For single-ended operation in differential mode, FB/VREF2 should be set to the desired toggle voltage
for FB:
2.5V LVTTL
VREF = 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL
VREF = 900mV
HSTL
VREF = 750mV
LVEPECL
VREF = 1082mV
NOTE:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
4
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION, CONTINUED
Symbol
I/O
Type
REF_SEL
I
LVTTL(1)
Description
Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.
nsOE
I
LVTTL(1)
Synchronous output enable. When nsOE is HIGH, nQ[1:0] are synchronously stopped. OMODE selects whether the outputs are gated
LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ[1:0] is stopped in a HIGH/LOW state. When OMODE is LOW, the outputs are tri-stated. Set nsOE LOW for normal operation.
QFB
O
Adjustable(2)
Feedback clock output
QFB
O
Adjustable(2)
Complementary feedback clock output
nQ[1:0]
O
Adjustable(2)
Five banks of two outputs
RxS
I
3-Level(3)
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF clock input
TxS
I
3-Level(3)
Sets the drive strength of the output drivers and feedback inputs to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL/eHSTL (LOW)
compatible. Used in conjuction with VDDQ to set the interface levels.
PE
I
LVTTL(1)
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock (has internal pull-up).
nF[2:1]
I
LVTTL(1)
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank (See Control Summary table)
FBF[2:1]
I
LVTTL(1)
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on the feedback bank (See Control Summary table)
FS
I
LVTTL(1)
Selects appropriate oscillator circuit based on anticipated frequency range. (See VCO Frequency Range Select.)
DS[1:0]
I
3-Level(3)
3-level inputs for feedback input divider selection (See Divide Selection table)
PLL_EN
I
LVTTL(1)
PLL enable/disable control. Set LOW for normal operation. When PLL_EN is HIGH, the PLL is disabled and REF[1:0] goes to all outputs.
PD
I
LVTTL(1)
Power down control. When PD is LOW, the inputs are disabled and internal switching is stopped. OMODE selects whether the outputs
are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/
HIGH, the nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the QFB is stopped in a LOW/HIGH state. When OMODE is
LOW, the outputs are tri-stated. Set PD HIGH for normal operation.
LOCK
O
LVTTL
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the
inputs. The output will be 2.5V LVTTL. (For more information on application specific use of the LOCK pin, please see AN237.)
OMODE
I
VDDQ
Output disable control. Determines the outputs' disable state. Used in conjunction with nsOE and PD. (See Output Enable/Disable and
Powerdown tables.)
LVTTL(1)
PWR
Power supply for output buffers. When using 2.5V LVTTL, VDDQ should be connected to VDD.
VDD
PWR
Power supply for phase locked loop, lock output, inputs, and other internal circuitry
GND
PWR
Ground
NOTES:
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V LVTTL signals as well.
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
OUTPUT ENABLE/DISABLE
nsOE
OMODE
Output
L
X
Normal Operation
H
L
Tri-State
H
H
Gated(1)
VCO FREQUENCY RANGE SELECT
FS(1)
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ[1:0] is stopped in a HIGH/LOW state.
OMODE
Output
H
X
Normal Operation
L
L
Tri-State
L
H
Gated(1)
Max.
Unit
LOW
50
125
MHz
HIGH
100
250
MHz
NOTE:
1. The level to be set on FS is determined by the nominal operating frequency of the
VCO. The VCO frequency (FNOM) always appears at nQ[1:0] outputs when they are
operated in their undivided modes. The frequency appearing at the REF[1:0] and
REF[1:0] /VREF[1:0] and FB and FB/VREF2 inputs will be FNOM when the QFB and QFB
are undivided and DS[1:0] = MM. The frequency of REF[1:0] and REF[1:0] /VREF[1:0]
and FB and FB/VREF2 inputs will be FNOM/2 or FNOM/4 when the part is configured for
frequency multiplication by using a divided QFB and QFB and setting DS[1:0] = MM.
Using the DS[1:0] inputs allows a different method for frequency multiplication (see
Divide Selection table).
POWERDOWN
PD
Min.
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the QFB is stopped in a
LOW/HIGH state.
5
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
EXTERNAL DIFFERENTIAL FEEDBACK
By providing a dedicated external differential feedback, the IDT5T2010
gives users flexibility with regard to divide selection. The FB and FB/
VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0]
signals at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
DIVIDE SELECTION TABLE
DS [1:0]
Divide-by-n
Permitted Output Divide-by-n connected to FB and FB/VREF2(1)
LL
2
1, 2
LM
3
1
LH
4
1, 2
ML
5
1, 2
MM
1
1, 2, 4
MH
6
1, 2
HL
8
1
HM
10
1
HH
12
1
NOTE:
1. Permissible output division ratios connected to FB and FB/VREF2. The frequencies of the REF[1:0] and REF[1:0]/VREF[1:0] inputs will be FNOM/N when the parts are configured for
frequency multiplication by using an undivided output for FB and FB/VREF2 and setting DS[1:0] to N (N = 1-6, 8, 10, 12).
CONTROL SUMMARY TABLE FOR ALL
OUTPUTS
nF2/FBF2
nF1/FBF1
Output Skew
L
L
Divide by 2
L
H
Zero Delay
H
L
Inverted
H
H
Divide by 4
6
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
INPUT/OUTPUT SELECTION(1)
Input
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
Input
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
Output
2.5V LVTTL
1.8V LVTTL
Output
eHSTL
HSTL
NOTE:
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the
REF[1:0] /VREF[1:0] and FB/VREF2 pins to be left floating. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring VREF[1:0] and VREF2. Differential
(DIF) inputs are used only in differential mode.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
VIHH
VIMM
VILL
Parameter
Input HIGH Voltage Level(1)
Input MID Voltage Level(1)
Input LOW Voltage Level(1)
I3
3-Level Input DC Current
(RxS, TxS, DS[1:0])
Input Pull-Up Current (PE)
IPU
Test Conditions
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
VIN = VDD
HIGH Level
VIN = VDD/2
MID Level
VIN = GND
LOW Level
VDD = Max., VIN = GND
Min.
VDD – 0.4
VDD/2 – 0.2
—
—
–50
–200
–100
Max
—
VDD/2 + 0.2
0.4
200
+50
—
—
Unit
V
V
V
μA
μA
NOTE:
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup,
the function and timing of the outputs may be glitched, and the PLL may require additional tLOCK time before all datasheet limits are achieved.
7
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL(1)
Symbol
Parameter
Input Characteristics
IIH
Input HIGH Current
IIL
Input LOW Current
VIK
Clamp Diode Voltage
VIN
DC Input Voltage
VDIF
DC Differential Voltage(2,8)
VCM
DC Common Mode Input Voltage(3,8)
VIH
DC Input HIGH(4,5,8)
VIL
DC Input LOW(4,6,8)
Single-Ended Reference Voltage(4,8)
VREF
Output Characteristics
Output HIGH Voltage
VOH
VOL
Output LOW Voltage
VOX
FB/FB Output Crossing Point
Test Conditions
VDD = 2.7V
VI = VDDQ/GND
VDD = 2.7V
VI = GND/VDDQ
VDD = 2.3V, IIN = -18mA
IOH = -8mA
IOH = -100μA
IOL = 8mA
IOL = 100μA
Min.
Typ.(7)
Max
Unit
—
—
—
- 0.3
0.2
680
VREF + 100
—
—
—
—
- 0.7
μA
750
±5
±5
- 1.2
+3.6
—
900
—
VREF - 100
—
VDDQ/2
—
—
0.4
0.1
VDDQ/2 + 150
VDDQ - 0.4
VDDQ - 0.1
—
—
VDDQ/2 - 150
750
V
V
V
mV
mV
mV
mV
V
V
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
POWER SUPPLY CHARACTERISTICS FOR HSTL OUTPUTS(1)
Symbol
IDDQ
Parameter
Quiescent VDD Power Supply Current(3)
IDDQQ
Quiescent VDDQ Power Supply Current(3)
IDDPD
IDDD
ITOT
Power Down Current
Dynamic VDD Power Supply
Current per Output
Dynamic VDDQ Power Supply
Current per Output
Total Power VDD Supply Current(4)
ITOTQ
Total Power VDDQ Supply Current(4)
IDDDQ
Test Conditions(2)
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQ = Max., CL = 0pF
Typ.
15
Max
25
Unit
mA
0.7
50
μA
0.8
13
3
20
mA
μA/MHz
VDD = Max., VDDQ = Max., CL = 0pF
16
25
μA/MHz
VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF
VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF
35
55
45
80
55
85
70
120
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
8
mA
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol
Parameter
Value
Units
VDIF
(1)
Input Signal Swing
1
V
VX
Differential Input Signal Crossing Point(2)
750
mV
VTHI
Input Timing Measurement Reference Level(3)
tR, tF
Input Signal Edge Rate(4)
Crossing Point
V
1
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR eHSTL(1)
Symbol
Parameter
Input Characteristics
IIH
Input HIGH Current
IIL
Input LOW Current
VIK
Clamp Diode Voltage
VIN
DC Input Voltage
VDIF
DC Differential Voltage(2,8)
VCM
DC Common Mode Input Voltage(3,8)
VIH
DC Input HIGH(4,5,8)
VIL
DC Input LOW(4,6,8)
VREF
Single-Ended Reference Voltage(4,8)
Output Characteristics
Output HIGH Voltage
VOH
VOL
Output LOW Voltage
VOX
FB/FB Output Crossing Point
Test Conditions
VDD = 2.7V
VI = VDDQ/GND
VDD = 2.7V
VI = GND/VDDQ
VDD = 2.3V, IIN = -18mA
IOH = -8mA
IOH = -100μA
IOL = 8mA
IOL = 100μA
Min.
Typ.(7)
Max
Unit
—
—
—
- 0.3
0.2
800
VREF + 100
—
—
—
—
- 0.7
μA
900
±5
±5
- 1.2
+3.6
—
1000
—
VREF - 100
—
V
V
V
mV
mV
mV
mV
VDDQ/2
—
—
0.4
0.1
VDDQ/2 + 150
V
V
V
V
mV
VDDQ - 0.4
VDDQ - 0.1
—
—
VDDQ/2 - 150
900
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in a differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
9
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS FOR eHSTL OUTPUTS(1)
Symbol
IDDQ
Parameter
Quiescent VDD Power Supply Current(3)
IDDQQ
Quiescent VDDQ Power Supply Current(3)
IDDPD
IDDD
ITOT
Power Down Current
Dynamic VDD Power Supply
Current per Output
Dynamic VDDQ Power Supply
Current per Output
Total Power VDD Supply Current(4)
ITOTQ
Total Power VDDQ Supply Current(4)
IDDDQ
Test Conditions(2)
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQ = Max., CL = 0pF
Typ.
15
Max
25
Unit
mA
1.7
50
μA
0.8
13
3
20
mA
μA/MHz
VDD = Max., VDDQ = Max., CL = 0pF
20
30
μA/MHz
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF
35
55
50
115
55
85
75
175
mA
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol
Parameter
Value
Units
VDIF
Input Signal Swing
(1)
1
V
VX
Differential Input Signal Crossing Point(2)
900
mV
VTHI
Input Timing Measurement Reference Level(3)
tR, tF
Input Signal Edge Rate(4)
Crossing Point
V
1
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
10
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR
LVEPECL(1)
Symbol
Parameter
Input Characteristics
IIH
Input HIGH Current
IIL
Input LOW Current
VIK
Clamp Diode Voltage
VIN
DC Input Voltage
VCM
DC Common Mode Input Voltage(3,5)
VREF
Single-Ended Reference Voltage(4,5)
VIH
DC Input HIGH
VIL
DC Input LOW
Test Conditions
VDD = 2.7V
VI = VDDQ/GND
VDD = 2.7V
VI = GND/VDDQ
VDD = 2.3V, IIN = -18mA
Min.
Typ.(2)
Max
Unit
—
—
—
- 0.3
915
—
1275
555
—
—
- 0.7
—
1082
1082
—
—
±5
±5
- 1.2
3.6
1248
—
1620
875
μA
V
V
mV
mV
mV
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation while in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL
Symbol
Parameter
Value
Units
VDIF
(1)
Input Signal Swing
732
mV
VX
Differential Input Signal Crossing Point(2)
1082
mV
(3)
VTHI
Input Timing Measurement Reference Level
tR, tF
Input Signal Edge Rate(4)
Crossing Point
V
1
V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
11
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 2.5V
LVTTL(1)
Symbol
Parameter
Input Characteristics
IIH
Input HIGH Current
IIL
Input LOW Current
VIK
Clamp Diode Voltage
DC Input Voltage
VIN
Single-Ended Inputs(2)
VIH
DC Input HIGH
DC Input LOW
VIL
Differential Inputs
VDIF
DC Differential Voltage(3,9)
VCM
DC Common Mode Input Voltage(4,9)
VIH
DC Input HIGH(5,6,9)
VIL
DC Input LOW(5,7,9)
Single-Ended Reference Voltage(5,9)
VREF
Output Characteristics
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Test Conditions
VDD = 2.7V
VI = VDDQ/GND
VDD = 2.7V
VI = GND/VDDQ
VDD = 2.3V, IIN = -18mA
IOH = -12mA
IOH = -100μA
IOL = 12mA
IOL = 100μA
Min.
Typ.(8)
Max
Unit
—
—
—
- 0.3
—
—
- 0.7
±5
±5
- 1.2
+3.6
μA
1.7
—
—
0.7
V
V
0.2
1150
VREF + 100
—
—
—
1350
—
VREF - 100
—
V
mV
mV
mV
mV
—
—
0.4
0.1
V
V
V
V
VDDQ - 0.4
VDDQ - 0.1
—
—
1250
1250
V
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and REF[1:0]/VREF[1:0] is left floating. If TxS is HIGH, FB/VREF2 should be left floating.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
12
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS FOR 2.5V LVTTL OUTPUTS(1)
Symbol
IDDQ
Parameter
Quiescent VDD Power Supply Current(3)
IDDQQ
Quiescent VDDQ Power Supply Current(3)
IDDPD
IDDD
ITOT
Power Down Current
Dynamic VDD Power Supply
Current per Output
Dynamic VDDQ Power Supply
Current per Output
Total Power VDD Supply Current(4)
ITOTQ
Total Power VDDQ Supply Current(4)
IDDDQ
Test Conditions(2)
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQ = Max., CL = 0pF
Typ.
15
Max
25
Unit
mA
12
50
μA
0.5
15
3
25
mA
μA/MHz
VDD = Max., VDDQ = Max., CL = 0pF
30
40
μA/MHz
VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF
VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF
40
60
80
200
60
90
120
300
mA
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol
VDIF
Parameter
Input Signal Swing(1)
(2)
VX
Differential Input Signal Crossing Point
VTHI
Input Timing Measurement Reference Level(3)
tR, tF
Input Signal Edge Rate(4)
Value
Units
VDD
V
VDD/2
V
Crossing Point
V
2.5
V/ns
NOTES:
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF
(AC) specification under actual use conditions.
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol
Parameter
Value
Units
VIH
Input HIGH Voltage
VDD
V
VIL
Input LOW Voltage
0
V
(1)
VTHI
Input Timing Measurement Reference Level
tR, tF
Input Signal Edge Rate(2)
VDD/2
V
2
V/ns
NOTES:
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
13
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 1.8V
LVTTL(1)
Symbol
Parameter
Input Characteristics
IIH
Input HIGH Current
IIL
Input LOW Current
VIK
Clamp Diode Voltage
DC Input Voltage
VIN
Single-Ended Inputs(2)
VIH
DC Input HIGH
DC Input LOW
VIL
Differential Inputs
VDIF
DC Differential Voltage(3,9)
VCM
DC Common Mode Input Voltage(4,9)
VIH
DC Input HIGH(5,6,9)
VIL
DC Input LOW(5,7,9)
Single-Ended Reference Voltage(5,9)
VREF
Output Characteristics
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Test Conditions
VDD = 2.7V
VI = VDDQ/GND
VDD = 2.7V
VI = GND/VDDQ
VDD = 2.3V, IIN = -18mA
Min.
Typ.(8)
Max
Unit
—
—
—
- 0.3
—
—
- 0.7
±5
±5
- 1.2
VDDQ + 0.3
μA
—
0.683(11)
V
V
—
975
—
VREF - 100
—
V
mV
mV
mV
mV
—
—
0.4
0.1
V
V
V
V
1.073(10)
—
0.2
825
VREF + 100
—
—
IOH = -6mA
IOH = -100μA
IOL = 6mA
IOL = 100μA
VDDQ - 0.4
VDDQ - 0.1
—
—
900
900
V
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is MID and REF[1:0]/VREF[1:0] is left floating. If TxS is MID, FB/VREF2 should be left floating.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. The input is guaranteed to toggle within ±200mV of VREF[1:0] when VREF[1:0]
is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the REF[1:0] input. To guarantee switching in voltage range
specified in the JEDEC 1.8V LVTTL interface specification, VREF[1:0] must be maintained at 900mV with appropriate tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIL = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.
14
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS(1)
Symbol
IDDQ
Parameter
Quiescent VDD Power Supply Current(3)
IDDQQ
Quiescent VDDQ Power Supply Current(3)
IDDPD
IDDD
ITOT
Power Down Current
Dynamic VDD Power Supply
Current per Output
Dynamic VDDQ Power Supply
Current per Output
Total Power VDD Supply Current(4)
ITOTQ
Total Power VDDQ Supply Current(4)
IDDDQ
Test Conditions(2)
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQ = Max., CL = 0pF
Typ.
15
Max
25
Unit
mA
1.5
50
μA
0.5
16
3
25
mA
μA/MHz
VDD = Max., VDDQ = Max., CL = 0pF
22
30
μA/MHz
VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF
VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF
40
70
55
135
60
105
85
205
mA
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
VDIF
Parameter
Value
Units
Input Signal Swing(1)
VDDI
V
(2)
VX
Differential Input Signal Crossing Point
VTHI
Input Timing Measurement Reference Level(3)
tR, tF
(4)
Input Signal Edge Rate
VDDI/2
mV
Crossing Point
V
1.8
V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable
results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
Parameter
Value
(1)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VTHI
Input Timing Measurement Reference Level(2)
tR, tF
Input Signal Edge Rate(3)
VDDI
V
0
V
VDDI/2
mV
2
V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
15
Units
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
FNOM
tRPW
tFPW
tSK(B)
tSK(O)
tSK1(ω)
tSK2(ω)
tSK1(INV)
tSK2(INV)
tSK(PR)
t(φ)
tODCV
tORISE
tOFALL
tL
tL(ω)
tL(REFSEL1)
tL(REFSEL2)
tL(PD)
tJIT(CC)
Parameter
VCO Frequency Range
Reference Clock Pulse Width HIGH or LOW
Feedback Input Pulse Width HIGH or LOW
Output Matched Pair Skew(1,2,4)
Output Skew (Rise-Rise, Fall-Fall, Nominal)(1,3)
Multiple Frequency Skew (Rise-Rise, Fall-Fall, Nominal-Divided, Divided-Divided)(1,3,4)
Multiple Frequency Skew (Rise-Fall, Nominal-Divided, Divided-Divided)(1,3,4)
Inverting Skew (Nominal-Inverted)(1,3)
Inverting Skew (Rise-Rise, Fall-Fall, Rise-Fall, Inverted-Divided)(1,3,4)
Process Skew(1,3.5)
REF Input to FB Static Phase Offset(6)
Output Duty Cycle Variation from 50%(7)
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
Output Rise Time(8)
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
(8)
Output Fall Time
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
Power-up PLL Lock Time(9)
PLL Lock Time After Input Frequency Change(9)
PLL Lock Time After Change in REF_SEL (9,11)
PLL Lock Time After Change in REF_SEL (REF1 and REF0 are different frequency)(9)
PLL Lock Time After Asserting PD Pin(9)
Cycle-to-Cycle Output Jitter (peak-to-peak)(10)
Min.
Typ.
Max
Unit
see VCO Frequency Range Select Table
1
—
—
ns
1
—
—
ns
—
—
50
ps
—
—
100
ps
—
—
100
ps
—
—
400
ps
—
—
400
ps
—
—
400
ps
—
—
300
ps
-100
—
100
ps
-375
—
375
ps
-275
—
275
—
—
1.2
ns
—
—
1
—
—
1.2
ns
—
—
1
—
—
1
ms
—
—
1
ms
—
—
100
μs
—
—
1
ms
—
—
1
ms
—
50
75
ps
tJIT(PER)
Period Jitter (peak-to-peak)(10)
—
—
tJIT(HP)
Half Period Jitter (peak-to-peak, QFB/QFB only)(10, 12)
—
—
125
ps
—
VDDQ/2 - 150
—
100
VDDQ/2 + 150
ps
mV
tJIT(DUTY)
VOX
Duty Cycle Jitter (peak-to-peak)(10)
HSTL and eHSTL Differential True and Complementary Output Crossing Voltage Level
QFB/QFB only(12)
VDDQ/2
75
ps
NOTES:
1. Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
2. tSK(B) is the skew between a pair of outputs (nQ0 and nQ1) when all outputs are selected as the same class.
3. The measurement is made at VDDQ/2.
4. There are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode).
5. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQ, ambient temperature, air flow, etc.).
6. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For TxS/RxS = MID or HIGH, the measurement is taken from VTHI on REF to VTHI on
FB. For TxS/RxS = LOW, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to zero delay, FB input divider set to divideby-one, and FS = HIGH.
7. tODCV is measured with all outputs selected for zero delay.
8. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
9. tL, tL(ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQ is stable and
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified
limits.
10. The jitter parameters are measured with all outputs selected for zero delay, FB input divider is set to divide-by-one, and FS = HIGH.
11. Both REF inputs must be the same frequency, but up to ±180° out of phase.
12. For HSTL/eHSTL outputs only.
16
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
AC DIFFERENTIAL INPUT SPECIFICATIONS(1)
Symbol
tW
Parameter
Reference/Feedback Input Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)(2)
Reference/Feedback Input Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)(2)
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
Min.
1
1
Typ.
—
—
Max
—
—
Unit
ns
VDIF
AC Differential Voltage(3)
400
—
—
mV
VIH
AC Input HIGH(4,5)
Vx + 200
—
—
mV
AC Input LOW(4,6)
—
—
Vx - 200
mV
AC Differential Voltage(3)
400
—
—
mV
VIL
LVEPECL
VDIF
(4)
VIH
AC Input HIGH
1275
—
—
mV
VIL
AC Input LOW(4)
—
—
875
mV
NOTES:
1. For differential input mode, RxS is tied to GND.
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined
by VDIF has been met or exceeded.
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level.
The AC differential voltage must be achieved to guarantee switching to a new state.
4. For single-ended operation, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. Refer to each input interface's DC specification for the correct VREF[1:0] range.
5. Voltage required to switch to a logic HIGH, single-ended operation only.
6. Voltage required to switch to a logic LOW, single-ended operation only.
17
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
AC TIMING DIAGRAM(1)
tRPWL
REF
tRPWH
REF
tODCV
tODCV
tODCV
tODCV
tFPWH
tFPWL
FB
FB
Q
tSK(O),
tSK(B)
tSK(O),
tSK(B)
OTHER Q
tSK1(INV)
tSK1(INV)
INVERTED Q
tSK2(ω),
tSK2(INV)
tSK2(INV)
tSK2(ω)
Q DIVIDED BY 2
tSK1(ω),
tSK2(INV)
tSK1(ω)
Q DIVIDED BY 4
NOTE:
1. The AC TIMING DIAGRAM applies to PE = VDD. For PE = GND, the negative edge of FB aligns with the negative edge of REF[1:0], divided outputs change on the negative
edge of REF[1:0], and the positive edges of the divide-by-2 and divide-by-4 signals align.
18
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
JITTER AND OFFSET TIMING WAVEFORMS
QFB
nQ[1:0], QFB
tcycle n
tcycle n + 1
tjit(cc) = tcycle n
tcycle n+1
Cycle-to-Cycle jitter
REF[1:0]
REF[1:0]
FB
FB
t(Ø)n + 1
t(Ø)n
∑
t(Ø) =
n=N
1
t(Ø)n
N
Static Phase Offset
NOTE:
1. Diagram for PE = H and TxS/RxS = L.
QFB
nQ[1:0], QFB
tW(MIN)
tW(MAX)
tJIT(DUTY) = tW(MAX) - tW(MIN)
Duty-Cycle Jitter
19
(N is a large number of samples)
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
QFB
nQ[1:0], QFB
tcycle n
QFB
nQ[1:0], QFB
1
fo
tjit(per) = tcycle n
1
fo
Period jitter
NOTE:
1. 1/fo = average period.
QFB
QFB
thalf period n+1
thalf period n
QFB
QFB
1
fo
tjit(hper) = thalf period n
Half-Period jitter
NOTE:
1. 1/fo = average period.
20
1
2 * fo
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND CONDITIONS
VDDI
R1
VIN
3 inch, ~50Ω
Transmission Line
VDD
VDDQ
R2
VDDI
REF[1:0]
D.U.T.
Pulse
Generator
R1
VIN
REF[1:0]
3 inch, ~50Ω
Transmission Line
R2
Test Circuit for Differential Input(1)
DIFFERENTIAL INPUT TEST CONDITIONS
Symbol
VDD = 2.5V ± 0.2V
Unit
R1
100
Ω
R2
100
Ω
VDDI
VCM*2
V
HSTL: Crossing of REF[1:0] and REF[1:0]
eHSTL: Crossing of REF[1:0] and REF[1:0]
VTHI
LVEPECL: Crossing of REF[1:0] and REF[1:0]
V
1.8V LVTTL: VDDI/2
2.5V LVTTL: VDD/2
NOTE:
1. This input configuration is used for all input interfaces. For single-ended testing,
the REF[1:0] must be left floating. For testing single-ended in differential input
mode, the VIN should be floating.
21
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
VDDQ
VDDQ
VDDQ
VDD
R1
VDDQ
VDD
R1
REF[1:0]
R2
CL
REF[1:0]
nQ[1:0]
D.U.T.
FB
QFB
FB
QFB
VDDQ
QFB
D.U.T.
CL
R2
R1
FB
QFB
FB
CL
SW1
R2
SW1
Test Circuit for Outputs
Test Circuit for Differential Feedback
OUTPUT TEST CONDITIONS
DIFFERENTIAL FEEDBACK TEST
CONDITIONS
Symbol
VDD = 2.5V ± 0.2V
Symbol
Unit
VDD = 2.5V ± 0.2V
Unit
VDDQ = Interface Specified
VDDQ = Interface Specified
CL
15
pF
CL
15
pF
R1
100
Ω
R1
100
Ω
R2
100
Ω
R2
100
Ω
VTHO
VDDQ / 2
V
VOX
HSTL: Crossing of QFB and QFB
V
SW1
TxS = MID or HIGH
Open
TxS = LOW
Closed
eHSTL: Crossing of QFB and QFB
VTHO
1.8V LVTTL: VDDQ/2
V
SW1
TxS = MID or HIGH
Open
TxS = LOW
Closed
2.5V LVTTL: VDDQ/2
22
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
RECOMMENDED LANDING PATTERN
NL 68 pin
NOTE:
All dimensions are in millimeters.
23
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XXXXX
Device Type
XX
Package
X
Package
I
-40°C to +85°C (Industrial)
BB
BBG
NL
NLG
Plastic Ball Grid Array
BGA - Green
Thermally Enhanced Plastic Very Fine
Pitch Quad Flat No Lead Package
VFQFPN - Green
5T2010
2.5V Zero Delay PLL Clock Driver Teraclock
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
24
for Tech Support:
[email protected]