HA-5102, HA-5104, HA-5114 Data Sheet April 1999 Dual and Quad, 8MHz and 60MHz, Low Noise Operational Amplifiers Low noise and high performance are key words describing HA-5102, HA-5104 and HA-5114. These general purpose amplifiers offer an array of dynamic specifications ranging from a 3V/µs slew rate and 8MHz bandwidth (5102/04) to 20V/µs slew rate and 60MHz gain-bandwidth-product (HA-5114). Complementing these outstanding parameters is a very low noise specification of 4.3nV/√Hz at 1kHz. Fabricated using the Intersil high frequency DI process, these operational amplifiers also offer excellent input specifications such as a 0.5mV offset voltage and 30nA offset current. Complementing these specifications are 108dB open loop gain and 60dB channel separation. Consuming a very modest amount of power (90mW/ package for duals and 150mW/package for quads), HA5102/04/14 also provide 15mA of output current. This impressive combination of features make this series of amplifiers ideally suited for designs ranging from audio amplifiers and active filters to the most demanding signal conditioning and instrumentation circuits. These operational amplifiers are available in dual or quad form with industry standard pinouts allowing for immediate interchangeability with most other dual and quad operational amplifiers. HA-5102 HA-5114 Dual, Comp. HA-5104 Quad, Uncomp. HA3-5102-5 HA7-5102-2 0 to 75 • Low Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3nV/√Hz • Bandwidth. . . . . . . . . . . . . . . . . . . . 8MHz (Compensated) 60MHz (Uncompensated) • Slew Rate . . . . . . . . . . . . . . . . . . . . 3V/µs (Compensated) 20V/µs (Uncompensated) • Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 0.5mV • Available in Duals or Quads Applications • • • • • • High Q, Active Filters Audio Amplifiers Instrumentation Amplifiers Integrators Signal Generators For Further Design Ideas, See Application Note AN554 Pinouts HA-5102 (PDIP, CERDIP) TOP VIEW OUT1 1 -IN1 2 +IN1 3 -IN1 2 PACKAGE 8 Ld CERDIP PKG. NO + E8.3 F8.3A +IN2 5 -IN2 6 F14.3 HA1-5104-5 0 to 75 14 Ld CERDIP F14.3 HA3-5104-5 0 to 75 14 Ld PDIP E14.3 HA9P5104-9 -40 to 85 16 Ld SOIC M16.3 HA3-5114-5 0 to 75 14 Ld PDIP E14.3 OUT1 1 M16.3 -IN1 2 16 Ld SOIC 4 + + 5 +IN2 13 -IN4 12 +IN4 V+ 4 14 Ld CERDIP 11 V+ + - - 2 3 OUT2 7 10 +IN3 9 -IN3 8 OUT3 HA5104/5114 (SOIC) TOP VIEW 16 OUT4 1 +- 4 +- +IN1 3 +IN2 5 -IN2 6 OUT2 7 NC 8 15 -IN4 14 +IN4 13 V- V+ 4 1 6 -IN2 14 OUT4 1 +IN1 3 -55 to 125 -40 to 85 7 OUT2 + V- 4 HA1-5104-2 HA9P5114-9 8 V+ OUT1 1 8 Ld PDIP -55 to 125 Features HA-5104 (PDIP, CERDIP) HA-5114 (PDIP) TOP VIEW Ordering Information TEMP. RANGE (oC) 2925.4 Quad, Comp. Refer to the /883 data sheet for military product. PART NUMBER File Number + - 2 + - 3 12 +IN3 11 -IN3 10 OUT3 9 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HA-5102, HA-5104, HA-5114 Absolute Maximum Ratings Thermal Information Supply Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . 40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY Output Short Circuit Duration (Note 3). . . . . . . . . . . . . . . . Indefinite Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) 8 Lead PDIP Package . . . . . . . . . . . . . 92 N/A 8 Lead CERDIP Package. . . . . . . . . . . 135 50 14 Lead CERDIP Package. . . . . . . . . . 80 30 14 Lead PDIP Package . . . . . . . . . . . . 86 N/A SOIC Package (HA-5104, HA-5114) . . 96 N/A Maximum Junction Temperature (Note 1, Hermetic Package) . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-5102/5104-2 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-5102/5104/5114-5 . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HA-5104/5114-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 175oC for hermetic packages, and below 150oC for plastic packages. 2. θJA is measured with the component mounted on an evaluation PC board in free air. 3. Any one amplifier may be shorted to ground indefinitely. VSUPPLY = ±15V, Unless Otherwise Specified Electrical Specifications HA-5104-2, -5 HA-5114 -5 HA-5102-2, -5 HA-5104-9 HA-5114-9 TEMP. (oC) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 25 - 0.5 2.0 - 0.5 2.5 - 0.5 2.5 mV Full - - 2.5 - - 3.0 - - 3.0 mV Offset Voltage Average Drift Full - 3 - - 3 - - 3 - µV/oC Bias Current 25 - 130 200 - 130 200 - 130 200 nA Full - - 325 - - 325 - - 500 nA 25 - 30 75 - 30 75 - 30 75 nA Full - - 125 - - 125 - - 125 nA Input Resistance 25 - 500 - - 500 - - 500 - kΩ Common Mode Range Full ±12 - - ±12 - - ±12 - - V 25 100 250 - 100 250 - 80 250 - kV/V Full 100 - - 100 - - 80 - - kV/V Common Mode Rejection Ratio (VCM = ±5.0V) Full 86 95 - 86 95 - 80 95 - dB Small Signal Bandwidth, HA-5102/5104 (AV = 1) 25 - 8 - - 8 - - 8 - MHz Gain Bandwidth Product, HA-5114 (AV = 10) 25 - 60 - - 60 - - 60 - MHz Channel Separation (Note 4) 25 - 60 - - 60 - - 60 - dB (RL = 10kΩ) Full ±12 ±13 - ±12 ±13 - ±12 ±13 - V (RL = 2kΩ) Full ±10 ±12 - ±10 ±12 - ±10 ±12 - V Output Current, (VOUT = ±5V) Full ±10 ±15 - ±10 ±15 - ±7 ±15 - mA Full Power Bandwidth (Note 5) HA-5102/5104 25 16 47 - 16 47 - 16 47 - kHz 25 191 318 - 191 318 - 191 318 - kHz PARAMETER INPUT CHARACTERISTICS Offset Voltage Offset Current TRANSFER CHARACTERISTICS Large Signal Voltage Gain, (VOUT = ±5V, RL = 2kΩ) OUTPUT CHARACTERISTICS Output Voltage Swing HA-5114 2 HA-5102, HA-5104, HA-5114 VSUPPLY = ±15V, Unless Otherwise Specified (Continued) Electrical Specifications HA-5104-2, -5 HA-5114 -5 HA-5102-2, -5 HA-5104-9 HA-5114-9 TEMP. (oC) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 25 - 110 - - 110 - - 110 - Ω HA-5102/5104 Full 1 - - 1 - - 1 - - V/V HA-5114 Full 10 - - 10 - - 10 - - V/V HA-5102/5104 25 - 108 200 - 108 200 - 108 200 ns HA-5114 25 - 48 100 - 48 100 - 48 100 ns HA-5102/5104 25 - 20 35 - 20 35 - 20 35 % HA-5114 25 - 30 40 - 30 40 - 30 40 % HA-5102/5104 25 1 3 - 1 3 - 1 3 - V/µs HA-5114 25 12 20 - 12 20 - 12 20 - V/µs HA-5102/5104 25 - 4.5 - - 4.5 - - 4.5 - µs HA-5114 25 - 0.6 - - 0.6 - - 0.6 - µs f = 10Hz 25 - 9 25 - 9 25 - 9 25 nV/√Hz f = 1kHz 25 - 4.3 6.0 - 4.3 6.0 - 4.3 6.0 nV/√Hz f = 10Hz 25 - 5.1 15 - 5.1 15 - 5.1 15 pA/√Hz f = 1kHz 25 - 0.57 3 - 0.57 3 - 0.57 3 pA/√Hz f = DC to 30kHz 25 - 870 - - 870 - - 870 - nVRMS Supply Current (All Amps) 25 - 3.0 5.0 - 5.0 6.5 - 5.0 6.5 mA Power Supply Rejection Ratio, (∆VS = ±5V) Full 86 100 - 86 100 - 80 100 - dB PARAMETER Output Resistance STABILITY Minimum Stable Closed Loop Gain TRANSIENT RESPONSE (Note 6) Rise Time Overshoot Slew Rate Settling Time (Note 7) NOISE CHARACTERISTICS (Note 8) Input Noise Voltage Input Noise Current Broadband Noise Voltage POWER SUPPLY CHARACTERISTICS NOTES: 4. Channel separation value is referred to the input of the amplifier. Input test conditions are: f = 10kHz; VIN = 100mVPEAK; RS = 1kΩ. Slew Rate 5. Full power bandwidth is guaranteed by equation: Full power bandwidth = ----------------------------- . 2πV PEAK 6. Refer to Test Circuits section of the data sheet. 7. Settling time is measured to 0.1% of final value for a 1V input step, and AV = -10 for HA-5114, and a 10V input step, AV = -1 for HA-5102/5104. 8. The limits for these parameters are guaranteed based on lab characterization, and reflect lot-to-lot variation. 3 HA-5102, HA-5104, HA-5114 Test Circuits and Waveforms HA-5102, HA-5104 2kΩ 2kΩ - IN + IN OUT + - 50pF 1kΩ 2kΩ 50pF OUTPUT +5V INPUT 200mV 0V INPUT -5V +5V OUTPUT 0V 0V -5V Vertical = 40mV/Div., Horizontal = 50ns/Div. (AV = +1) Vertical = 5V/Div., Horizontal = 5µs/Div. (AV = -1) FIGURE 1. LARGE SIGNAL RESPONSE CIRCUIT FIGURE 2. SMALL SIGNAL RESPONSE CIRCUIT HA-5114 +0.5V OUTPUT 200mV 0V INPUT -0.5V +5V 0V OUTPUT -5V Input = 0.5V/Div., Output = 5V/Div., Time = 500ns/Div. 4 INPUT 0V Input = 10mV/Div., Output = 50mV/Div., Time = 50ns/Div. HA-5102, HA-5104, HA-5114 Test Circuits and Waveforms (Continued) +15V 2N4416 IN + 5kΩ 500Ω (NOTE 9) OUT - TO OSCILLOSCOPE 5kΩ 1.8kΩ 2kΩ +15V 50pF + VOUT 200Ω - VIN -15V 200Ω (NOTE 9) 2kΩ 50pF 2kΩ NOTES: 9. AV = -1 (HA-5102/5104), AV = -10 (HA-5114). 10. Feedback and summing resistors should be 0.1% matched. NOTE: 11. Clipping diodes are optional, HP5082-2810 recommended. AV = +10. FIGURE 4. SETTLING TIME CIRCUIT FIGURE 3. LARGE AND SMALL SIGNAL RESPONSE CIRCUIT (AV = +10) Simplified Schematic V+ OUTPUT V+INPUT 5 -INPUT HA-5102, HA-5104, HA-5114 Typical Performance Curves 10 VS = ±15V, TA = 25oC NOISE CURRENT (pA/√Hz) NOISE VOLTAGE (nV/√Hz) 15 HIGH 10 TYPICAL LOW 5 0 10 100 VS = ±15V, TA = 25oC 5.0 1.0 0.5 0.1 10 1K 100 FIGURE 5. INPUT NOISE VOLTAGE DENSITY FIGURE 6. INPUT NOISE CURRENT DENSITY VS = ±15V, TA = 25oC, 50µV/Div., 1s/Div., AV = 1000V/V Input Noise = 0.232µVP-P FIGURE 7. 0.1Hz TO 10Hz NOISE VS = ±15V, TA = 25oC, 500µV/Div., 1s/Div., AV = 1000V/V Total Output Noise = 2.075µVP-P FIGURE 8. 0.1Hz TO 1MHz NOISE 2.0 2.0 VS = ±15V TA = 25oC OFFSET VOLTAGE (mV) INPUT OFFSET VOLTAGE (mV) 1K FREQUENCY (Hz) FREQUENCY (Hz) 1.5 1.0 0.5 0 -60 1.5 1.0 0.5 0 -40 -20 0 20 40 60 80 TEMPERATURE (oC) FIGURE 9. VIO vs TEMPERATURE 6 100 120 0 2 4 6 8 10 12 SUPPLY VOLTAGE (±V) FIGURE 10. VIO vs VS 14 16 18 HA-5102, HA-5104, HA-5114 4 2 VS = ±15V 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -60 -40 -20 (Continued) 100 VS = ±15V 90 INPUT BIAS CURRENT (nA) INPUT OFFSET CURRENT (nA) Typical Performance Curves 80 70 60 50 40 30 20 10 0 20 40 60 80 100 0 -60 120 -40 -20 TEMPERATURE (oC) TOTAL SUPPLY CURRENT (mA) TOTAL SUPPLY CURRENT (mA) 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 3 2 1 0 2 OPEN LOOP VOLTAGE GAIN (105V/V) OPEN LOOP VOLTAGE GAIN (105V/V) 1 0 40 60 80 TEMPERATURE (oC) FIGURE 15. AVOL vs TEMPERATURE 7 6 8 10 12 14 16 18 6K 8K 10K 5.5 2 20 4 FIGURE 14. ICC vs VS (HA-5102) 3 0 120 SUPPLY VOLTAGE (±V) 4 -20 100 0 120 VS = ±15V, ∆VO = ±10V, RL = 2kΩ -40 80 4 FIGURE 13. ICC vs TEMPERATURE (HA-5104/14) -60 60 TA = 25oC, IOUT = 0 TEMPERATURE (oC) 5 40 FIGURE 12. IBIAS vs TEMPERATURE VS = ±15V, IOUT = 0 -60 20 TEMPERATURE (oC) FIGURE 11. IIO vs TEMPERATURE 5 0 100 120 VO = ±10V, VS = ±15V 5.0 125oC 25oC 4.0 -55oC 3.0 2.0 1K 2K 4K LOAD RESISTANCE (Ω) FIGURE 16. AVOL vs LOAD RESISTANCE HA-5102, HA-5104, HA-5114 290 280 270 260 250 240 230 220 210 200 190 180 170 160 150 140 130 (Continued) 13 TA = 25oC, RL = 2kΩ TA = 25oC, RL = 2kΩ 12 MAX OUTPUT SWING (±V) 11 10 9 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 18 0 2 4 FIGURE 17. AVOL vs VS 10 12 14 16 18 0 VS = ±15V, TA = 25oC 40 -20 35 VOUT = -15V 30 -40 -60 VOUT = +15V 25 -80 20 0 50 100 150 200 250 300 350 400 -100 1K 450 10K TIME (SECONDS) 6 -20 225 VS = ±15V, RL = 2kΩ, CL = 50pF -55oC GAIN VOLTAGE GAIN (dB) 0 -40 +PSRR -PSRR -80 -100 1K -3 125oC GAIN -6 100K FREQUENCY (Hz) FIGURE 21. PSRR vs FREQUENCY 8 1M 135 45 0 -45 -12 125oC PHASE -18 10K 1M FIGURE 20. CMRR vs FREQUENCY 0 -60 100K FREQUENCY (Hz) FIGURE 19. OUTPUT SHORT CIRCUIT CURRENT vs TIME POWER SUPPLY REJECTION (dB) 8 FIGURE 18. VOUT vs VS CMRR (dB) OUTPUT CURRENT (mA) 45 6 SUPPLY VOLTAGE (±V) SUPPLY VOLTAGE (±V) -24 10K -135 -55oC PHASE 100K 1M 10M PHASE SHIFT (DEGREES) OPEN LOOP GAIN (kV/V) Typical Performance Curves -225 40M FREQUENCY (Hz) FIGURE 22. HA-5104/02 UNITY GAIN FREQUENCY RESPONSE HA-5102, HA-5104, HA-5114 Typical Performance Curves GAIN 10 5 0 -5 0 -10 45 PHASE -15 90 -20 135 -25 100 60 1K 10K 100K 1M 10M 180 100M PHASE SHIFT (DEGREES) VOLTAGE GAIN (dB) 15 60 40 HA-5102/5104 GAIN 20 HA-5114 GAIN 0 HA-5114 PHASE 45 90 HA-5102/5104 PHASE 100 1K 135 10K 100K 1M 10M 180 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 23. HA-5114 FREQUENCY RESPONSE FIGURE 24. OPEN LOOP GAIN vs FREQUENCY 1.1 SLEW RATE (NORMALIZED) 50 40 30 20 10 100 1K RL = 2kΩ, CL = 50pF, VS = ±15V 1.0 0.9 0.8 0.7 0.6 -60 0 10K -40 -20 0 FIGURE 25. SMALL SIGNAL OVERSHOOT vs CLOAD RL = 2kΩ, CL = 50pF, VS = ±15V 1.0 0.9 0.8 0.7 -40 -20 0 20 40 60 80 100 TEMPERATURE (oC) FIGURE 27. RISE TIME vs TEMPERATURE 9 40 60 80 100 FIGURE 26. SLEW RATE vs TEMPERATURE 1.1 0.6 -60 20 TEMPERATURE (oC) LOAD CAPACITANCE (pF) RISE TIME (NORMALIZED) OVERSHOOT (%) VS = ±15V, TA = 25oC, RL = 2kΩ , CL = 50pF 80 0 VS = ±15V, TA = 25oC, RL = 2kΩ 10 100 PHASE SHIFT (DEGREES) 20 120 AVCL = +10, TA = 25oC, RL = 2kΩ, CL = 50pF VOLTAGE GAIN (dB) 25 (Continued) 120 120 HA-5102, HA-5104, HA-5114 Die Characteristics PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ DIE DIMENSIONS: 98.4 mils x 67.3 mils x 19 mils 2500µm x 1710µm x 483µm SUBSTRATE POTENTIAL (POWERED UP): METALLIZATION: Unbiased Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ TRANSISTOR COUNT: 93 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5102 10 V- +IN1 -IN1 OUT1 +IN2 -IN2 OUT2 V+ HA-5102, HA-5104, HA-5114 Die Characteristics DIE DIMENSIONS: SUBSTRATE POTENTIAL (POWERED UP): 95 mils x 99 mils x 19 mils 2420µm x 2530µm x 483µm Unbiased TRANSISTOR COUNT: METALLIZATION: 175 Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PROCESS: Bipolar Dielectric Isolation PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ Metallization Mask Layout HA-5104 +IN2 V+ +IN1 -IN1 -IN2 OUT2 OUT1 OUT3 OUT4 -IN3 -IN4 +IN3 V- +IN4 HA-5114 +IN2 V+ +IN1 -IN2 -IN1 OUT2 OUT1 OUT3 OUT4 -IN3 -IN4 +IN3 11 V- +IN4 HA-5102, HA-5104, HA-5114 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 12 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 8 0.355 10.16 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 8 10.92 7 3.81 4 9 Rev. 0 12/93 HA-5102, HA-5104, HA-5114 Dual-In-Line Plastic Packages (PDIP) E14.3 (JEDEC MS-001-AA ISSUE D) N 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8 eA C 0.008 0.014 C D 0.735 0.775 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). 13 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 0.204 14 0.355 18.66 19.68 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 14 10.92 7 3.81 4 9 Rev. 0 12/93 HA-5102, HA-5104, HA-5114 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) LEAD FINISH 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 eA ccc M C A - B S e eA/2 c aaa M C A - B S D S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH 14 NOTES - b2 b MAX 0.014 α A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 8 8 8 Rev. 0 4/94 HA-5102, HA-5104, HA-5114 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) LEAD FINISH c1 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - eA ccc M C A - B S e eA/2 c aaa M C A - B S D S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 15 NOTES - b2 b MAX 0.014 α A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 14 14 8 Rev. 0 4/94 HA-5102, HA-5104, HA-5114 Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e α B S 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MILLIMETERS α 16 0o 1.27 6 16 8o 0o 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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