HD-6408 CMOS Asynchronous Serial Manchester Adapter (ASMA) March 1997 Features Description • Low Bit Error Rate The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder for creating a very high speed asynchronous serial data bus. The Encoder converts serial NRZ data (typically from a shift register) to Manchester II encoded data, adding a sync pulse and parity bit. The Decoder recognizes this sync pulse and identifies it as a Command Sync or a Data Sync. The data is then decoded and shifted out in NRZ code (typically into a shift register). Finally, the parity bit is checked. If there were no Manchester or parity errors the Decoder responds with a valid word signal. The Decoder puts the Manchester code to full use to provide clock recovery and excellent noise immunity at these very high speeds. • Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1MBit/s • Sync Identification and Lock-In • Clock Recovery • Manchester II Encoder, Decoder • Separate Encode and Decode • Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V • Single Power Supply • 24 Lead Package Ordering Information PACKAGE TEMP. RANGE PART NUMBER PKG. NO. PDIP -40oC to +85oC HD3-6408-9 E24.6 CERDIP -40oC to +85oC HD1-6408-9 E24.6 The HD-6408 can be used in many commercial applications such as security systems, environmental control systems, serial data links and many others. It utilizes a single 12 x clock and achieves data rates of up to one million bits per second with a very minimum overhead of only 4 bits out of 20, leaving 16 bits for data. Pinout HD-6408 (DIP) TOP VIEW VW 1 24 VCC ESC 2 23 EC TD 3 22 SCI SDO 4 21 SD DC 5 20 SS BZI 6 19 EE BOI 7 18 SDI UDI 8 17 BOO DSC 9 16 OI CDS 10 15 BZO DR 11 14 DBS 13 MR GND 12 d CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 5-1 File Number 2952.1 HD-6408 Block Diagrams ENCODER DECODER 11 23 ÷6 EC DR 14 BIT COUNTER DBS 13 MR SCI ESC SD SS 22 ÷2 BIT COUNTER 2 TD CDS 21 RESET 20 18 DATA 3 10 VALID WORD LATCH VALID WORD TEST CIRCUIT PARITY CHECK CHARACTER IDENTIFIER NRZ OUTPUT PORT SYNC LATCH COUNT DECODER 5 SYNC PARITY SDI 1 VW DC CHARACTER FORMER 15 16 17 9 BZO OI BOO DSC CLOCK SYNCHRONIZER 6 BZI 19 BOI EE UDI 5-2 7 8 TRANSITION FINDER 4 SDO HD-6408 Pin Description PIN TYPE SYMBOL SECTION DESCRIPTION 1 O VW Decoder Output high indicates receipt of a VALID WORD. 2 O ESC Encoder ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The Encoder samples SDI on the low-to-high transition of ESC. 3 O TD Decoder TAKE DATA output is high during receipt of data after identification of a sync pulse and two valid Manchester data bits. 4 O SDO Decoder SERIAL DATA OUT delivers received data in correct NRZ format. 5 I DC Decoder DECODER CLOCK input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the Decoder. Input a frequency equal to 12X the data rate. 6 I BZI Decoder A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative state. This pin must be held high when the Unipolar input is used. 7 I BOI Decoder A high input should be applied to BIPOLAR ONE IN when the bus is in its positive state, this pin must be held low when the Unipolar input is used. 8 I UDI Decoder With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition finder circuit. If not used this input must be held low. 9 O DSC Decoder DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK ÷ 12), synchronized by the recovered serial data stream. 10 O CDS Decoder COMMAND/DATA SYNC output high occurs during output of decoded data which was preceded by a Command synchronizing character. A low output indicates a Data synchronizing character. 11 I DR Decoder A high input to DECODER RESET during a rising edge of DECODER SHIFT CLOCK resets the decoder bit counting logic to a condition ready for a new word. 12 I GND Both GROUND supply pin. 13 I MR Both A high on MASTER RESET clears the 2:1 counters in both the encoder and decoder and the ÷ 6 counter. 14 O DBS Encoder DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER CLOCK. 15 O BZO Encoder BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative sense of a bipolar line driver. 16 I OI Encoder A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states. 17 O BOO Encoder BIPOLAR ONE OUT is an active low output designed to drive the one or positive sense of a bipolar line driver. 18 I SDI Encoder SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK. 19 I EE Encoder A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preceding cycle being completed). 20 I SS Encoder SYNC SELECT actuates a Command sync for an input high and data sync for an input low. 21 O SD Encoder SEND DATA is an active high output which enables the external source of serial data. 22 I SCI Encoder SEND CLOCK IN is 2X the Encoder data rate. 23 I EC Encoder ENCODER CLOCK is the input to the 6:1 divider. 24 I VCC Both VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin 24) to GND (pin 12) is recommended. 5-3 HD-6408 Encoder Operation During these sixteen periods the data should be clocked into the SD Input with every high-to-low transition of the ESC (3) - (4). After the sync and Manchester II encoded data are transmitted through the BOO and BZO outputs, the Encoder adds on an additional bit which is the (odd) parity for that word (5). If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time (5) as shown to prevent a consecutive word from being encoded. At any time a low on OI will force both bipolar outputs to a high state but will not affect the Encoder in any other way. The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SClock input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SClock by dividing the DClock. The Encoder’s cycle begins when EE is high during a falling edge of ESC (1). This cycle lasts for one word length or twenty ESC periods. At the next low-to-high transition of the ESC, a high at SS input actuates a Command sync or a low will produce a Data sync for that word (2). When the Encoder is ready to accept data, the SD output will go high and remain high for sixteen ESC periods (3) - (4). To Abort the Encoder transmission a positive pulse must be applied at MR. Any time after or during this pulse, a low-tohigh transition on SCI clears the internal counters and initializes the Encoder for a new word. 0 TIMING 1 2 3 4 5 6 7 15 16 17 18 19 SCI ESC EE SS DON’T CARE DON’T CARE VALID SD SDI 15 BOO 1ST HALF 2ND HALF BZO SYNC 1 2 SYNC 14 13 12 11 10 3 2 1 0 15 14 13 12 11 3 2 1 0 P 15 14 13 12 11 3 2 1 0 P 3 4 5-4 5 HD-6408 Decoder Operation The decoded data available at SDO is in a NRZ format. The DSC is provided so that the decoded bits can be shifted into an external register on every low-to-high transition of this clock (2) - (3). Note that DECODER SHIFT CLOCK may adjust its phase up until the time that TAKE DATA goes high. The Decoder requires a single clock with a frequency of 12 times the desired data rate applied at the DClock input. The Manchester II coded data can be presented to the Decoder in one of two ways. The BOI and BZI inputs will accept data from a differential output comparator. The UDI input can only accept noninverted Manchester II coded data (e.g. from BOO of an Encoder through an inverter to UDI). After all sixteen decoded bits have been transmitted (3) the data is checked for odd parity. A high on VW output (4) indicates a successful reception of a word without any Manchester or parity errors. At this time the Decoder is looking for a new sync character to start another output sequence. VALID WORD will go low approximately 20 DECODER SHIFT CLOCK periods after it goes high if not reset low sooner by a valid sync and two valid Manchester bits as shown (1). The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle. When a valid sync is recognized (1), the type of sync is indicated by the CDS output. If the sync character was a command, this output will go high (2) and remain high for sixteen DSC periods (3), otherwise it will remain low. The TD output will go high and remain high (2) - (3) while the Decoder is transmitting the decoded data through SDO. TIMING 0 1 2 At any time in the above sequence a high input on DR during a low-to-high transition of DSC will abort transmission and initialize the Decoder to start looking for a new sync character. 3 4 5 6 7 8 16 17 18 19 15 14 13 12 11 10 2 1 0 P 15 14 13 12 11 10 2 1 0 P DSC BOI BZI 1ST HALF 2ND HALF SYNC SYNC TD CDS SDO UNDEFINED VW FROM PREVIOUS RECEPTION 15 14 13 1 2 12 4 3 2 1 0 3 5-5 4 HD-6408 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical) θJA θJC CERDIP Package . . . . . . . . . . . . . . . . 50oC/W 11oC/W PDIP Package . . . . . . . . . . . . . . . . . . . 60oC/W N/A Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V DC Electrical Specifications SYMBOL Operating Temperature Range HD-6408-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC VCC = 5.0V ±10%, TA = -40oC to +85oC PARAMETER MIN TYP MAX UNITS TEST CONDITIONS VIH Logical “1” Input Voltage 70% VCC - - V VIL Logical “0” Input Voltage - 20% VCC - V VIHC Logical “1” Input Voltage (Clock) VCC -0.5 - - V VILC Logical “0” Input Voltage (Clock) - GND +0.5 - V II Input Leakage -1.0 - +1.0 µA VIN = VCC or GND, DIP Pins 5-8, 11, 13, 16, 18, 19, 20, 22, 23 VOH Logical “1” Output Voltage 2.4 - - V IOH = -3mA VOL Logical “0” Output Voltage - - 0.4 V IOL = 1.8mA ICCSB Supply Current Standby - 0.5 2 mA VIN = VCC = 5.5V Outputs Open ICCOP Supply Current Operating (Note 1) - 8.0 10.0 mA VCC = 5.5V, f = 15MHz NOTE: 1. Guaranteed but not 100% tested. AC Electrical Specifications VCC = 5.0V ±10%, TA = -40oC to +85oC SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS ENCODER TIMING (1) FEC Encoder Clock Frequency 0 - 12 MHz CL = 50pF (2) FESC Send Clock Frequency 0 - 2.0 MHz CL = 50pF (3) TECR Encoder Clock Rise Time - - 8 ns CL = 50pF (4) TECF Encoder Clock Fall Time - - 8 ns CL = 50pF (5) FED Data Rate 0 - 1.0 MHz CL = 50pF (6) TMR Master Reset Pulse Width 150 - - ns CL = 50pF (7) TE1 Shift Clock Delay - - 125 ns CL = 50pF (8) TE2 Serial Data Setup 75 - - ns CL = 50pF (9) TE3 Serial Data Hold 75 - - ns CL = 50pF (10) TE4 Enable Setup 90 - - ns CL = 50pF (11) TE5 Enable Pulse Width 100 - - ns CL = 50pF 5-6 HD-6408 AC Electrical Specifications VCC = 5.0V ±10%, TA = -40oC to +85oC SYMBOL PARAMETER (Continued) MIN TYP MAX UNITS TEST CONDITIONS (12) TE6 Sync Setup 55 - - ns CL = 50pF (13) TE7 Sync Pulse Width 150 - - ns CL = 50pF (14) TE8 Send Data Delay 0 - 50 ns CL = 50pF (15) TE9 Bipolar Output Delay - - 130 ns CL = 50pF (16) TE10 Enable Hold 10 - - ns CL = 50pF (17) TE11 Sync Hold 95 - - ns CL = 50pF DECODER TIMING (18) FDC Decoder Clock Frequency 0 - 12 MHz CL = 50pF (19) TDCR Decoder Clock Rise Time - - 8 ns CL = 50pF (20) TDCF Decoder Clock Fall Time - - 8 ns CL = 50pF (21) FDD Data Rate 0 - 1.0 MHz CL = 50pF (22) TDR Decoder Reset Pulse Width 150 - - ns CL = 50pF (23) TDRS Decoder Reset Setup Time 75 - - ns CL = 50pF (24) TDRH Decoder Reset Hold Time 10 - - ns CL = 50pF (25) TMR Master Reset Pulse Width 150 - - ns CL = 50pF (26) TD1 Bipolar Data Pulse Width TDC +10 - - ns Note 1, CL = 50pF (27) TD2 Sync Transition Span - 18TDC - ns Note 1, CL = 50pF (28) TD3 One Zero Overlap - - TDC -10 ns Note 1, CL = 50pF (29) TD4 Short Data Transition Span - 6TDC - ns Note 1, CL = 50pF (30) TD5 Long Data Transition Span - 12TDC - ns Note 1, CL = 50pF (31) TD6 Sync Delay (ON) -20 - 110 ns CL = 50pF (32) TD7 Take Data Delay (ON) 0 - 110 ns CL = 50pF (33) TD8 Serial Data Out Delay - - 80 ns CL = 50pF (34) TD9 Sync Delay (OFF) 0 - 110 ns CL = 50pF (35) TD10 Take Data Delay (OFF) 0 - 110 ns CL = 50pF (36) TD11 Valid Word Delay 0 - 110 ns CL = 50pF NOTE: 1. TDC = Decoder Clock Period = 1/FDC. (These parameters are guaranteed but not 100% tested). Capacitance SYMBOL TA = +25oC PARAMETER MIN TYP MAX UNITS TEST CONDITIONS FREQ = 1MHz, all measurements are referenced to device GND CIN Input Capacitance - 15 - pF CO Output Capacitance - 15 - pF 5-7 HD-6408 AC Testing Input, Output Waveform INPUT VIH VOH 50% 50% VIL VOL NOTE: AC Testing: All input signals must switch between VIL and VIH. Input rise and fall times are driven at 1ns per volt. Encoder Timing (7) SCI TE1 ESC SDI TE3 (9) VALID VALID TE2 (8) SC (7) TE1 TE10 (16) (10) TE4 ESC (17) TE11 EE (11) TE5 (12) TE6 SS VALID TE7 (13) ESC (14) TE8 SD SC (15) TE9 BOO OR BZO 5-8 HD-6408 Decoder Timing NOTE: UI = 0, FOR NEXT DIAGRAMS BIT PERIOD BOI TD1 (26) BIT PERIOD TD2 (27) BZI BIT PERIOD TD3 (28) TD3 (28) TD1 (26) TD2 (27) COMMAND SYNC TD1 (26) TD3 (28) BOI TD2 (27) BZI TD1 (26) (28) TD3 DATA SYNC TD2 (27) BOI BZI TD1 (26) TD1 (26) TD3 (28) TD3 TD3 (28) TD3 (28) (28) TD3 (28) TD1 (26) TD4 TD5 (30) TD5 (30) TD4 (29) (29) ONE ZERO ONE NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS (27) UI TD2 COMMAND SYNC (27) TD2 UI DATA SYNC UI (27) TD2 TD4 (29) (27) TD2 (30) TD5 ONE TD5 (30) ZERO 5-9 ONE (29) (29) TD4 TD4 ONE HD-6408 Decoder Timing DSC (Continued) (31) TD6 CDS TD DSC TD7 (32) (33) TD8 DATA BIT SDO DSC (34) TD9 CDS (35) TD10 TD (36) TD11 VW DSC (23) TDRS (22) TDR DR (24) TDRH 5-10 HD-6408 Decoder Timing DSC (Continued) (31) TD6 CDS TD6 TD (32) DSC (33) TD8 DATA BIT SDO DSC (34) TD8 CDS (35) TD10 TD (34) TD11 VW DSC DR (34) TD11 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 5-11