IRFF430 Data Sheet March 1999 2.75A, 500V, 1.500 Ohm, N-Channel Power MOSFET • 2.75A, 500V Formerly developmental type TA17415. Ordering Information IRFF430 PACKAGE TO-205AF 1894.4 Features This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. PART NUMBER File Number • rDS(ON) = 1.500Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND D IRFF430 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-205AF SOURCE DRAIN (CASE) GATE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRFF430 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFF430 500 500 2.75 11 ±20 25 0.2 300 -55 to 150 UNITS V V A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to TJ = 125oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA (Figure 10) 500 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS , ID = 250µA 2.0 - 4.0 V VDS = Rated BVDSS , VGS = 0V - - 25 µA VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA Zero-Gate Voltage Drain Current IDSS On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) 2.75 - - A - - ±100 nA - 1.3 1.500 Ω 3.0 - S - - 30 ns - - 30 ns td(OFF) - - 55 ns tf - - 30 ns - 22 30 nC - 11 - nC - 11 - nC - 600 - pF - 100 - pF - 30 - pF - 5.0 - nH - 15 - nH - - 5.0 oC/W - - 175 oC/W gfs tr Turn-Off Delay Time VGS = ±20V 2.5 rDS(ON) td(ON) Rise Time VDS > ID(ON) x rDS(ON)MAX , VGS = 10V (Figure 7) Qg(TOT) Gate to Source Charge Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse-Transfer Capacitance CRSS Internal Drain Inductance LD Internal Source Inductance LS VGS = 10V, ID = 1.5A (Figures 8, 9) VDS ≥ 10V, ID = 2.7A (Figure 12) ID ≈ 2.75A, RG = 9.1Ω, VDD = 225V, RL = 80Ω, VGS = 10V (Figures 17, 18), MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = 10V, ID ≈ 2.75A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA (Figures 14, 19, 20), Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) Measured from the Drain Lead, 5mm (0.2in) from Header to Center of Die Modified MOSFET Symbol Showing the Internal Device Measured from the Source Inductances Lead, 5mm (0.2in) from D Header and Source LD Bonding Pad G LS S Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA 2 Free Air 0peration IRFF430 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier D MIN TYP MAX UNITS - - 2.75 A - - 11 A G S Source to Drain Diode Voltage (Note 2) TJ = 25oC, ISD = 2.75A, VGS = 0V (Figure 13) - - 1.4 V trr TJ = 150oC, ISD = 2.75A, dISD/dt = 100A/µs - 800 - ns QRR TJ = 150oC, ISD = 2.75A, dISD/dt = 100A/µs - 4.6 - µC VSD Reverse Recovery Time Reverse Recovered Charge NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, start TJ = 25oC, L = 69.42mH, RG = 50Ω, peak IAS = 2.75A (Figures 15, 16). Typical Performance Curves Unless Otherwise Specified 3.0 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0 2.4 1.8 1.2 0.6 0.2 0 50 100 0 25 150 50 TC, CASE TEMPERATURE (oC) 75 125 100 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 0.5 THERMAL IMPEDANCE ZθJC, NORMALIZED TRANSIENT POWER DISSIPATION MULTIPLIER 1.2 0.2 0.1 0.1 PDM 0.05 t1 t2t2 0.02 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 0.01 10-2 10-5 SINGLE PULSE 10-4 10-3 10-2 0.1 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 1 10 IRFF430 Typical Performance Curves Unless Otherwise Specified (Continued) 6 20 VGS = 5.5V 10 VGS = 10V ID , DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 5 10 s 100 s 1 1ms OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 10ms 100ms 0.1 DC TC = 25oC TJ = MAX RATED SINGLE PULSE 0.01 VGS = 5V 4 3 VGS = 4.5V 2 1 VGS = 4V 0 10 102 VDS , DRAIN TO SOURCE VOLTAGE (V) 1 80µs PULSE TEST 103 0 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 5 VGS = 5V 3 VGS = 4.5V 2 1 300 5 ID(ON) , ON-STATE DRAIN CURRENT (A) ID , DRAIN CURRENT (A) VGS = 5.5V 4 200 FIGURE 5. OUTPUT CHARACTERISTICS VGS = 10V 80µs PULSE TEST 100 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 4V VDS > ID(ON) x rDS(ON)MAX 80µs PULSE TEST 4 3 TJ = 125oC TJ = 25oC 2 TJ = -55oC 1 0 0 0 2 4 6 8 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 10 1 2 3 5 4 6 7 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 4 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VGS = 20V ON RESISTANCE rDS(ON) , DRAIN TO SOURCE VGS = 10V 3 2 1 0 5 10 15 20 ID , DRAIN CURRENT (A) 25 2.2 VGS = 10V ID = 1.5A 1.8 1.4 1.0 0.6 0.2 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) NOTE: Heating effect of 2µs pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 160 IRFF430 Typical Performance Curves Unless Otherwise Specified (Continued) 2000 VGS = 0V, f = 1MHz CISS = CGS + CGD 1.15 CRSS = CGD COSS ≈ CDS + CGD 1600 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 1.05 0.95 1200 CISS 800 0.85 400 COSS CRSS 0.75 -40 40 0 80 120 0 160 1 10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 5 100 ISD, SOURCE TO DRAIN CURRENT (A) TJ = -55oC TJ = 25oC TJ = 125oC 3 2 1 0 80µs PULSE TEST TJ = 25oC TJ = 150oC 10 TJ = 150oC TJ = 25oC 1 0 1 2 3 ID , DRAIN CURRENT (A) 4 5 0 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 1 2 3 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS , GATE TO SOURCE VOLTAGE (V) gfs , TRANSCONDUCTANCE (S) 80µs PULSE TEST 4 50 ID = 2.75A VDS = 400V VDS = 250V VDS = 100V 15 10 5 0 0 8 16 24 32 40 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 4 IRFF430 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS - VGS VDS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 IG(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 6 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRFF430 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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