DS7310 00

RT7310
Phase-Cut Dimmable Primary-Side Regulation
LED Driver Controller with Active PFC
General Description
Features
The RT7310 is a high power factor constant current
LED driver which is optimized for the compatibility with
phase-cut dimmers. It supports high power factor
across a wide range of line voltages, and it drives the
converter in the Quasi-Resonant (QR) mode to achieve
higher efficiency. By using Primary Side Regulation
(PSR), RT7310 controls the output current accurately


Maximum/Minimum Switching Frequency
Clamping
without a shunt regulator and an opto-coupler at the
secondary side, reducing the external component count,
the cost, and the volume of the driver board.

Maximum/Minimum On-Time Limitation
Wide VDD Range (up to 25V)
Multiple Protection Features :
 LED Open-Circuit Protection
 LED Short-Circuit Protection
 Output Diode Short-Circuit Protection




The RT7310 supports phase-cut dimmers, including
leading-edge (TRIAC) and trailing-edge dimmers.
RT7310 embeds comprehensive protection functions for
robust designs, including LED open circuit protection,
LED short circuit protection, output diode short-circuit
protection, VDD Under-Voltage Lockout (UVLO), VDD
Over-Voltage Protection (OVP), Over-Temperature
Protection (OTP), and cycle-by-cycle current limitation.


Supporting Phase-Cut Dimmers
Tight LED Current Regulation
No Opto-Coupler and TL431 Required
Power Factor Correction (PFC)
Quasi-Resonant




VDD Under-Voltage Lockout
VDD Over-Voltage Protection
Over-Temperature Protection
Cycle-by-Cycle Current Limitation
Application
 Phase-Cut Dimmable LED luminaries
Simplified Application Circuit
Flyback Converter
L1
Line
Tapped-Inductor Buck-Boost Converter
RDMR2
CX
Neutral
RDMR1
CDMR
RST1
NP
Q2
CM
VOUT+
NS
RT7310
DZ
Line
CS
BD
TX1
RDMR2
COUT
CX
VOUTQ1
GD
DST
L1
DOUT
TX1
BD
Neutral
RDMR1
CDMR
N1
DST
GD
CS
VDD
CCOMP
COMP
GND
ZCD
RZCD2
COMP
GND
CCOMP
ZCD
NA
DAUX
DAUX
DS7310-00
October
2014
Q1
RZCD2
N3
RZCD1
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
RPC
RCS
CVDD
CVDD
COUT
RT7310
DZ
RPC
VOUTDOUT
VOUT+
Q2
CM
RCS
VDD
N2
RST1
RZCD1
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1
RT7310
Ordering Information
Marking Information
RT7310
3K=DNN
Package Type
E : SOT-23-6
Lead Plating System
G : Green (Halogen Free and Pb Free)
3K= : Product Code
DNN : Date Code
Pin Configuration
(TOP VIEW)
Note :
COMP ZCD CS
Richtek products are :

RoHS compliant and compatible with the current
6
5
4
2
3
requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
GND VDD GD
SOT-23-6
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
GND
Ground of the Controller.
2
VDD
Supply Voltage (VDD) input. The controller will be enabled when VDD exceeds
VTH_ON and disabled when VDD is lower than VTH_OFF.
3
GD
Gate Driver Output for External Power MOSFET.
4
CS
Current Sense Input. Connect this pin to the current sense resistor.
5
ZCD
Zero Current Detection Input. This pin is used to sense the voltage at auxiliary
winding of the transformer for detecting demagnetization time of the magnetizing
inductance.
6
COMP
Compensation Node. Output of the internal trans-conductance amplifier.
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is a registered trademark of Richtek Technology Corporation.
DS7310-00
October
2014
RT7310
Function Block Diagram
ZCD
Valley Valley Signal
Detector
Clamping
Circuit
VDD OVP
Starter
ICS
LeadingEdge
Blanking
CS
UnderVoltage
Lockout
(16V/9V)
UVLO
PWM
Control
Logic
Constant Current
with Phase-Cut
Dimming Control
VDD
VDD
Over-Voltage
Protection
VCLAMP 13V
PWM
GD
Gate
Driver
RGD
OverTemperature
Protection
OTP
GND
Output
Output OVP
Over-Voltage
Protection
COMP
Operation
Critical-Conduction Mode (CRM) with Constant
IL_PK 
VIN_PK  sin(θ)  tON
Lm
On-Time Control
Figure 1 shows a typical flyback converter with input
voltage (VIN). When main switch Q1 is turned on with
a fixed on-time (tON), the peak current (IL_PK) of the
magnetic inductor (Lm) can be calculated by the
following equation :
When the converter operates in CRM with constant
on-time control, the envelope of the peak inductor
current will follow the input voltage waveform with
in-phase. Thus, high power factor can be achieved, as
shown in Figure 2.
V
IL_PK  IN  tON
Lm
TX1
DOUT
NP : NS
IOUT
+
IL
COUT
Lm
VIN
VOUT
ROUT
Q1
Figure 1. Typical Flyback Converter
If the input voltage is the output voltage of the
full-bridge rectifier with sinusoidal input voltage
(VIN_PKsin()), the inductor peak current (IL_PK) can be
expressed as the following equation :
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7310-00
October
2014
VIN
Input Voltage
Iin_avg
Average Input Current
IL_PK
Peak Inductor Current
IDOUT
Output Diode Current
IQ1_DS MOSFET Current
VQ1_GS MOSFET Gate Voltage
Figure 2. Inductor Current of CRM with Constant
On-Time Control
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RT7310
Primary-Side Constant-Current Regulation
Quasi-Resonant Operation
RT7310 needs no shunt regulator and opto-coupler at
For improving converter’s efficiency, RT7310 detects
the secondary side to achieve the output current
regulation. Figure 3 shows several key waveforms of a
conventional flyback converter in Quasi-Resonant (QR)
mode, in which VAUX is the voltage on the auxiliary
winding of the transformer.
valleys of the Drain-to-Source voltage (VDS) of main
switch and turns it on near the selected valley. For the
valley detections, a pulse of the “valley signal” is
generated after a 500ns (typ.) delay time which starts at
which the voltage (VZCD) on ZCD pin goes down and
reaches the voltage threshold (VZCDT, 0.4V typ.).
VDS
VIN
0
GD
(VGS)
VAUX
0
During the rising of the VZCD, the VZCD must reach the
voltage threshold (VZCDA, 0.5V typ.). Otherwise, no
pulse of the “valley signal” is generated. Moreover, if
the timing when the falling VZCD reaches VZCDT is not
later than a mask time (tMASK, 2s typ.) then the valley
signal will be masked and regards as no valley, as
shown in Figure 4.
(VOUT + Vf) x NA / NS
VIN x NA / NP
Clamped by
controller
PWM
～
～
IQ1
VZCD
～
～
IDOUT
VZCDA
VZCDT
Figure 3. Key Waveforms of a Flyback Converter
Voltage Clamping Circuit
RT7310 provides a voltage clamping circuit at ZCD pin
since the voltage on the auxiliary winding is negative
when the main switch is turned on. The lowest voltage
on ZCD pin is clamped near zero to prevent the IC from
being damaged by the negative voltage. Meanwhile,
the sourcing ZCD current (IZCD_SH), flowing through the
upper resistor (RZCD1), is sampled and held to be a
line-voltage-related signal for propagation delay
compensation. RT7310 embeds the programmable
propagation delay compensation through CS pin. A
sourcing current ICS (equal to IZCD_SH x KPC) applies a
voltage offset (ICS x RPC) which is proportional to line
voltage on CS to compensate the propagation delay
effect. Thus, the total power limit or output current can
be equal at high and low line voltage.
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Valley
Signal
500ns
tMASK
Figure 4. Valley Signal Generating Method
Figure 5 illustrates how valley signal triggers PWM. If
no valley signal detected for a long time, the next PWM
is triggered by a starter circuit at end of the interval
(tSTART, 75s typ.) which starts at the rising edge of the
previous PWM signal. A blanking time (tS(MIN), 8.5s
typ.), which starts at the rising edge of the previous
PWM signal, limits minimum switching period. When
the tS(MIN) interval is on-going, all of valley signals are
not allowed to trigger the next PWM signal. After the
end of the tS(MIN) interval, the coming valley will trigger
the next PWM signal. If one or more valley signals are
detected during the tS(MIN) interval and no valley is
detected after the end of the tS(MIN) interval, the next
PWM signal will be triggered automatically at end of the
tS(MIN) + 5s (typ.).
is a registered trademark of Richtek Technology Corporation.
DS7310-00
October
2014
RT7310
～
～
LED short-circuit protection can be achieved by
～
～
LED Short-Circuit Protection
Valley
Signal
cycle-by-cycle current limitation, and it
auto-restarted when the output is recovered.
PWM
tSTART
When the output diode is damaged as short-circuit, the
transformer will be led to magnetic saturation and the
main switch will suffer from a high current stress. To
avoid the above situation, an output diode short-circuit
protection is built-in. When CS voltage VCS exceeds
the threshold (VCS_SD 1.5 typ.) of the output diode
short-circuit protection, RT7310 will shut down the
PWM
tS(MIN)
……
PWM output (GD pin) in few cycles to prevent the
converter from damage.
PWM
tS(MIN)
VDD Under-Voltage Lockout (UVLO) and
……
Valley
Signal
be
Output Diode Short-Circuit Protection
Valley
Signal
Valley
Signal
will
Over-Voltage Protection (VDD OVP)
RT7310 will be enabled when VDD voltage (VDD)
PWM
tS(MIN)
5µs
Figure 5. PWM Triggered Method
Protections
LED Open-Circuit Protection
In an event of output open circuit, the converter will be
shut down to prevent being damaged. Once the LED is
open-circuit, the output voltage and VZCD will rise.
When the sample-and-hold ZCD voltage (VZCD_SH)
exceeds its OV threshold (VZCD_OVP, 3.1V typ.), output
OVP will be activated and the PWM output (GD pin) will
be forced low to turn off the main switch.
exceeds rising UVLO threshold (VTH_ON, 16V typ.) and
disabled when VDD is lower than falling UVLO
threshold (VTH_OFF, 9V typ.).
When VDD exceeds its over-voltage threshold (VOVP,
27V typ.), the PWM output of RT7310 is shut down. It
will be auto-restarted when the VDD is recovered to a
normal level.
Over-Temperature Protection (OTP)
The RT7310 provides an internal OTP function to
protect the controller itself from suffering thermal stress
and permanent damage. It is not suggested to use the
function as precise control of over temperature. Once
the junction temperature is higher than the OTP
threshold (TSD, 150°C typ.), the controller will shut
down until the temperature cools down by 30°C (typ.).
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7310-00
October
2014
is a registered trademark of Richtek Technology Corporation.
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RT7310
Absolute Maximum Ratings
(Note 1)

VDD Supply Voltage, VDD ----------------------------------------------------------------------------------------- −0.3V to 30V

GD to GND Voltage, VGD ------------------------------------------------------------------------------------------ −0.3V to 20V

CS, ZCD, COMP to GND Voltage ------------------------------------------------------------------------------- −0.3V to 6V

Power Dissipation, PD @ TA = 25°C
SOT-23-6 -------------------------------------------------------------------------------------------------------------- 0.42W

Package Thermal Resistance
(Note 2)
SOT-23-6, JA-------------------------------------------------------------------------------------------------------- 235.6°C/W

Junction Temperature----------------------------------------------------------------------------------------------- 150°C

Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------ 260°C

Storage Temperature Range-------------------------------------------------------------------------------------- −65°C to 150°C

ESD Susceptibility
(Note 3)
Human Body Model ------------------------------------------------------------------------------------------------- 2kV
Machine Model ------------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 4)

Supply Input Voltage, VDD ----------------------------------------------------------------------------------------- 12V to 25V

COMP Voltage, VCOMP --------------------------------------------------------------------------------------------- 0.7V to 4.3V

Ambient Temperature Range ------------------------------------------------------------------------------------- −40°C to 85°C

Junction Temperature Range ------------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
(VDD = 15V, TA = 25°C, unless otherwise specification)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
25.5
27
28.5
V
--
10
--
s
VDD Supply Current and Protections Section
VDD OVP Threshold Voltage
VOVP
VDD OVP De-bounce Time
(Note 5)
Rising UVLO Threshold Voltage
VTH_ON
15
16
17
V
Falling UVLO Threshold Voltage
VTH_OFF
8
9
10
V
Operating Supply Current
IDD_OP
IZCD = 0, GD open
--
--
3.5
mA
VDD = VTH_ON  1V
--
--
50
A
IZCD = 0 to 2.5mA
--
0
0.3
V
2.8
3.1
3.4
V
0.245
0.25
0.255
V
4.5
--
--
V
--
62.5
--
A
Start-up Current
ZCD Section
Lower Clamp Voltage
ZCD OVP Threshold Voltage
VZCD_OVP
At the knee point
(Note 5)
Constant Current Control Section
Regulated factor for
Constant-Current Control
KCC
Maximum COMP Voltage
ICOMP < 30A
Maximum COMP Sourcing Current ICOMP(MAX) VCOMP < 3.5V
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is a registered trademark of Richtek Technology Corporation.
DS7310-00
October
2014
RT7310
Timing Control Section
Voltage Ramp Slope of the Ramp
Generator Output
Sramp
Minimum On-Time
tON(MIN)
Maximum On-Time
228
270
312
mV/s
2.2
2.7
3.2
s
tON(MAX)
--
65
--
s
Minimum Switching Period
tS(MIN)
7
8.5
10
s
Duration of Starter
tSTART
At no valley detected
--
75
--
s
tLEB
LEB + Propagation Delay
(Note 5)
240
400
570
ns
--
1.5
--
V
0.93
1.03
1.13
V
IZCD = 150A
Current Sense Section
Blanking Time
Output Diode Short-Circuit
V
Protection Voltage Threshold at CS CS_SD
CS Voltage Threshold for Peak
Current Limitation
VCS_CL
Propagation Delay Compensation
Factor
KPC
Sourcing ICS = IZCD x KPC,
IZCD = 150A
--
0.02
--
A/A
GD Voltage Rising Time
tR
CL = 1nF
--
60
80
ns
GD Voltage Falling Time
tF
CL = 1nF
--
40
70
ns
GD Output Clamping Voltage
VCLAMP
CL = 1nF
--
13
--
V
Internal GD Pull Low Resistor
RGD
--
40
--
k
Gate Driver Section
Over-Temperature Protection Section
Over-Temperature Threshold
TSD
(Note 5)
--
150
--
°C
Over-Temperature Threshold
Hysteresis
TSD_HYS
(Note 5)
--
30
--
°C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured in the natural convection at TA = 25C on a low effective two layer thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by Design.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7310-00
October
2014
is a registered trademark of Richtek Technology Corporation.
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RT7310
Typical Application Circuit
Flyback Application Circuit
RSN3 CSN2
F1
L1
Line
CX
CDMR
RDMR1
RST1
RSN1
CSN1
NP
NS
COUT
RSN2 DSN
Q2
CM
VOUT+
…
RDMR2
Neutral
DOUT
TX1
BD
VOUT-
DZ
RT7310
DST
RST2
GD
2
VDD
CS
CVDD
3
RG
Q1
RPC
4
CCS
6
CCOMP
COMP
GND
ZCD
5
RCS
1
RZCD2
NA
CZCD
RZCD1
DAUX
Buck-Boost Application Circuit
L1
BD
TX1
RDMR2
CX
Neutral
RDMR1
CDMR
RST1
N2
Q2
CM
VOUT-
RSN1
DZ
2
CVDD
VDD
RT7310
GD
CS
6
CCOMP
N1
RSN2 DSN
DST
RST2
DOUT
CSN1
3
RG
4
GND
VOUT+
RSN3 CSN2
Q1
RPC
CCS
COMP
COUT
…
F1
Line
RCS
1
ZCD
5
RZCD2
N3
CZCD
DAUX
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RZCD1
is a registered trademark of Richtek Technology Corporation.
DS7310-00
October
2014
RT7310
Typical Operating Characteristics
VTH_ON vs. Junction Temperature
VOVP vs. Junction Temperature
28.0
18.0
27.8
17.5
27.6
17.0
VTH_ON (V)
VOVP (V)
27.4
27.2
27.0
26.8
26.6
16.5
16.0
15.5
15.0
26.4
14.5
26.2
14.0
26.0
-50
-25
0
25
50
75
100
-50
125
-25
25
50
75
100
125
IDD_OP vs. Junction Temperature
VTH_OFF vs. Junction Temperature
11.0
3.00
10.5
2.75
10.0
2.50
I DD_OP (mA)
VTH_OFF (V)
0
Junction Temperature (°C)
Junction Temperature (°C)
9.5
9.0
8.5
2.25
2.00
1.75
8.0
1.50
7.5
1.25
1.00
7.0
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
Sramp vs. Junction Temperature
KCC vs. Junction Temperature
0.270
0.32
0.265
0.30
Sramp (V/μs)
KCC (V)
0.260
0.255
0.250
0.245
0.28
0.26
0.24
0.240
0.22
0.235
0.230
0.20
-50
-25
0
25
50
75
100
Junction Temperature (°C)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7310-00
October
2014
125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
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RT7310
Application Information
Output Current Setting
IZCD_SH can be expressed as :
Considering the conversion efficiency, the programmed
DC level of the average output current (IOUT(t)) can be
derived as:
IZCD_SH 
VIN  NA
RZCD1  NP
Thus, RZCD1 can be determined by:
tON(MIN)  VIN NA

405p
NP
IOUT_CC 
1 NP KCC


 CTRTX1
2 NS RCS
RZCD1 
CTRTX1 
ISEC_PK
In addition, the current flowing out of ZCD pin must be
lower than 2.5mA (typ.). Thus, the RZCD1 is also
determined by:
N
 S,
IPRI_PK NP
in which CTRTX1 is the current transfer ratio of the
transformer TX1, ISEC_PK is the peak current of the
secondary side, and IPRI_PK is the peak current of the
primary side. CTRTX1 can be estimated to be 0.9.
According to the above parameters, current sense
resistor RCS can be determined as the following
equation :
1 NP
KCC
RCS  

 CTRTX1
2 NS IOUT_CC
Propagation Delay Compensation Design
RZCD1 
 typ.
2  VAC(MAX) NA

2.5m
NP
where the VAC(MAX) is maximum input AC voltage.
Output Over-Voltage Protection Setting
Output OVP is achieved by sensing the knee voltage
on the auxiliary winging. It is recommended that output
OV level (VO_OVP) is set at 120% of nominal output
voltage (VO). Thus, RZCD1 and RZCD2 can be
determined by the equation as :
NA
RZCD2

 120%  3.1V (typ.)
NS RZCD1  RZCD2
The VCS deviation (VCS) caused by propagation delay
effect can be derived as:
VO 
V  t R
VCS  IN d CS ,
Lm
Thermal Considerations
in which td is the delay period which includes the
propagation delay of RT7310 and the turn-off transition
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
of the main MOSFET. The sourcing current from CS pin
of RT7310 (ICS) can be expressed as :
ICS  KPC  VIN 
NA
1

NP RZCD1
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature.
The maximum power dissipation can be calculated by
the following formula:
where NA is the turns number of auxiliary winding.
PD(MAX) = (TJ(MAX) − TA ) / θJA
RPC can be designed by :
Where TJ(MAX) is the maximum junction temperature,
TA is the ambient temperature, and θJA is the junction
to ambient thermal resistance.
RPC 
VCS t d  RCS  RZCD1 NP


ICS
Lm  KPC
NA
Minimum On-Time Setting
RT7310 limits a minimum on-time (tON(MIN)) for each
switching cycle. The tON(MIN) is a function of the
sample-and-hold ZCD current (IZCD_SH) as following :
tON(MIN)  IZCD_SH  405p  sec  A (typ.)
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For recommended operating condition specifications,
the maximum junction temperature is 125°C. The
junction to ambient thermal resistance, θJA, is layout
dependent. For SOT-23-6 packages, the thermal
resistance, θJA, is 235.6°C/W on a standard JEDEC
51-3 two-layer thermal test board. The maximum power
is a registered trademark of Richtek Technology Corporation.
DS7310-00
October
2014
RT7310
dissipation at TA = 25°C can be calculated by the
following formula :

PD(MAX) = (125°C − 25°C) / (235.6°C/W) = 0.42W for
MOSFET, RCS return to input capacitor is also a high
frequency current loop. They must be as short as
possible to decrease noise coupling and kept a
space to other low voltage traces, such as IC control
circuit paths, especially. Besides, the path(3)
between MOSFET ground(b) and IC ground(d) is
recommend to be as short as possible, too.
SOT-23-6 package
The maximum power dissipation depends on the
operating ambient temperature for fixed TJ(MAX) and
thermal resistance, θJA. The derating curve in Figure 6
allows the designer to see the effect of rising ambient
temperature on the maximum power dissipation.
0.6
Maximum Power Dissipation (W)1
The current path(1) from input capacitor, transformer,
MOSFET, RCS return to input capacitor is a high
frequency current loop. The path(2) from GD pin,
Two-Layer PCB

The path(4) from RCD snubber circuit to MOSFET is
a high switching loop. Keep it as small as possible.

It is good for reducing noise, output ripple and EMI
0.5
0.4
issue to separate ground traces of input capacitor(a),
MOSFET(b), auxiliary winding(c) and IC control
circuit(d). Finally, connect them together on input
capacitor ground(a). The areas of these ground
traces should be kept large.
0.3
0.2
0.1

highly recommended. The capacitors CCOMP, CZCD,
and CCS should be placed as close to controller as
possible.
0.0
0
25
50
75
100
Placing bypass capacitor for abating noise on IC is
125
Ambient Temperature (°C)

Figure 6. Derating Curve of Maximum Power
Dissipation
Layout Considerations
A proper PCB layout can abate unknown noise
interference and EMI issue in the switching power
supply. Please refer to the guidelines when designing a
PCB layout for switching power supply :
To minimize parasitic trace inductance and EMI,
minimize the area of the loop connecting the
secondary winding, the output diode, and the output
filter capacitor. In addition, apply sufficient copper
area at the anode and cathode terminal of the diode
for heat-sinking. It is recommended to apply a larger
area at the quiet cathode terminal. A large anode
area will induce high-frequency radiated EMI.
VOUT+
…
Line
(4)
VOUTNeutral
RT7310
(a)
CCOMP
COMP
GD
VDD
CS
CCS (2)
(3)
(1)
Input capacitor
Ground (a)
(b)
GND
ZCD
(d)
(c)
Trace
IC
Ground (d)
CZCD
Trace
Trace
Auxiliary
MOSFET
Ground (c) Ground (b)
Figure 7. PCB Layout Guide
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7310-00
October
2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT7310
Outline Dimension
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.889
1.295
0.031
0.051
A1
0.000
0.152
0.000
0.006
B
1.397
1.803
0.055
0.071
b
0.250
0.560
0.010
0.022
C
2.591
2.997
0.102
0.118
D
2.692
3.099
0.106
0.122
e
0.838
1.041
0.033
0.041
H
0.080
0.254
0.003
0.010
L
0.300
0.610
0.012
0.024
SOT-23-6 Surface Mount Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
is a registered trademark of Richtek Technology Corporation.
DS7310-00
October
2014