INTERSIL ISL6269ACRZ

ISL6269A
®
Data Sheet
August 7, 2006
High-Performance Notebook PWM
Controller
Features
• High performance R3 technology
The ISL6269A IC is a Single-Phase Synchronous-Buck
PWM controller featuring Intersil's Robust Ripple Regulator
(R3) technology that delivers truly superior dynamic
response to input voltage and output load transients.
Integrated MOSFET drivers and bootstrap diode result in
fewer components and smaller implementation area.
Intersil’s R3 technology combines the best features of fixedfrequency PWM and hysteretic PWM while eliminating many
of their shortcomings. R3 technology employs an innovative
modulator that synthesizes an AC ripple voltage signal VR,
analogous to the output inductor ripple current. The AC
signal VR enters a window comparator where the lower
threshold is the error amplifier output VCOMP, and the upper
threshold is a programmable voltage reference VW, resulting
in generation of the PWM signal. The voltage reference VW
sets the steady-state PWM frequency. Both edges of the
PWM can be modulated in response to input voltage
transients and output load transients, much faster than
conventional fixed-frequency PWM controllers. Unlike a
conventional hysteretic converter, the ISL6269A has an error
amplifier that provides ±1% voltage regulation at the FB pin.
The ISL6269A has a 1.5ms digital soft-start and can be
started into a pre-biased output voltage. A resistor divider is
used to program the output voltage setpoint. The ISL6269A
can be configured to operate in continuous-conductionmode (CCM) or diode-emulation-mode (DEM), which
improves light-load efficiency. In CCM the controller always
operates as a synchronous rectifier however, when DEM is
enabled the low-side MOSFET is permitted to stay off,
blocking negative current flow into the low-side MOSFET
from the output inductor.
Pinout
PGOOD
PHASE
UG
BOOT
16
15
14
13
12 PVCC
VCC
2
FCCM
3
10 PGND
EN
4
9
11 LG
1
FB
8
VO
COMP
7
FSET
6
• Wide input voltage range: +7.0V to +25.0V
• Output voltage range: +0.6V to +3.3V
• Wide output load range: 0A to 25A
• Selectable diode emulation mode for increased light load
efficiency
• Programmable PWM frequency: 200kHz to 600kHz
• Pre-biased output start-up capability
• Integrated MOSFET drivers and bootstrap diode
• Internal digital soft-start
• Power good monitor
• Fault protection
- Undervoltage protection
- Soft crowbar overvoltage protection
- Low-side MOSFET rDS(on) overcurrent protection
- Over-temperature protection
- Fault identification by PGOOD pull down resistance
Applications
• PCI express graphical processing unit
• Auxiliary power rail
• VRM
• Network adapter
Ordering Information
PACKAGE
ISEN
PKG.
DWG. #
6269ACRZ -10 to +100 16 Ld 4x4 QFN L16.4x4
(Pb-Free)
ISL6269ACRZ-T 6269ACRZ 16 Ld 4x4 QFN Tape and
(See Note)
Reel (Pb-Free)
1
5
• ±1% regulation accuracy: -10°C to +100°C
ISL6269ACRZ
(See Note)
VIN
GND
• Fast transient response
PART
PART NUMBER MARKING TEMP (°C)
ISL6269A (4x4 QFN)
TOP VIEW
FN9253.1
L16.4x4
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Block Diagram
VIN
VO
GND
PACKAGE BOTTOM
PWM FREQUENCY
CONTROL
+
VREF
VW
−
2
+
−
gmVIN
EN
−
FSET
−
VCC
+
R
PWM
Q
OVP
+
gmVO
+
−
−
UVP
CR
VCOMP
+
S
+
BOOT
+
EA
DRIVER
−
POR
DIGITAL SOFT-START
PWM CONTROL
FB
COMP
−
ISEN
OCP
+
IOC
30Ω
90Ω
UG
60Ω
PHASE
SHOOT THROUGH
PROTECTION
PVCC
DRIVER
LG
150°OT
PGND
PGOOD
FCCM
FN9253.1
August 7, 2006
FIGURE 1. SCHEMATIC BLOCK DIAGRAM
ISL6269A
−
VR
−
+
ISL6269A
Typical Application
ISL6269A
VIN
7V-25V
PGOOD
VIN
CIN
RPGOOD
QHIGH_SIDE
5V
PVCC
UG
RVCC
VCC
BOOT
CVCC
CPVCC
CBOOT
GND
VOUT
LOUT
0.6V-3.3V
PHASE
COUT
RSEN
FCCM
ISEN
QLOW_SIDE
EN
LG
RCOMP
COMP
PGND
CCOMP1
FB
VO
CCOMP2
FSET
RFSET
RBOTTOM
3
CFSET
RTOP
FN9253.1
August 7, 2006
ISL6269A
Absolute Voltage Ratings
Thermal Information
ISEN, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VCC, PGOOD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN, FCCM . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +3.3V
PHASE to GND (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
(<100ns Pulse Width, 10µJ) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0V
BOOT to GND, or PGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
UG (DC) . . . . . . . . . . . . . . . . . . . . . . .-0.3V to PHASE, BOOT +0.3V
(<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . . -4.0V
LG (DC) . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to PGND, PVCC +0.3V
(<100ns Pulse Width, 4µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
43
11.5
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -10°C to 100°C
Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . . . 7V to 25V
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a highly effective thermal conductivity test board on free air. See Tech Brief TB379 for details.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
These specifications apply for VIN = 15V, TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V, PVCC = 5V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN = 5V, VIN = 7V
-
6.5
10
µA
EN = 5V, VIN = 25V
-
26
35
µA
EN = GND, VIN = 25V
-
0.1
1.0
µA
EN = 5V, FCCM = GND, FB = 0.65V, VIN = 7V to 25V
-
1.7
2.5
mA
EN = GND, VCC = 5V
-
0.1
1.0
µA
-
0.1
1.0
µA
VIN
IVIN
VIN Input Bias Current
VIN Shutdown Current
IVIN_SHDN
VCC and PVCC
VCC Input Bias Current
IVCC
VCC Shutdown Current
IVCC_SHDN
PVCC Shutdown Current
IPVCC_SHDN EN = GND, PVCC = 5V
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage
VVCC_THR
4.35
4.45
4.55
V
Falling VCC POR Threshold Voltage
V
4.10
4.20
4.30
V
-
0.6
-
V
-1
-
+1
%
VCC_THF
REGULATION
Reference Voltage
VREF
Regulation Accuracy
FB connected to COMP
PWM
Frequency Range
FSW
Frequency-Set Accuracy
VO Range
FCCM = 5V
200
-
600
kHz
FSW = 300kHz
-12
-
+12
%
0.60
-
3.30
V
VO = 0.60V
-
1.3
-
µA
VO = 3.30V
-
7.0
-
µA
FB = 0.60V
-0.5
-
+0.5
µA
-
2.5
-
mA
VVO
IVO
VO Input Leakage
ERROR AMPLIFIER
FB Input Bias Current
IFB
COMP Source Current
ICOMP_SRC FB = 0.40V, COMP = 3.20V
COMP Sink Current
ICOMP_SNK
FB = 0.80V, COMP = 0.30V
-
0.3
-
mA
COMP High Clamp Voltage
VCOMP_HC
FB = 0.40V, Sink 50µA
3.10
3.40
3.65
V
COMP Low Clamp Voltage
VCOMP_LC
FB = 0.80V, Source 50µA
0.09
0.15
0.21
V
4
FN9253.1
August 7, 2006
ISL6269A
Electrical Specifications
These specifications apply for VIN = 15V, TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V, PVCC = 5V (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PGOOD = 5mA Sink
80
95
133
Ω
RPG_OV
PGOOD = 5mA Sink
53
63
89
Ω
RPG_OC
PGOOD = 5mA Sink
26
32
46
Ω
IPGOOD
PGOOD = 5V
POWER GOOD
RPG_SS
RPG_UV
PGOOD Pull Down Impedance
PGOOD Leakage Current
PGOOD Maximum Sink Current (Note 3)
PGOOD Soft-Start Delay
TSS
EN High to PGOOD High
-
0.1
1.0
µA
-
5.0
-
mA
2.20
2.75
3.30
ms
GATE DRIVER
UG Pull-Up Resistance
RUGPU
200mA Source Current
-
1.0
1.5
Ω
UG Source Current (Note 3)
IUGSRC
UG - PHASE = 2.5V
-
2.0
-
A
UG Sink Resistance
RUGPD
250mA Sink Current
-
1.0
1.5
Ω
UG Sink Current (Note 3)
IUGSNK
UG - PHASE = 2.5V
-
2.0
-
A
LG Pull-Up Resistance
RLGPU
250mA Source Current
-
1.0
1.5
Ω
LG Source Current (Note 3)
ILGSRC
LG - PGND = 2.5V
-
2.0
-
A
LG Sink Resistance
RLGPD
250mA Sink Current
-
0.5
0.9
Ω
LG Sink Current (Note 3)
ILGSNK
LG - PGND = 2.5V
-
4.0
-
A
UG to LG Deadtime
tUGFLGR
UG falling to LG rising, no load
-
21
-
ns
LG to UG Deadtime
tLGFUGR
LG falling to UG rising, no load
-
14
-
ns
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 2mA
-
0.58
-
V
Reverse Leakage
IR
VR = 25V
-
0.2
-
µA
CONTROL INPUTS
EN High Threshold
VENTHR
2.0
-
-
V
EN Low Threshold
VENTHF
-
-
1.0
V
FCCM High Threshold
VFCCMTHR
2.0
-
-
V
FCCM Low Threshold
VFCCMTHF
-
-
1.0
V
EN Leakage
IENL
EN = 0V
-
0.1
1.0
µA
IENH
EN = 5.0V
-
0.1
1.0
µA
IFCCML
FCCM = 0V
-
0.1
1.0
µA
IFCCMH
FCCM = 5.0V
-
2.0
-
µA
IOC
ISEN sourcing
19
26
33
µA
ISEN Short-Circuit Threshold
ISC
ISEN sourcing
-
50
-
µA
UVP Threshold
VUV
81
84
87
%
OVP Rising Threshold
VOVR
113
116
119
%
OVP Falling Threshold
VOVF
100
103
106
%
TOTR
-
150
-
°C
TOTHYS
-
25
-
°C
FCCM Leakage
PROTECTION
ISEN OCP Threshold
OTP Rising Threshold (Note 3)
OTP Hysteresis (Note 3)
NOTE:
3. Guaranteed by characterization.
5
FN9253.1
August 7, 2006
ISL6269A
Functional Pin Descriptions
GND (Bottom Pad)
Signal common of the IC. Unless otherwise stated, signals
are referenced to the GND pin, not the PGND pin.
VIN (Pin 1)
The VIN pin measures the converter input voltage which is a
required input to the R3 PWM modulator. Connect across
the drain of the high-side MOSFET to the GND pin.
VCC (Pin 2)
The VCC pin is the input bias voltage for the IC. Connect
+5V from the VCC pin to the GND pin. Decouple with at least
1µF of a MLCC capacitor from the VCC pin to the GND pin.
FCCM (Pin 3)
The FCCM pin configures the controller to operate in forcedcontinuous-conduction-mode (FCCM) or diode-emulationmode (DEM.) DEM is disabled when the FCCM pin is pulled
above the rising threshold voltage VFCCMTHR, conversely
DEM is enabled when the FCCM pin is pulled below the
falling threshold voltage VFCCMTHF.
EN (Pin 4)
The EN pin is the on/off switch of the IC. The soft-start
sequence begins when the EN pin is pulled above the rising
threshold voltage VENTHR and VCC is above the power-on
reset (POR) rising threshold voltage VVCC_THR . When the
EN pin is pulled below the falling threshold voltage VENTHF
PWM immediately stops.
COMP (Pin 5)
The COMP pin is the output of the control-loop error
amplifier. Compensation components for the control-loop
connect across the COMP and FB pins.
FB (Pin 6)
The FB pin is the inverting input of the control-loop error
amplifier. The converter output voltage regulates to 600mV
from the FB pin to the GND pin. Program the desired output
voltage with a resistor network connected across the VO,
FB, and GND pins. Select the resistor values such that FB to
GND is 600mV when the converter output voltage is at the
programmed regulation value.
FSET (Pin 7)
The FSET pin programs the PWM switching frequency.
Program the desired PWM frequency with a resistor and a
capacitor connected across the FSET and GND pins.
ISEN (Pin 9)
The ISEN pin programs the threshold of the OCP
overcurrent fault protection. Program the desired OCP
threshold with a resistor connected across the ISEN and
PHASE pins. The OCP threshold is programmed to detect
the peak current of the output inductor. The peak current is
the sum of the DC and AC components of the inductor
current.
PGND (Pin 10)
The PGND pin conducts the turn-off transient current
through the LG gate driver. The PGND pin must be
connected to complete the pulldown circuit of the LG gate
driver. The PGND pin should be connected to the source of
the low-side MOSFET through a low impedance path,
preferably in parallel with the trace connecting the LG pin to
the gate of the low-side MOSFET. The adaptive shootthrough protection circuit, measures the low-side MOSFET
gate-source voltage from the LG pin to the PGND pin.
LG (Pin 11)
The LG pin is the output of the low-side MOSFET gate
driver. Connect to the gate of the low-side MOSFET.
PVCC (Pin 12)
The PVCC pin is the input voltage bias for the LG low-side
MOSFET gate driver. Connect +5V from the PVCC pin to the
PGND pin. Decouple with at least 1µF of an MLCC capacitor
across the PVCC and PGND pins.
BOOT (Pin 13)
The BOOT pin stores the input voltage for the UG high-side
MOSFET gate driver. Connect an MLCC capacitor across
the BOOT and PHASE pins. The boot capacitor is charged
through an internal boot diode connected from the PVCC pin
to the BOOT pin, each time the PHASE pin drops below
PVCC minus the voltage dropped across the internal boot
diode.
UG (Pin 14)
The UG pin is the output of the high-side MOSFET gate
driver. Connect to the gate of the high-side MOSFET.
PHASE (Pin 15)
The PHASE pin detects the voltage polarity of the PHASE
node and is also the current return path for the UG high-side
MOSFET gate driver. Connect the PHASE pin to the node
consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor.
PGOOD (Pin 16)
VO (Pin 8)
The VO pin measures the converter output voltage and is
used exclusively as an input to the R3 PWM modulator.
Connect at the physical location where the best output
voltage regulation is desired.
6
The PGOOD pin is an open-drain output that indicates when
the converter is able to supply regulated voltage. Connect
the PGOOD pin to +5V through a pull-up resistor.
FN9253.1
August 7, 2006
ISL6269A
Theory of Operation
Power-On Reset
Modulator
The ISL6269A is a hybrid of fixed frequency PWM control,
and variable frequency hysteretic control. Intersil’s R3
technology can simultaneously affect the PWM switching
frequency and PWM duty cycle in response to input voltage
and output load transients. The term “Ripple” in the name
“Robust-Ripple-Regulator” refers to the converter output
inductor ripple current, not the converter output ripple
voltage. The R3 modulator synthesizes an AC signal VR,
which is an ideal representation of the output inductor ripple
current. The duty-cycle of VR is the result of charge and
discharge current through a ripple capacitor CR. The current
through CR is provided by a transconductance amplifier gm
that measures the VIN and VO pin voltages. The positive
slope of VR can be written as:
V RPOS = ( g m ) • ( V IN – V OUT )
(EQ. 1)
The negative slope of VR can be written as:
V RNEG = g m ⋅ V OUT
The ISL6269A is disabled until the voltage at the VCC pin
has increased above the rising power-on reset (POR) VCCR
threshold voltage. The controller will become once again
disabled when the voltage at the VCC pin decreases below
the falling POR VCCF threshold voltage.
EN, Soft-Start, and PGOOD
The ISL6269A uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the softstart sequence has been selected to limit the inrush current
through the output capacitors as they charge to the desired
regulation voltage. When the EN pin is pulled above the rising
EN threshold voltage VENTHR the PGOOD Soft-Start Delay
TSS begins and the output voltage begins to rise. The output
voltage enters regulation in approximately 1.5ms and the
PGOOD pin goes to high impedance once TSS has elapsed.
1.5ms
VOUT
(EQ. 2)
VCC and PVCC
Where:
- gm is the gain of the transconductance amplifier
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of
VW is set by a resistor connected across the FSET and GND
pins. The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold voltage
and VW is the higher threshold voltage. Figure 2 shows
PWM pulses being generated as VR traverses the VW and
VCOMP thresholds . The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of VR; the PWM switching frequency is inversely
proportional to the voltage between VW and VCOMP.
Ripple Capacitor Voltage CR
Window Voltage VW
Error Amplifier Voltage VCOMP
EN
PGOOD
2.75ms
FIGURE 3. SOFT-START SEQUENCE
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if VCC has not reached the rising POR
threshold VCCR, or if VCC is below the falling POR threshold
VCCF. The ISL6269A features a unique fault-identification
capability that can drastically reduce trouble-shooting time
and effort. The pull-down resistance of the PGOOD pin
corresponds to the fault status of the controller. During softstart or if an undervoltage fault occurs, the PGOOD pulldown
resistance is 95Ω, or 30Ω for an overcurrent fault, or 60Ω for
an overvoltage fault.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
PGOOD RESISTANCE
VCC Below POR
Undefined
Soft Start or Undervoltage
95Ω
Overvoltage
60Ω
Overcurrent
30Ω
PWM
FIGURE 2. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
7
FN9253.1
August 7, 2006
ISL6269A
MOSFET Gate-Drive Outputs LG and UG
The ISL6269A has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The LG gate-driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant, requiring a low
rDS(on) MOSFET. The LG pulldown resistance is small in
order to clamp the gate of the MOSFET below the VGS(th) at
turnoff. The current transient through the gate at turnoff can
be considerable because the switching charge of a low
rDS(on) MOSFET can be large. Adaptive shoot-through
protection prevents a gate-driver output from turning on until
the opposite gate-driver output has fallen below
approximately 1V. The dead-time shown in Figure 4. begins
only after the adaptive shoot-through protection has granted
permission for the driver to go high. The high-side gatedriver output voltage is measured across the UG and
PHASE pins while the low-side gate-driver output voltage is
measured across the LG and PGND pins. The power for the
LG gate-driver is sourced directly from the PVCC pin. The
power for the UG gate-driver is sourced from a “boot”
capacitor connected across the BOOT and PHASE pins.
The boot capacitor is charged from a 5V bias supply through
a “boot diode” each time the low-side MOSFET turns on,
pulling the PHASE pin low. The ISL6269A has an integrated
boot diode connected from the PVCC pin to the BOOT pin.
tLGFUGR
tUGFLGR
UG
LG
FIGURE 4. LG AND UG DEAD-TIME
Diode Emulation
The ISL6269A can be configured to operate in continuousconduction-mode (CCM) or diode-emulation-mode (DEM),
which can improve light-load efficiency by allowing the
low-side MOSFET to block negative inductor current flow.
DEM is permitted when the FCCM pin is pulled low, and is
disabled when pulled high.
Positive-going inductor current flows from either the source
of the high-side MOSFET, or the drain of the low-side
MOSFET. Negative-going inductor current flows into the
8
source of the high-side MOSFET, or the drain of the low-side
MOSFET. When the low-side MOSFET conducts positive
inductor current, the phase voltage will be negative with
respect to the GND pin. Conversely, when the low-side
MOSFET conducts negative inductor current, the phase
voltage will be positive with respect to the GND pin. Negative
inductor current occurs in CCM when the output load current
is less than ½ the inductor ripple current. Sinking negative
inductor through the low-side MOSFET lowers efficiency
through conduction losses. While in DEM the PWM
switching frequency is automatically shifted downward by an
increase of the window voltage VW. The PWM switching
frequency will continue to decrease as the load continues to
decrease. The reduction of PWM frequency further improves
efficiency by reducing switching losses. With FCCM pulled
low, the converter will automatically enter DEM after the
PHASE pin has detected positive voltage, while the LG
gate-driver pin is high, for eight consecutive PWM pulses.
The converter will return to CCM on the following cycle after
the PHASE pin detects negative voltage, indicating that the
body diode of the MOSFET is conducting positive inductor
current.
Overcurrent and Short-Circuit Protection
The overcurrent protection (OCP) and short circuit protection
(SCP) setpoint is programmed with resistor RSEN that is
connected across the ISEN and PHASE pins. The PHASE
pin is connected to the drain terminal of the low-side
MOSFET.
The SCP setpoint is internally set to twice the OCP setpoint.
When an OCP or SCP fault is detected, the PGOOD pin will
pulldown to 30Ω and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage VENTHF or if VCC has decayed
below the falling POR threshold voltage VVCC_THF.
The OCP circuit does not directly detect the DC load current
leaving the converter. The OCP circuit detects the peak of
positive-flowing output inductor current. The low-side
MOSFET drain current ID is assumed to be equal to the
positive output inductor current when the high-side MOSFET
is off. The inductor current develops a negative voltage
across the rDS(on) of the low-side MOSFET that is measured
shortly after the LG gate-driver output goes high. The ISEN
pin sources the OCP sense current ISEN, through the OCP
programming resistor RSEN, forcing the ISEN pin to zero
volts with respect to the GND pin. The negative voltage
across the PHASE and GND pins is nulled by the voltage
dropped across RSEN as ISEN conducts through it. An OCP
fault occurs if ISEN rises above the OCP threshold current
IOC while attempting to null the negative voltage across the
PHASE and GND pins. ISEN must exceed IOC on all the
PWM pulses that occur within 20µs. If ISEN falls below IOC
on a PWM pulse before 20µs has elapsed, the timer will be
reset. An SCP fault will occur within 10µs when ISEN
FN9253.1
August 7, 2006
ISL6269A
exceeds twice IOC. The relationship between ID and ISEN is
written as:
(EQ. 3)
I SEN • R SEN = I D • r DS ( on )
The value of RSEN is then written as:
I PP
⎛ I + --------⎞ • OC SP • r DS ( on )
⎝ FL
2 ⎠
R SEN = -------------------------------------------------------------------------I OC
(EQ. 4)
V
VCC_THF. All other protection circuits function normally
during OTP. It is likely that the IC will detect an UVP fault
because in the absence of PWM, the output voltage
immediately decays below the undervoltage threshold VUV;
the PGOOD pin will pulldown to 95Ω and latch-off the
converter. The UVP fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
VENTHF or if VCC has decayed below the falling POR
threshold voltage VVCC_THF.
Programming the Output Voltage
Where:
- RSEN (Ω) is the resistor used to program the
overcurrent setpoint
- ISEN is the current sense current that is sourced from
the ISEN pin
- IOC is the ISEN threshold current sourced from the ISEN
pin that will activate the OCP circuit
- IFL is the maximum continuous DC load current
- IPP is the inductor peak-to-peak ripple current
- OCSP is the desired overcurrent setpoint expressed as
a multiplier relative to IFL
Overvoltage Protection
When an OVP fault is detected, the PGOOD pin will pull
down to 60Ω and latch-off the converter. The OVP fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage VENTHF or if VCC has decayed
below the falling POR threshold voltage VVCC_THF.
The OVP fault detection circuit triggers after the voltage
across the FB and GND pins has increased above the rising
overvoltage threshold VOVR. Although the converter has
latched-off in response to an OVP fault, the LG gate-driver
output will retain the ability to toggle the low-side MOSFET
on and off, in response to the output voltage transversing the
VOVR and VOVF thresholds.
Undervoltage Protection
When a UVP fault is detected, the PGOOD pin will pull down
to 95Ω and latch-off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage VENTHF or if VCC has decayed below the
falling POR threshold voltage VVCC_THF. The UVP fault
detection circuit triggers after the voltage across the FB and
GND pins has fallen below the undervoltage threshold VUV.
Over-Temperature
When the temperature of the ISL6269A increases above the
rising threshold temperature TOTR, the IC will enter an OTP
state that suspends the PWM , forcing the LG and UG
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature TOTHYS at which time normal PWM
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage VENTHF or if
VCC decays below the falling POR threshold voltage
9
When the converter is in regulation there will be 600mV from
the FB pin to the GND pin. Connect a two-resistor voltage
divider across the VO pin and the GND pin with the output
node connected to the FB pin. Scale the voltage-divider
network such that the FB pin is 600mV with respect to the
GND pin when the converter is regulating at the desired
output voltage. The output voltage can be programmed from
600mV to 3.3V.
Programming the output voltage is written as:
R BOTTOM
V REF = V OUT • -------------------------------------------------R TOP + R BOTTOM
(EQ. 5)
Where:
- VOUT is the desired output voltage of the converter
- VREF is the voltage that the converter regulates to
between the FB pin and the GND pin
- RTOP is the voltage-programming resistor that connects
from the FB pin to the VO pin. In addition to setting the
output voltage, this resistor is part of the loop
compensation network
- RBOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Beginning with RTOP between 1kΩ to 5kΩ, calculating
RBOTTOM is written as:
V REF • R
TOP
R BOTTOM = -----------------------------------V OUT – V REF
(EQ. 6)
Programming the PWM Switching Frequency
The ISL6269A does not use a clock signal to produce PWM.
The PWM switching frequency FSW is programmed by the
resistor RFSET that is connected from the FSET pin to the
GND pin. The approximate PWM switching frequency is
written as:
1
F SW = --------------------------K ⋅ R FSET
(EQ. 7)
Estimating the value of RFSET is written as:
1
R FSET = -------------------K • F SW
(EQ. 8)
Where:
- FSW is the PWM switching frequency
- RFSET is the FSW programming resistor
- K =75 x 10-12
FN9253.1
August 7, 2006
ISL6269A
It is recommended that whenever the control loop
compensation network is modified, FSW should be checked
for the correct frequency and if necessary, adjust RFSET.
Compensation Design
The LC output filter has a double pole at its resonant frequency
that causes the phase to abruptly roll downward. The R3
modulator used in the ISL6269A makes the LC output filter
resemble a first order system in which the closed loop stability
can be achieved with a Type II compensation network.
R2
C1
C2
error amplifier of the ISL6269A and the external components
R1, R2, C1, and C2 as well as the frequency setting
components RFSET, and CFSET, are identified in the
schematic Figure 5.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as:
R1
COMP
-
FB
V OUT
D = --------------V IN
EA
+
(EQ. 9)
The output inductor peak-to-peak ripple current is written as:
V OUT • ( 1 – D )
I PP = ------------------------------------F SW • L OUT
REF
FSET
RFSET
CFSET
R3 Modulator
A typical step-down DC/DC converter will have an IPP of
20% to 40% of the maximum DC output load current. The
value of IPP is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by:
P COPPER = I LOAD
VO
VOUT
VIN
DCR
(EQ. 11)
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components, as well as nuisance OCP
faults.
QHIGH_SIDE
PHASE
DCR
Gate Drivers
COUT
LG
CESR
GND
•
- ILOAD is the converter output DC current
UG
QLOW_SIDE
2
Where:
VIN
LOUT
(EQ. 10)
ISL6269A
A DC/DC buck regulator must have output capacitance
COUT into which ripple current IPP can flow. Current IPP
develops a corresponding ripple voltage VPP across COUT,
which is the sum of the voltage drop across the capacitor
ESR and of the voltage change stemming from charge
moved in and out of the capacitor. These two voltages are
written as:
∆V ESR = I PP • E SR
(EQ. 12)
and
FIGURE 5. COMPENSATION REFERENCE CIRCUIT
Your local Intersil representative can provide a PC-based
tool that can be used to calculate compensation network
component values and help simulate the loop frequency
response. The compensation network consists of the internal
10
I PP
∆V C = -------------------------------------8 • C OUT • F
(EQ. 13)
SW
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required VPP is achieved.
FN9253.1
August 7, 2006
ISL6269A
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors constructed with reverse package
geometry are available. A capacitor dissipates heat as a
function of RMS current and frequency. Be sure that IPP is
shared by a sufficient quantity of paralleled capacitors so that
they operate below the maximum rated RMS current at FSW.
Take into account that the rated value of a capacitor can fade
as much as 50% as the DC voltage across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 6 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as:
2
2 D
2
( I MAX ⋅ ( D – D ) ) + ⎛ x ⋅ I MAX ⋅ ------ ⎞
⎝
12 ⎠
I IN_RMS = ----------------------------------------------------------------------------------------------------I MAX
(EQ. 14)
- IMAX is the maximum continuous ILOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as:
V OUT
D = ------------------------V IN ⋅ EFF
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn off, the high-side MOSFET turns off with
VIN-VOUT across it. The preferred low-side MOSFET
emphasizes low rDS(on) when fully saturated to minimize
conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as:
2
P CON_LS ≈ I LOAD ⋅ r DS ( on )_LS • ( 1 – D )
(EQ. 15)
For the high-side MOSFET, (HS), its conduction loss is
written as:
2
•
r DS ( on )_HS • D
(EQ. 16)
For the high-side MOSFET, its switching loss is written as:
V IN • I VALLEY • T ON • F
V IN • I PEAK • T OFF • F
SW
SW
- + ---------------------------------------------------------------P SW_HS = -------------------------------------------------------------------2
2
(EQ. 17)
Where:
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
NORMALIZED INPUT RMS RIPPLE CURRENT
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum VDS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
P CON_HS = I LOAD
Where:
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
MOSFET Selection and Considerations
- IVALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- IPEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- TON is the time required to drive the device into
saturation
- TOFF is the time required to drive the device into cutoff
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
Qg
C BOOT = ----------------------∆V BOOT
x=1
x = 0.75
x = 0.50
x = 0.25
x=0
0
0.1
0.2
0.3
0.4
0.5
(EQ. 18)
Where:
0.6
0.7
0.8
0.9
1
DUTY CYCLE
- Qg is the total gate charge required to turn on the
high-side MOSFET
- ∆VBOOT, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
FIGURE 6. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
11
FN9253.1
August 7, 2006
ISL6269A
As an example, suppose the high-side MOSFET has a total
gate charge Qg, of 25nC at VGS = 5V, and a ∆VBOOT of
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin select a capacitor that is double the
calculated capacitance, in this example 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
GND
VOUT
INDUCTOR
HIGH-SIDE
MOSFETS
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
PHASE
NODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
VIN
For best performance, place the decoupling capacitor very
close to the PVCC and PGND pins, preferably on the same
side of the PCB as the ISL6269A IC.
FCCM (Pin 3), EN (Pin 4), and PGOOD (Pin 16)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
Layout Considerations
VIAS TO
GROUND
PLANE
PVCC (Pin 12)
FIGURE 7. TYPICAL POWER COMPONENT PLACEMENT
Signal Ground and Power Ground
The bottom of the ISL6269A QFN package is the signal
ground (GND) terminal for analog and logic signals of the IC.
Connect the GND pad of the ISL6269A to the island of
ground plane under the top layer using several vias, for a
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground plane.
COMP (Pin 5), FB (Pin 6), and VO (Pin 8)
For best results, use an isolated sense line from the output
load to the VO pin. The input impedance of the FB pin is
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND
pins keeping the high impedance trace short.
FSET (Pin 7)
This pin requires a quiet environment. The resistor RFSET
and capacitor CFSET should be placed directly adjacent to
this pin. Keep fast moving nodes away from this pin.
ISEN (Pin 9)
Route the connection to the ISEN pin away from the traces
and components connected to the FB pin, COMP pin, and
FSET pin.
LG (Pin 11)
The signal going through this trace is both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the PGND pin.
These two traces should be short, wide, and away from
other traces. There should be no other weak signal traces in
proximity with these traces on any layer.
BOOT (Pin 13), UG (Pin 14), and PHASE (Pin 15)
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UG and PHASE pins in parallel with short
and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
PGND (Pin 10)
Copper Size for the Phase Node
This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to
the source of the low-side MOSFET with a low-resistance,
low-inductance path .
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
VIN (Pin 1)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pin 2)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
12
FN9253.1
August 7, 2006
ISL6269A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.23
D
0.28
9
0.35
5, 8
4.00 BSC
D1
D2
9
0.20 REF
-
3.75 BSC
1.95
2.10
9
2.25
7, 8
E
4.00 BSC
-
E1
3.75 BSC
9
E2
1.95
e
2.10
2.25
7, 8
0.65 BSC
-
k
0.25
-
-
-
L
0.50
0.60
0.75
8
L1
-
-
0.15
10
N
16
2
Nd
4
3
Ne
4
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerances conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN9253.1
August 7, 2006