M
HCS515
Code Hopping Decoder
FEATURES
PACKAGE TYPE
PDIP, SOIC
Security
•
•
•
•
•
Encrypted storage of manufacturer’s code
Encrypted storage of encoder decryption keys
Up to seven transmitters can be learned
KEELOQ code hopping technology
Normal and secure learning mechanisms
1
14
NC
NC
2
13
NC
Vdd
3
12
Vss
Operating
S0
4
11
RF_IN
• 3.0V—5.5V operation
• Internal oscillator
• Auto bit rate detection
S1
5
10
S_CLK
MCLR
6
9
S_DAT
NC
7
8
NC
Other
•
•
•
•
•
Stand-alone decoder
Internal EEPROM for transmitter storage
Synchronous serial interface
1 Kbit user EEPROM
14-pin DIP/SOIC package
HCS515
NC
BLOCK DIAGRAM
RFIN
67-bit Reception Register
Typical Applications
•
•
•
•
•
•
•
DECRYPTOR
Automotive remote entry systems
Automotive alarm systems
Automotive immobilizers
Gate and garage openers
Electronic door locks
Identity tokens
Burglar alarm systems
EE_DAT
Internal
EEPROM
S_DAT
S_CLK
S0
S1
MCLR
CONTROL
EE_CLK
OSCILLATOR
Compatible Encoders
• HCS200, HCS300, HCS301, HCS360, HCS361,
HCS410 (PWM Mode)
DESCRIPTION
The Microchip Technology Inc. HCS515 is a code hopping decoder designed for secure Remote Keyless
Entry (RKE) systems. The HCS515 utilizes the patented KEELOQ code hopping system and high security
learning mechanisms to make this a canned solution
when used with the HCS encoders to implement a unidirectional remote and access control systems. The
HCS515 can be used as a stand-alone decoder or in
conjunction with a microcontroller.
The manufacturer’s code, encoder decryption keys,
and synchronization information are stored in
encrypted form in internal EEPROM. The HCS515
uses the S_DAT and S_CLK inputs to communicate
with a host controller device.
The HCS515 operates over a wide voltage range of
3.0 volts to 5.5 volts. The decoder employs automatic
bit-rate detection, which allows it to compensate for
wide variations in transmitter data rate. The decoder
contains sophisticated error checking algorithms to
ensure only valid codes are accepted.
The KEELOQ name, KEELOQ logo, and logotype are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries.
*Code hopping patents issued in Europe, U. S. A. and R. S.—US:5,517,187; Europe: 0459781
1998 Microchip Technology Inc.
Preliminary
DS40183A-page 1
HCS515
1.0
KEELOQ SYSTEM OVERVIEW
1.2
1.1
Key Terms
The HCS encoders have a small EEPROM array which
must be loaded with several parameters before use.
The most important of these values are:
• Manufacturer’s Code – A 64-bit word, unique to
each manufacturer, used to produce a unique
encoder decryption key in each transmitter.
• Encoder Decryption Key – A 64-bit key, unique for
each transmitter. The encoder decryption key
controls the KEELOQ decryption algorithm and is
stored in EEPROM on the decoder device.
• Learn – The receiver uses information that is
transmitted to derive the transmitter’s encoder
decryption key, decrypt the discrimination value,
and the synchronization counter in learning mode.
The encoder decryption key is a function of the
manufacturer’s code and the device serial number
and/or seed value.
The HCS encoders and decoders employ the KEELOQ
code hopping technology and a KEELOQ encryption
algorithm to achieve a high level of security. Code
hopping is a method by which the code transmitted
from the transmitter to the receiver is different every
time a button is pushed. This method, coupled with a
transmission length of 66 bits, virtually eliminates the
use of code ‘grabbing’ or code ‘scanning’.
FIGURE 1-1:
• An encoder decryption key that is generated at
the time of production
• A 16-bit synchronization counter value
• A 28-bit serial number which is meant to be
unique for every encoder
The manufacturer programs the serial number for each
encoder at the time of production, while the ‘Key Generation Algorithm’ generates the encoder decryption
key (Figure 1-1). Inputs to the key generation algorithm
typically consist of the encoder’s serial number and a
64-bit manufacturer’s code, which the manufacturer
creates.
Note:
The manufacturer code is a pivotal part of
the system’s overall security. Consequently, all possible precautions must be
taken and maintained for this code.
The 16-bit synchronization counter is the basis for the
transmitted code changing for each transmission and is
updated each time a button is pressed. Because of the
complexity of the KEELOQ encryption algorithm, a
change in one bit of the synchronization counter value
will result in a large change in the actual transmitted
code. There is a relationship (Figure 1-2) between the
encoder decryption key values in EEPROM and how
they are used in the encoder. Once the encoder
detects that a button has been pressed, the encoder
reads the button and updates the synchronization
counter. The synchronization value is then combined
with the encoder decryption key in the KEELOQ
encryption algorithm, and the output is 32 bits of
encrypted information. This data will change with every
button press, hence, it is referred to as the code hopping portion of the code word. The 32-bit code hopping
portion is combined with the button information and the
serial number to form the code word transmitted to the
receiver.
CREATION AND STORAGE OF ENCRYPTION KEY DURING PRODUCTION
HCS515 EEPROM Array
Transmitter
Serial Number or
Seed
Manufacturer’s
Code
DS40183A-page 2
HCS Encoder Overview
Key
Generation
Algorithm
Serial Number
Encryption Key
Sync Counter
Encryption
Key
Preliminary
.
.
.
1998 Microchip Technology Inc.
HCS515
1.3
HCS Decoder Overview
When a valid formatted message is detected, the
receiver first compares the serial number. If the serial
number check value is from a learned transmitter, the
message is decrypted. Next, the receiver checks the
decrypted synchronization counter value against what
is stored in memory. If the synchronization counter
value is verified, then a valid transmission message is
sent. Figure 1-3 shows the relationship between some
of the values stored by the receiver and the values
received from the transmitter.
Before a transmitter and receiver can work together,
the receiver must first ‘learn’ and store certain information from the transmitter. This information includes a
‘check value’ of the serial number, the encoder decryption key, and current synchronization counter value.
FIGURE 1-2:
BASIC OPERATION OF A CODE HOPPING TRANSMITTER (ENCODER)
Transmitted Information
KEELOQ
Encryption
Algorithm
EEPROM Array
32 Bits of
Encrypted Data
Serial Number
Button Press
Information
Encoder Decryption Key
Sync. Counter Value
Serial Number
FIGURE 1-3:
BASIC OPERATION OF A CODE HOPPING RECEIVER (DECODER)
Check for
Match
EEPROM Array
KEELOQ
Decryption
Algorithm
Encoder Decryption Key
Decrypted
Synchronization
Counter
Sync. Counter Value
Serial Number
Check for
Match
Manufacturer Code
Button Press
Information
Serial Number
32 Bits of
Encrypted Data
Received Information
1998 Microchip Technology Inc.
Preliminary
DS40183A-page 3
HCS515
2.0
PIN ASSIGNMENT
PIN
Decoder
Function
I/O(1)
Buffer
Type(1)
1
NC
—
—
Description
No connection
2
NC
—
—
No connection
3
VDD
—
—
Power connection
4
S0
O
TTL
S0 function output
5
S1
O
TTL
S1 function output
6
MCLR
I
ST
Master clear input
7
NC
—
—
No connection
No connection
8
NC
—
—
9
S_DAT
I/O
TTL
10
S_CLK
I
TTL
Synchronous clock from controller
11
RF_IN
I
TTL
RF input from receiver
12
GND
—
—
Ground connection
13
NC
—
—
No connection
14
NC
—
—
No connection
Synchronous data from controller
Note: P = power, I = in, O = out, and ST = Schmitt Trigger input.
DS40183A-page 4
Preliminary
1998 Microchip Technology Inc.
HCS515
3.0
DECODER OPERATION
3.1
Learning a Transmitter to a Receiver
(Normal or Secure Learn)
3: Learning a transmitter with an encoder
decryption key that is identical to a transmitter already in memory replaces the existing
transmitter. In practice, this means that all
transmitters should have unique encoder
decryption keys. Learning a previously
learned transmitter does not use any additional memory slots.
Before the transmitter and receiver can work together,
the receiver must first ‘learn’ and store the following
information from the transmitter in EEPROM:
• A check value of the serial number
• The encoder decryption key
• The current synchronization counter value
The following checks are performed by the decoder to
determine if the transmission is valid during learn:
The decoder must also store the manufacturer’s code
(Section 1.2) in protected memory. This code will
typically be the same for all of the decoders in a system.
The HCS515 has seven memory slots, and, consequently, can store up to seven transmitters. During the
learn procedure, the decoder searches for an empty
memory slot for storing the transmitter’s information.
When all of the memory slots are full, the decoder will
overwrite the last transmitter’s information. To erase all
of the memory slots at once, use the ERASE_ALL
command (C3H).
3.1.1
• The first code word is checked for bit integrity.
• The second code word is checked for bit integrity.
• The encoder decryption key is generated according to the selected algorithm.
• The hopping code is decrypted.
• The discrimination value is checked.
• If all the checks pass, the key, serial number
check value, and synchronization counter values
are stored in EEPROM memory.
Figure 3-1 shows a flow chart of the learn sequence.
FIGURE 3-1:
Enter Learn
Mode
LEARNING PROCEDURE
Learning is initiated by sending the ACTIVATE_LEARN
(D2H) command to the decoder. The decoder acknowledges reception of the command by pulling the data
line high.
For the HCS515 decoder to learn a new transmitter, the
following sequence is required:
1.
2.
3.
4.
Activate the transmitter once.
Activate the transmitter a second time. (In
secure learning mode, the seed transmission
must be transmitted during the second stage of
learn by activating the appropriate buttons on
the transmitter.)
The HCS515 will transmit a learn-status string,
indicating that the learn was successful.
The decoder has now learned the transmitter.
Repeat steps 1-3 to learn up to seven
transmitters
Note 1: Learning will be terminated if two
nonsequential codes were received or if two
acceptable codes were not decoded within
30 seconds.
2: If more than seven transmitters are learned,
the new transmitter will replace the last
transmitter learned. It is, therefore, not possible to erase lost transmitters by
repeatedly learning new transmitters. To
remove lost or stolen transmitters,
ERASE_ALL transmitters and relearn all
available transmitters.
1998 Microchip Technology Inc.
LEARN SEQUENCE
Preliminary
Wait for Reception
of a Valid Code
Wait for Reception
of Second
Non-Repeated
Valid Code
Generate Key
from Serial Number/
Seed Value
Use Generated Key
to Decrypt
Compare Discrimination
Value with Serial Number
Equal?
No
Yes
Learn successful. Store:
Learn
Unsuccessful
Serial number check value
Encoder decryption key
Sync. counter value
Exit
DS40183A-page 5
HCS515
3.2
Validation of Codes
The decoder waits for a transmission and checks the
serial number to determine if it is a learned transmitter.
If it is, it takes the code hopping portion of the transmission and decrypts it, using the encoder decryption key.
It uses the discrimination value to determine if the
decryption was valid. If everything up to this point is
valid, the synchronization counter value is evaluated.
3.3
Validation Steps
Validation consists of the following steps:
1.
2.
3.
4.
5.
6.
Search EEPROM to find the Serial Number
Check Value Match
Decrypt the Hopping Code
Compare the 10 bits of the discrimination value
with the lower 10 bits of serial number
Check if the synchronization counter value falls
within the first synchronization window.
Check if the synchronization counter value falls
within the second synchronization window.
If a valid transmission is found, update the
synchronization counter, else use the next
transmitter block, and repeat the tests.
FIGURE 3-2:
Synchronization with Decoder
3.4
DECODER OPERATION
Start
The KEELOQ technology features a sophisticated
synchronization technique (Figure 3-3) which does not
require the calculation and storage of future codes. If
the stored synchronization counter value for that
particular transmitter and the synchronization counter
value that was just decrypted are within a formatted
window of 16, the counter is stored, and the command
is executed. If the synchronization counter value was
not within the single operation window, but is within the
double operation window of the 16K window, the
transmitted synchronization counter value is stored in a
temporary location, and the decoder goes back to waiting for another transmission. When the next valid
transmission is received, it will check the new
synchronization counter value with the one in temporary storage. If the two values are sequential, it is
assumed that the counter had just gotten out of the
single operation ‘window’, but is now back in synchronization, so the new synchronization counter value is
stored, and the command is executed. If a transmitter
has somehow gotten out of the double operation
window, the transmitter will not work and must be
relearned. Since the entire window rotates after each
valid transmission, codes that have been used become
part of the ‘blocked’ (48K) codes and are no longer
valid. This eliminates the possibility of grabbing a previous code and retransmitting to gain entry.
FIGURE 3-3:
No Transmission
Received?
Entire Window
rotates to eliminate
use of previously
used codes
Yes
No
SYNCHRONIZATION WINDOW
Does
Ser # Check Val
Match?
Blocked
(48K Codes)
Yes
Decrypt Transmission
No
Is
decryption
valid?
Double
Operation
(16K Codes)
Yes
Is
Yes
counter within
16?
Execute
Command
and
Update
Counter
Current
Position
Single
Operation
Window
(16 Codes)
No
Is
No counter
within
16K?
Yes
Save Counter
in Temp Location
DS40183A-page 6
Preliminary
1998 Microchip Technology Inc.
HCS515
4.0
INTERFACING TO A
MICROCONTROLLER
4.1
Valid Transmission Message
The decoder informs the microcontroller of a valid
transmission by taking the data line high for up to
500 ms. The controlling microcontroller must acknowledge by taking the clock line high. The decoder then
takes the data line low. The microcontroller can then
begin clocking a data stream out of the HCS515. The
data stream consists of:
The HCS515 interfaces to a microcontroller via a synchronous serial interface. A clock and data line are
used to communicate with the HCS515. The microcontroller controls the clock line. There are two groups of
data transfer messages. The first is from the decoder
whenever the decoder receives a valid transmission.
The decoder signals reception of a valid code by taking
the data line high (maximum of 500 ms) The microcontroller then services the request by clocking out a data
string from the decoder. The data string contains the
function code, the status bit, and block indicators. The
second is from the controlling microcontroller to the
decoder in the form of a defined command set.
•
•
•
•
•
Start bit ‘0’.
2 status bits [REPEAT, VLOW].
4-bit function code [S3 S2 S1 S0].
Stop bit ‘1’.
4 bits indicating the number of transmitters
learned into the decoder [CNT3…CNT0].
• 4 bits indicating which block was used
[TX3…TX0].
• 64 bits of the received transmission with the hopping code decrypted.
Figure 4-1 shows the HCS515 decoder and the I/O
interface lines necessary to interface to a microcontroller.
Note:
Data is always clocked in/out Least
Significant Bit (LSB) first.
The decoder will terminate the transmission of the data
stream at any point where the clock is kept low for
longer than 1 ms.Therefore, the microcontroller can
only clock out the required bits. A maximum of 80 bits
can be clocked out of the decoder.
FIGURE 4-1:
HCS515 DECODER AND I/O INTERFACE LINES
X
X
VCC
1
2
3
4
5
6
X
7
NC
NC
NC
NC
VSS
VDD
S0
RF_IN
S1
S_CLK
MCLR
S_DAT
NC
NC
14
13
RF DATA
X
X
SYNC CLOCK
12
11
SYNC DATA
10
9
MICRO RESET
8
X
S1 OUTPUT
HCS515
S0 OUTPUT
FIGURE 4-2:
DECODER VALID TRANSMISSION MESSAGE
TACK
TACT
TCLKL
TCLKH
TDS
S_CLK
TCLA
TCLKH
TDHI
0
S_DAT
Decoder Signal Valid
Transmission
A
REPT VLOW S0
S1
S2
S3
1
CNT0
CNT3 TX0
TX3
RX0
Information
B
1998 Microchip Technology Inc.
RX62 RX63
Received String
Ci
Preliminary
RX1
Cii
DS40183A-page 7
HCS515
4.2
Command Mode
4.2.2
4.2.1
MICROCONTROLLER COMMAND MODE
ACTIVATION
The HCS515 uses collision detection to prevent
clashes between the decoder and microcontroller.
Whenever the decoder receives a valid transmission
the following sequence is followed:
The microcontroller command consists of four parts.
The first part activates the command mode, the second
part is the actual command, the third is the address
accessed, and the last part is the data. The microcontroller starts the command by taking the clock line high
for up to 500 ms. The decoder acknowledges the startup sequence by taking the data line high. The microcontroller takes the clock line low, after which the
decoder will take the data line low, tri-state the data line
and wait for the command to be clock in. The data must
be set up on the rising edge and will be sampled on the
falling edge of the clock line.
FIGURE 4-3:
COLLISION DETECTION
• The decoder first checks to see if the clock line is
high. If the clock line is high, the valid transmission notification is aborted, and the microcontroller command mode request is serviced.
• The decoder takes the data line high and checks
that the clock line doesn’t go high within 50 µs. If
the clock line goes high, the valid transmission
notification is aborted and the command mode
request is serviced.
• If the clock line goes high after 50 µs but before
500 ms, the decoder will acknowledge by taking
the data line low.
• The microcontroller can then start to clock out the
80-bit data stream of the received transmission.
MICROCONTROLLER COMMAND MODE ACTIVATION
TCLKL
TREQ
TCLKH
TSTART
TADDR
TCMD
TDATA
TDS
CLK
µC Data
LSB
MSB
LSB
MSB
LSB
MSB
TACK
TRESP
HCS515
Data
Start Command
A
DS40183A-page 8
Command Byte
B
Address Byte
C
Preliminary
Data Byte
D
E
1998 Microchip Technology Inc.
HCS515
4.2.3
4.2.4
COMMAND ACTIVATION TIMES
The command activation time (Table 4-1) is defined as
the maximum time the microcontroller has to wait for a
response from the decoder. The decoder will abort and
service the command request. The response time
depends on the state of the decoder when the command mode is requested.
TABLE 4-1:
DECODER COMMANDS
The command byte specifies the operation required by
the controlling microcontroller. Table 4-2 lists the commands.
COMMAND ACTIVATION TIMES
Decoder State
Min
Max
While receiving transmissions
—
2 1/2 BPWMAX = 2.7 ms
During the validation of a received transmission
—
3 ms
During the update of the sync counters
—
40 ms
During learn
—
170 ms
TABLE 4-2:
DECODER COMMANDS
Instruction
Command Byte
Operation
READ
F016
Read a byte from user EEPROM
WRITE
E116
Write a byte to user EEPROM
ACTIVATE_LRN
D216
Activate a learn sequence on the decoder
ERASE_ALL
C316
Activate an erase all function on the decoder
PROGRAM
B416
Program manufacturer’s code and configuration byte
1998 Microchip Technology Inc.
Preliminary
DS40183A-page 9
HCS515
4.2.5
4.2.6
READ BYTE/S FROM USER EEPROM
The write command (Figure 4-5) is used to write a location in the user EEPROM. The address byte is truncated to seven bits (C to D). The data is clocked in least
significant bit first. The clock line must be asserted to
initiate the write. Sequential writes of bytes are possible
by clocking in the byte and then asserting the clock line
(D – F). The decoder will terminate the write command
if no clock pulses are received for a period longer than
1.2 ms After a successful write sequence the decoder
will acknowledge by taking the data line high and keeping it high until the clock line goes low.
The read command (Figure 4-4) is used to read bytes
from the user EEPROM. The offset in the user
EEPROM is specified by the address byte which is
truncated to seven bits (C to D). After the address, a
dummy byte must be clocked in (D to E). The EEPROM
data byte is clocked out on the next rising edge of the
clock line with the least significant bit first (E to F).
Sequential reads are possible by repeating sequence E
to F within 1 ms after the falling edge of the previous
byte’s Most Significant Bit (MSB) bit. During the
sequential read, the address value will wrap after 128
bytes. The decoder will terminate the read command if
no clock pulses are received for a period longer than
1.2 ms.
FIGURE 4-4:
WRITE BYTE/S TO USER EEPROM
4.2.7
ERASE ALL
The erase all command (Figure 4-6) erases all the
transmitters in the decoder. After the command and two
dummy bytes are clocked in, the clock line must be
asserted to activate the command. After a successful
completion of an erase all command, the data line is
asserted until the clock line goes low.
READ BYTES FROM USER EEPROM
TRD
TRD
CLK
µC DATA
LSB
MSB
LSB
MSB
LSB
MSB
MSB
LSB
Decoder DATA
Start Command
A
FIGURE 4-5:
Command Byte
Dummy Byte
Address Byte
B
Data Byte
D
C
F
E
WRITE BYTES TO USER EEPROM
TACK
TWR
TRESP
CLK
µC DATA
LSB
MSB
LSB
MSB
LSB
MSB
TACK2
Decoder DATA
Start Command
A
Command Byte
B
FIGURE 4-6:
Data Byte
Address Byte
C
Acknowledge
D
E
F
ERASE ALL
TACK
TERA
TRESP
CLK
µC DATA
LSB
MSB
LSB
MSB
LSB
MSB
TACK2
Decoder DATA
Start Command
A
DS40183A-page 10
B
Subcommand Byte
Command Byte
C
Dummy Byte
D
Preliminary
Acknowledge
E
F
1998 Microchip Technology Inc.
HCS515
4.2.8
Upon reception of the second transmission, the
decoder will respond with a learn status message
(Figure 4-9).
ACTIVATE LEARN
The activate learn command (Figure 4-7) is used to
activate a transmitter learning sequence on the
decoder. The command consists of a command mode
activation sequence, a command byte, and two dummy
bytes. The decoder will respond by taking the data line
high to acknowledge that the command was valid and
that learn is active.
The learn status message after the second transmission consists of the following:
• 1 start bit.
• The function code [S3:S0] of the message is zero,
indicating that this is a status string.
• The RESULT bit indicates the result of the learn
sequence. The RESULT bit is set if successful
and cleared otherwise.
• The OVR bit will indicate whether an exiting transmitter is over written. The OVR bit will be set if an
existing transmitter is learned over.
• The [CNT3…CNT0] bits will indicate the number
of transmitters learned on the decoder.
• The [TX3…TX0] bits indicate the block number
used during the learning of the transmitter.
Upon reception of the first transmission, the decoder
will respond with a learn status message (Figure 4-8).
During learn, the decoder will acknowledge the reception of the first transmission by taking the data line high
for 60 ms. The controlling microcontroller can clock out
at most eight bits, which will all be zeros. All of the bits
of the status byte are zero, and this is used to distinguish between a learn time-out status string and the
first transmission received string. The controlling microcontroller must ensure that the clock line does not go
high 60 ms after the falling edge of the data line, for this
will terminate learn.
FIGURE 4-7:
LEARN MODE ACTIVATION
TACK
TRESP
TLRN
CLK
µC DATA
MSB
LSB
LSB
MSB
LSB
MSB
TACK2
Decoder DATA
Start Command
A
FIGURE 4-8:
Command Byte
Dummy Byte
B
Dummy Byte
Acknowledge
D
C
E
F
LEARN STATUS MESSAGE AFTER FIRST TRANSMISSION
TCA
TCLL
TCLKL
TDS
TCLKH
CLK
TCLH
TCLA
TDHI
0
Decoder
Data
0
Command Request
0
0
0
0
0
Status Byte
A
FIGURE 4-9:
0
B
C
LEARN STATUS MESSAGE AFTER SECOND TRANSMISSION
TACT
TCLL
TCLKL
TDS
TCLKH
CLK
TCLH
TCLA
TDHI
0
Decoder
Data
Communications Request
A
1998 Microchip Technology Inc.
OVR RSLT
0
0
0
0
1
CNT0
CNT3 TX0
TX3
RX0
Ci
Preliminary
RX62 RX63
Decoded Tx
Learn Status Bits
B
RX1
Cii
DS40183A-page 11
HCS515
4.3
Stand-alone Mode
4.4
The HCS515 decoder can also be used in stand-alone
applications. The HCS515 will activate the data line for
up to 500 ms if a valid transmission was received, and
this output can be used to drive a relay circuit. To activate learn or erase all commands, a button must be
connected to the CLK input. User feedback is indicated
on an LED connected to the DATA output line. If the
CLK line is pulled high, using the learn button, the LED
will switch on. After the CLK line is kept high for longer
than 2 seconds, the decoder will switch the LED line off,
indicating that learn will be entered if the button is
released. If the CLK line is kept high for another 6 seconds, the decoder will activate an ERASE_ALL Command.
Learn mode can be aborted by taking the clock line
high until the data line goes high (LED switches on).
During learn, the data line will give feedback to the user
and, therefore, must not be connected to the relay drive
circuitry.
Note:
The REPS bit must be cleared in the configuration byte in stand-alone mode.
After taking the clock low and before a transmitter is
learn, any low-to-high change on the clock line may terminate learn. This has learn implications when a switch
with contact bounce is used.
Erase All Command and Erase
Command
The Table 4-3 describes two versions of the Erase All
command.
TABLE 4-3:
ERASE ALL COMMAND
Command
Byte
Subcommand
Byte
C316
0016
Erase all
transmitters.
0116
Erase all transmitters except 1. The
first transmitter in
memory is not
erased.
C316
Description
Subcommand 01 can be used where a transmitter with
permanent status is implemented in the microcontroller
software. Use of subcommand 01 ensures that the permanent transmitter remains in memory even when all
other transmitters are erased. The first transmitter
learned after any of the following events is the first
transmitter in memory and becomes the permanent
transmitter:
1.
2.
4.5
Programming of the manufacturer’s code.
Erasing of all transmitters
(subcommand 00 only).
Test Mode
A special test mode is activated after:
1.
2.
Programming of the manufacturer’s code.
Erasing of all transmitters.
Test mode can be used to test a decoder before any
transmitters are learned on it. Test mode enables testing of decoders without spending the time to learn a
transmitter. Test mode is terminated after the first successful learning of an ordinary transmitter. In test
mode, the decoder responds to a test transmitter. The
test transmitter has the following properties:
1.
2.
3.
4.
Encoder decryption key = manufacturer’s code.
Serial number = any value.
Discrimination bits = lower 10 bits of the serial
number.
Synchronization counter value = any value
(synchronization information is ignored).
Because the synchronization counter value is ignored
in test mode, any number of test transmitters can be
used, even if their synchronization counter values are
different.
DS40183A-page 12
Preliminary
1998 Microchip Technology Inc.
HCS515
4.6
Power Supply Supervisor
not occur after supply voltage “brown-out” conditions,
the use of a proper power supply supervisor device is
imperative (Figure 4-11 and Figure 8-4).
Reliable operation of the HCS515 requires that the
contents of the EEPROM memory be protected against
erroneous writes. To ensure that erroneous writes do
FIGURE 4-10: STAND-ALONE MODE LEARN/ERASE-ALL TIMING
TREQ
TLRN
TERA
TLRN
CLK
DATA
Learn Activation
A
B
Erase-All Activation
Successful
C
E
D
FIGURE 4-11: TYPICAL STAND-ALONE APPLICATION CIRCUIT
ANT1
RF Circuit
Vcc
Vcc
X
X
Vcc
U3
Brown-out Circuit
VI G VO
N
D
X
X
1
2
3
4
5
6
7
NC
NC
VDD
S0
S1
MCLR
NC
NC
NC
VSS
RF_IN
S_CLK
S_DAT
NC
14
X
13
X
12
11
10
9
8 X
S1
LEARN
HCS515
R1
10K
R3
10K
OUTPUT
Vcc
K2
Q2
NPN
1998 Microchip Technology Inc.
Preliminary
10K
R2
10K
D1
LED
RELAY SPST
DS40183A-page 13
HCS515
5.0
DECODER PROGRAMMING
The memory is divided between system memory that stores the transmitter information (read protected) and user memory (read/write). Commands to access the user memory are described in Sections 4.2.5 and 4.2.6.
The following information stored in system memory needs to be programmed before the decoder can be used:
• 64-bit manufacturer’s code
• Decoder configuration byte
Note 1: These memory locations are read protected and can only be written to using the program command with
the device powered up.
2: The contents of the system memory is encrypted by a unique 64-bit key that is stored in the HCS515. To
initialize the system memory, the HCS515’s program command must be used.
5.1
Configuration Byte
The decoder is configured during initialization by setting the appropriate bits in the configuration byte. The following table
list the options:
5.1.1
Bit
Mnemonic
0
LRN_MODE
1
2
Not Used
REPEAT
3
4
5
6
7
Not Used
Not Used
Not Used
Not Used
Not Used
Description
Learning mode selection
LRN_MODE = 0—Normal Learn
LRN_MODE = 1—Secure Learn
Reserved
Repeat Transmission enable
0 = Disable
1 = Enabled
Reserved
Reserved
Reserved
Reserved
Reserved
LRN_MODE
LRN_MODE selects between two learning modes. With LRN_MODE = 0, the normal (serial number derived) mode is
selected; with LRN_MODE=1, the secure (seed derived) mode is selected. See Section 6.0 for more detail on learning
modes.
5.1.2
REPEAT
The HCS515 can be configured to indicate repeated transmissions. In a stand-alone configuration, repeated transmissions must be disabled.
DS40183A-page 14
Preliminary
1998 Microchip Technology Inc.
HCS515
5.2
Programming Waveform
5.3
The programming command consists of the following:
•
•
•
•
•
A total of 80 bits are clocked into the decoder. The 8-bit
command byte is clocked in first, followed by the 8-bit
configuration byte and the 64-bit manufacturer’s code.
The data must be clocked in Least Significant Bit (LSB)
first. The decoder will then encrypt the manufacturer’s
code using the decoder’s unique 64-bit EEPROM
encoder decryption key. After completion of the programming EEPROM, the decoder will acknowledge by
taking the data line high (G to H). If the data line goes
high within 30 ms after the clock goes high, programming also fails.
Command Request Sequence (A to B)
Command Byte (B to C)
Configuration Byte (C to D)
Manufacturer’s Code Eight Data Bytes (D to G)
Activation and Acknowledge Sequence (G to H)
FIGURE 5-1:
Programming Data String
PROGRAMMING WAVEFORM
TCMD
TCLKL
TPP1 TPP3
TCLKH
TDATA
TADDR
TDATA
TDS
TACK
TWT2
CLK
µC DATA
TPP2TPP4
LSB
MSB
LSB
MSB
MSB
LSB
MSB
TAW
DECODER DATA
Start Command
A
Command Byte
B
1998 Microchip Technology Inc.
Least Significant Byte
Configuration Byte
C
D
Preliminary
E
Most Significant Byte
F
Acknowledge
G
H
DS40183A-page 15
HCS515
6.0
KEY GENERATION
The HCS515 supports two learning schemes which are selected during the initialization of the system EEPROM. The
learning schemes are:
• Normal learn using the KEELOQ decryption algorithm
• Secure learn using the KEELOQ decryption algorithm
6.1
Normal (Serial Number derived) Learn using the KEELOQ Decryption Algorithm
This learning scheme uses the KEELOQ decryption algorithm and the 28-bit serial number of the transmitter to derive
the encoder decryption key. The 28-bit serial number is patched with predefined values as indicated below to form two
32-bit seeds.
SourceH = 60000000 00000000H + Serial Number | 28 Bits
SourceL = 20000000 00000000H + Serial Number | 28 Bits
Then, using the KEELOQ decryption algorithm and the manufacturer’s code the encoder decryption key is
derived as follows:
KeyH Upper 32 bits = F KEELOQ Decryption (SourceH) | 64-Bit Manufacturer’s Code
KeyL Lower 32 bits = F KEELOQ Decryption (SourceL) | 64-Bit Manufacturer’s Code
6.2
Secure (Seed Derived) Learn using the KEELOQ Decryption Algorithm
This scheme uses the secure seed transmitted by the encoder to derive the two input seeds. The decoder always uses
the lower 64 bits of the transmission to form a 60-bit seed. The upper 4 bits are always forced to zero.
For 32-bit seed encoders (HCS200/HCS300/HCS301):
SourceH = Serial Number Lower 28 bits
SourceL = Seed 32 bits
For 48-bit seed encoders (HCS360/HCS361):
SourceH = Seed Upper 16 bits + Serial Number Upper 16 bits with upper 4 bits set to zero
SourceL = Seed Lower 32 bits
For 60-bit seed encoders (HCS410):
SourceH = Seed Upper 32 bits with upper 4 bits set to zero
SourceL = Seed Lower 32 bits
The KEELOQ decryption algorithm and the manufacturer’s code is used to derive the encoder decryption key as
follows:
KeyH Upper 32 bits = F KEELOQ Decrypt (SourceH) | 64 Bit Manufacturer’s Code
KeyL Lower 32 bits = F KEELOQ Decrypt (SourceL) | 64 Bit Manufacturer’s Code
DS40183A-page 16
Preliminary
1998 Microchip Technology Inc.
HCS515
7.0
KEELOQ ENCODERS
7.2
7.1
Transmission Format (PWM)
The HCS encoder transmits a 66/67-bit code word
when a button is pressed. The 66/67-bit word is constructed from a code hopping portion and a non-code
hopping portion (Figure 7-2).
The KEELOQ encoder transmission is made up of several parts (Figure 7-1). Each transmission begins with
a preamble and a header, followed by the encrypted
and then the fixed data. The actual data is 66/67 bits
which consists of 32 bits of encrypted data and 34/35
bits of non-encrypted data. Each transmission is followed by a guard period before another transmission
can begin. The code hopping portion provides up to
four billion changing code combinations and includes
the button status bits (based on which buttons were
activated), along with the synchronization counter
value and some discrimination bits. The non-code hopping portion is comprised of the status bits, the function
bits, and the 28-bit serial number. The encrypted and
non-encrypted combined sections increase the number of combinations to 7.38 x 1019.
FIGURE 7-1:
Code Word Organization
The Encrypted Data is generated from four button bits,
two overflow counter bits, ten discrimination bits, and
the 16-bit synchronization counter value.
The Non-encrypted Data is made up from 2 status
bits, 4 function bits, and the 28/32-bit serial number.
CODE WORD TRANSMISSION FORMAT
LOGIC ‘0’
LOGIC ‘1’
Bit
Period
Header
TH
Preamble
TP
FIGURE 7-2:
Fixed Portion of
Transmission
TFIX
Code Hopping Portion
of Transmission
THOP
CODE WORD ORGANIZATION
Non-encrypted Data
Repeat
CRC1*
Guard
Time
TG
CRC0*
3/2 bits
VLOW
(1 bit)
+
Encrypted Data
Button Status
S2S1S0S3
(4 bits)
28-bit
Serial
Number
Serial Number and
Button Status (32 bits)
Button Status
S2S1S0S3
(4 bits)
+
16-bit
Sync.
Counter
Value
Discrimination
bits (12 bits)
32 bits of Encrypted Data
66/67 bits
of Data
Transmitted
*HCS360/361
1998 Microchip Technology Inc.
Preliminary
DS40183A-page 17
HCS515
8.0
ELECTRICAL CHARACTERISTICS FOR HCS515
Absolute Maximum Ratings†
Ambient temperature under bias .............................................................................................................. -40°C to +85°C
Storage temperature ..............................................................................................................................-65 °C to +150°C
Voltage on any pin with respect to VSS (except VDD) ........................................................................ -0.6V to VDD +0.6V
Voltage on VDD with respect to Vss.................................................................................................................. 0 to +7.0V
Total power dissipation (Note) ............................................................................................................................. 700 mW
Maximum current out of VSS pin........................................................................................................................... 200 mA
Maximum current into VDD pin ............................................................................................................................. 150 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ........................................................................................................ ± 20 mA
Output clamp current, IOK (VO < 0 or VO >VDD) ................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin ......................................................................................................... 25 mA
Maximum output current sourced by any I/O pin.................................................................................................... 25 mA
Note:
Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD–VOH) x IOH} + ∑(VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DS40183A-page 18
Preliminary
1998 Microchip Technology Inc.
HCS515
TABLE 8-1:
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
Commercial (C):
0°C ≤ TA ≤ +70‡°C
Industrial (I):
-40°C ≤ TA ≤ +85‡°C
Symbol
Parameters
Min
Typ(†)
Max
Units
Conditions
VDD
Supply voltage
3.0
—
5.5
V
VPOR
VDD start voltage to
ensure Reset
—
Vss
—
V
SVDD
VDD rise rate to
ensure reset
0.05*
—
—
V/ms
IDD
Supply current
—
—
1.8
0.3
2.4
5
mA
µA
FOSC = 4 MHz, VDD = 5.5V
Sleep mode (no RF input)
IPD
Power Down Current
—
0.25
5
µA
VDD = 3.0V, Commercial
VDD = 3.0V, Industrial
VIL
Input low voltage
—
0.3
6
µA
VSS
—
0.15 VDD
V
VSS
—
0.8
V
VDD between 4.5V and 5.5V
0.25 VDD + 0.8
—
VDD
V
Except MCLR = 0.85 VDD
VIH
Input high voltage
2.0
—
VDD
V
VDD between 4.5V and 5.5V
VOL
Output low voltage
—
—
0.6
V
IOL = 8.7 mA, VDD = 4.5V
VOH
Output high voltage
VDD - 0.7
—
—
V
IOH = -5.4 mA, VDD = 4.5V
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
* These parameters are characterized but not tested.
Note:
Negative current is defined as coming out of the pin.
TABLE 8-2:
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified):
Commercial (C): 0°C ≤ TA ≤ +70°C
Industrial (I):
-40°C ≤ TA ≤ +85°C
Symbol
TE
TOD
TMCLR
Parameters
Note:
Typ
Max
Units
Transmit elemental period
65
—
660
µs
Output delay
48
75
237
ms
MCLR low time
150
—
—
ns
—
150
222
ms
Time output valid
TOV
Min
Conditions
These parameters are characterized but not tested.
FIGURE 8-3:
RESET WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER
TIMING
VDD
MCLR
TMCLR
Tov
I/O Pins
1998 Microchip Technology Inc.
Preliminary
DS40183A-page 19
HCS515
8.1
AC Electrical Characteristics
8.1.1
VALID TRANSMISSION NOTIFICATION
Standard Operating Conditions (unless otherwise specified)”
Commercial (C): 0°C ≤ TA ≤ +70°C
Industrial (I):
-40°C ≤ TA ≤ +85°C
Symbol
Parameters
Min
Typ
Max
Units
TDHI
Command request time
0.0050
—
500
ms
TCLA
Micro request acknowledge time
0.0050
—
1
ms
TACK
Decoder Acknowledge time
—
—
4
µs
TACT
Start command mode to
first command bit
20
—
1200
µs
TCLKH
Clock high time
20
—
1000
µs
TCLKL
Clock low time
20
—
1000
µs
FCLK
Clock frequency
500
—
25000
Hz
Data hold time
14
—
1000
µs
TDS
Note:
8.1.2
These parameters are characterized but not tested.
COMMAND MODE ACTIVATION
Standard Operating Conditions (unless otherwise specified):
Commercial (C): 0°C ≤ TA ≤ +70°C
Industrial (I):
-40°C ≤ TA ≤ +85°C
Symbol
Parameters
Min
Typ
Max
Units
TREQ
Command request time
0.0050
—
500
ms
TRESP
Microcontroller request
acknowledge time
—
—
1
ms
TACK
Decoder acknowledge time
—
—
4
µs
TSTART
Start command mode to first
command bit
20
—
1000
µs
TCLKH
Clock high time
20
—
1000
µs
TCLKL
Clock low time
20
—
1000
µs
FCLK
Clock frequency
500
—
25000
Hz
TDS
Data hold time
14
—
—
µs
TCMD
Command validate time
—
—
10
µs
TADDR
Address validate time
—
—
10
µs
TDATA
Data validate time
—
—
10
µs
Note:
8.1.3
These parameters are characterized but not tested.
READ FROM USER EEPROM COMMAND
Standard Operating Conditions (unless otherwise specified):
Commercial (C): 0°C ≤ TA ≤ +70°C
Industrial (I):
-40°C ≤ TA ≤ +85°C
Symbol
TRD
Note:
Parameters
Decoder EEPROM read time
Min
Typ
Max
Units
1000
—
2000
µs
These parameters are characterized but not tested.
DS40183A-page 20
Preliminary
1998 Microchip Technology Inc.
HCS515
8.1.4
WRITE TO USER EEPROM COMMAND
Standard Operating Conditions (unless otherwise specified):
Commercial (C): 0°C ≤ TA ≤ +70°C
Industrial (I):
-40°C ≤ TA ≤ +85°C
Symbol
Parameters
Min
Typ
Max
Units
TWR
Write command activation time
20
—
1000
µs
TACK
EEPROM write acknowledge time
—
—
10
ms
TRESP
Microcontroller acknowledge
response time
20
—
1000
µs
TACK2
Decoder response
acknowledge time
—
—
10
µs
Note:
8.1.5
These parameters are characterized but not tested.
ERASE ALL COMMAND
Standard Operating Conditions (unless otherwise specified):
Commercial (C): 0°C ≤ TA ≤ +70°C
Industrial (I):
-40°C ≤ TA ≤ +85°C
Symbol
Parameters
Min
Typ
Max
Units
TERA
Learn command activation time
20
—
1000
µs
TACK
Decoder acknowledge time
20
—
210
ms
TRESP
Microcontroller acknowledge
response time
20
—
1000
µs
TACK2
Decoder data line low
—
—
10
µs
Note:
8.1.6
These parameters are characterized but not tested.
ACTIVATE LEARN COMMAND IN MICRO MODE
Standard Operating Conditions (unless otherwise specified):
Commercial (C): 0°C ≤ TA ≤ +70 °C
Industrial (I):
-40°C ≤ TA ≤ +85°C
Symbol
Parameters
Min
Typ
Max
Units
TLRN
Learn command activation time
20
—
1000
µs
TACK
Decoder acknowledge time
—
—
20
µs
TRESP
Microcontroller acknowledge
response time
20
—
1000
µs
TACK2
Decoder data line low
—
—
10
µs
Note:
8.1.7
These parameters are characterized but not tested.
ACTIVATE LEARN COMMAND IN STAND-ALONE MODE
Standard Operating Conditions (unless otherwise specified):
Commercial (C): 0°C ≤ TA ≤ +70°C
Industrial (I):
-40°C ≤ TA ≤ +85°C
Symbol
Parameters
Min
Typ
Max
Units
TREQ
Command request time
—
—
100
ms
TLRN
Learn command activation time
—
—
2
s
TERA
Erase-all command activation time
—
—
6
s
Note:
These parameters are characterized but not tested.
1998 Microchip Technology Inc.
Preliminary
DS40183A-page 21
HCS515
8.1.8
LEARN STATUS STRING
Standard Operating Conditions (unless otherwise specified):
Commercial (C): 0°C ≤ TA ≤ +70°C
Industrial (I):
-40°C ≤ TA ≤ +85°C
Symbol
Parameters
TDHI
Command request time
TCLA
Microcontroller command
request time
TACT
Decoder request acknowledge time
TCLH
Clock high hold time
TCLL
Clock low hold time
Units
—
—
500
ms
0.005
—
500
ms
—
—
10
µs
1.2
ms
—
1.2
ms
—
1000
µs
Clock low time
20
—
1000
µs
Clock frequency
500
—
25000
Hz
—
—
5
µs
TCLKL
FCLK
8.1.9
Max
20
Clock high time
Data hold time
TDS
Typ
0.020
TCLKH
Note:
Min
These parameters are characterized but not tested.
PROGRAMMING COMMAND
Standard Operating Conditions (unless otherwise specified):
Commercial (C): 0°C ≤ TA ≤ +70°C
Industrial (I):
-40°C ≤ TA ≤ +85°C
Symbol
Parameters
Min
Typ
Max
Units
TPP1
Command request time
—
—
500
ms
TPP2
Decoder acknowledge time
—
—
1
ms
TPP3
Start command mode to first
command bit
20
—
1000
µs
TPP4
Data line low before tri-stated
—
—
5
µs
TCLKH
Clock high time
20
—
1000
µs
TCLKL
Clock low time
20
—
1000
µs
FCLK
Clock frequency
500
—
25000
Hz
TDS
Data hold time
—
—
5
µs
TCMD
Command validate time
—
—
10
µs
TACK
Command acknowledge time
30
—
240
ms
TWT2
Acknowledge respond time
20
—
1000
µs
Data low after clock low
—
—
10
µs
TALW
Note:
These parameters are characterized but not tested.
DS40183A-page 22
Preliminary
1998 Microchip Technology Inc.
HCS515
FIGURE 8-4:
TYPICAL MICROCONTROLLER INTERFACE CIRCUIT
RF
Receiver
Vcc
X
X
Vcc
Power Supply
Supervisor 4.5V
VI G VO
N
D
X
X
X
1
2
3
4
5
6
7
NC
NC
VDD
S0
S1
MCLR
NC
NC
NC
VSS
RF_IN
S_CLK
S_DAT
NC
14
X
13
X
12
11
10
9
8 X
HCS515
1998 Microchip Technology Inc.
Preliminary
RST
Microcontroller
10K
In circuit
Programming
Probe Pads
DS40183A-page 23
HCS515
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
HCS515
—
/P
Package:
P = Plastic DIP (300 mil Body), 14-lead
SM = Plastic SOIC (150 mil Body), 14-lead
Temperature
Range:
Device:
Blank = 0°C to +70°C
I = –40°C to +85°C
HCS515
HCS515T
Code Hopping Decoder
Code Hopping Decoder (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office.
The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.
The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
DS40183A-page 24
Preliminary
1998 Microchip Technology Inc.
HCS515
NOTES:
1998 Microchip Technology Inc.
Preliminary
DS40183A-page 25
HCS515
NOTES:
DS40183A-page 26
Preliminary
1998 Microchip Technology Inc.
HCS515
NOTES:
1998 Microchip Technology Inc.
Preliminary
DS40183A-page 27
M
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Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-39-6899939 Fax: 39-39-6899883
Microchip Technology Taiwan
Singapore Branch
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
1/13/98
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
All rights reserved. © 1998, Microchip Technology Incorporated, USA. 2/98
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty
is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval
by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS40183A-page 28
Preliminary
1998 Microchip Technology Inc.