PIC24FJXXXGA2/GB2 FAMILIES PIC24FJXXXGA2/GB2 Families Flash Programming Specification 1.0 DEVICE OVERVIEW This document defines the programming specification for the PIC24FJXXXGA2/GB2 families of microcontroller devices. This programming specification is required only for those developing programming support for the PIC24FJXXXGA2/GB2 devices. Customers using only one of these devices should use development tools that already provide support for device programming. This specification is divided into major sections that describe the programming methods independently. Section 3.0 “Device Programming – ICSP” describes the In-Circuit Serial Programming method. Section 4.0 “Device Programming – Enhanced ICSP” describes the Enhanced In-Circuit Serial Programming method. Note: This programming specification is specific to the following devices: • PIC24FJ128GA204 • PIC24FJ64GA204 • PIC24FJ128GA202 • PIC24FJ64GA202 • PIC24FJ128GB204 • PIC24FJ64GB204 • PIC24FJ128GB202 • PIC24FJ64GB202 2.0 In those cases where legacy programming specification code from other device families is used as a basis to implement the programming specification for the PIC24FJXXXGA2/GB2 devices, special care must be taken to ensure all references to TBLPAG and NVMCON, in any existing code, are updated with the correct opcode hex data for the mnemonic and operands. PROGRAMMING OVERVIEW OF PIC24FJXXXGA2/GB2 DEVICES There are two methods of programming the PIC24FJXXXGA2/GB2 devices discussed in this programming specification. They are: • In-Circuit Serial Programming™ (ICSP™) • Enhanced In-Circuit Serial Programming (Enhanced ICSP) The ICSP programming method is the most direct method to program the device; however, it is also the slower of the two methods. It provides native, low-level programming capability to erase, program and verify the chip. The address of the Special Function Register, TBLPAG, has moved from 32h to 54h in the devices covered in this specification. PIC24FJXXXGA2/GB2 Devices: Command (Binary) Data (Hex) 0000 8802A0 Description MOV W0, TBLPAG Previous PIC24F Families: Command (Binary) Data (Hex) 0000 880190 Description MOV W0, TBLPAG The Enhanced In-Circuit Serial Programming (Enhanced ICSP) protocol uses a faster method that takes advantage of the Programming Executive (PE), as illustrated in Figure 2-1. The Programming Executive provides all the necessary functionality to erase, program and verify the chip through a small command set. The command set allows the programmer to program the PIC24FJXXXGA2/GB2 MCUs without having to deal with the low-level programming protocols of the chip. 2012-2015 Microchip Technology Inc. DS30000510F-page 1 PIC24FJXXXGA2/GB2 FAMILIES FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™ FIGURE 2-2: CONNECTIONS FOR THE VCAP AND VBAT PINS PIC24FJ128GA20X/GB20X Devices (VBAT tied to VDD): PIC24F Devices 3.3V PIC24FJXXXGA2/GB2 Programming Executive Programmer VDD VBAT VCAP CEFC (10 F typ.) On-Chip Memory 2.1 2.2 Power Requirements All PIC24FJXXXGA2/GB2 devices power their core digital logic at a nominal 1.8V. To simplify system design, all devices in the PIC24FJXXXGA2/GB2 families incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins. A low-ESR capacitor (such as ceramic or tantalum) must be connected to the VCAP pin (see Table 2-1 and Figure 2-2). This helps to maintain the stability of the regulator. The specifications for core voltage and capacitance are listed in Section 7.0 “AC/DC Characteristics and Timing Requirements”. Program Memory Write/Erase Requirements The Flash program memory on PIC24FJXXXGA2/GB2 devices has a specific write/erase requirement that must be adhered to for proper device operation. The rule is that any given word in memory must not be written more than twice before erasing the page in which it is located. Thus, the easiest way to conform to this rule is to write all of the data in a programming block, within one write cycle. The programming methods specified in this specification comply with this requirement. Note: Devices in the PIC24FJ128GA204/GB204 families also incorporate a secondary voltage source pin (VBAT) that allows the device to resume operation after VDD has been removed. It is recommended that the VBAT pin always be supplied with voltage from either VDD or a backup battery source during programming. TABLE 2-1: VSS Writing to a location multiple times without erasing is not recommended. PIN DESCRIPTIONS (DURING PROGRAMMING) Pin Name During Programming Pin Name Pin Type Pin Description MCLR P Programming Enable VDD, AVDD(1) VDD P Power Supply VSS, AVSS(1) VBAT(2) VSS P Ground VBAT P VBAT Mode Power Supply MCLR VCAP VCAP P On-Chip Voltage Regulator Output to the Core PGECx I Programming Pin Pairs 1, 2 and 3: Serial Clock PGEDx PGEDX I/O VUSB3V3(3) VUSB3V3 P PGECx Programming Pin Pairs 1, 2 and 3: Serial Data USB Transceiver Power Input Voltage (3.3V nominal) Legend: I = Input, O = Output, P = Power 1: All power supply and ground pins must be connected, including analog supplies and ground (AVDD/AVSS are implemented). 2: It is recommended to connect the VBAT pin to the battery or VDD during programming. 3: This pin is available only in the PIC24FJXXXGB2XX family devices. DS30000510F-page 2 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 2.3 Pin Diagrams 2.3.1 All of the PIC24FJXXXGA2/GB2 devices have three separate pairs of programming pins, labeled as PGEC1/PGED1, PGEC2/PGED2 and PGEC3/PGED3. Any one of these pin pairs may be used for device programming by either the ICSP or Enhanced ICSP method. Unlike voltage supply and ground pins, it is not necessary to connect all three pin pairs to program the device. However, the programming method must use both pins of the same pair. Figure 2-3 through Figure 2-6 provide the pin diagrams for the PIC24FJXXXGA2/GB2 devices. The pins that are required for programming are listed in Table 2-1 and are shown in bold type in the figures. Refer to the specific device data sheet for complete pin descriptions. MCLR RA0 RA1 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 RB2 RB3 VSS RA2 RA3 RB4 RA4 VDD PGED3/RP5/ASDA1/CN27/RB5 MCLR PGED3/RA0 PGEC3/RA1 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 RB2 RB3 VSS RA2 RA3 RB4 RA4 VDD RB5 2012-2015 Microchip Technology Inc. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC24FJXXXGA202 PIN DIAGRAMS (28-PIN PDIP/SSOP/SOIC) PIC24FJXXXGB202 FIGURE 2-3: PGECx AND PGEDx PIN PAIRS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS RB15 RB14 RB13 RB12 PGEC2/TMS/RP11/CN15/RB11 PGED2/TDI/RP10/CN16/RB10 VCAP VBAT RB9 RB8 RB7 PGEC3/RP6/ASCL1/CN24/RB6 VDD VSS RB15 RB14 RB13 VUSB3V3 PGEC2/REFI/RP11/D-/CTED9/CN15/RB11 PGED2/RP10/D+/CTED11/CN16/RB10 VCAP VBAT RB9 RB8 RB7 VBUS/RB6 DS30000510F-page 3 PIC24FJXXXGA2/GB2 FAMILIES PIN DIAGRAMS (28-PIN QFN)(1) RA1 RA0 MCLR VDD VSS RB15 RB14 FIGURE 2-4: 28 27 26 25 24 23 22 1 21 RB13 2 20 RB12 3 19 PGEC2/TMS/RP11/CN15/RB11 4 PIC24FJXXXGA202 18 PGED2/TDI/RP10/CN16/RB10 5 17 VCAP 6 16 VBAT 7 15 RB9 8 9 10 11 12 13 14 PGEC3/CVREF-/VREF-/AN1/C3IND/RP6/ASCL1/CTED2/CN3/RA1 PGED3/CVREF+/VREF+/AN0/C3INC/RP5/ASDA1/CTED1/CN2/RA0 MCLR VDD VSS RB15 RB14 RB4 RA4 VDD PGED3/CN27/RB5 PGEC3/CN24/RB6 RB7 RB8 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 RB2 RB3 VSS RA2 RA3 28 27 26 25 24 23 22 1 21 2 20 3 19 PIC24FJXXXGB202 18 4 5 17 6 16 7 15 8 9 10 11 12 13 14 RB13 VUSB3V3 PGEC2/REFI/RP11/D-/CTED9/CN15/RB11 PGED2/RP10/D+/CTED11/CN16/RB10 VCAP VBAT RB9 RB4 RA4 VDD RB5 VBUS/RB6 RB7 RB8 PGED1/AN2/CTCMP/HLVDIN/C2INB/RP0/CN4/RB0 PGEC1/AN3/C2INA/RP1/CTED12/CN5/RB1 RB2 RB3 VSS RA2 RA3 Note 1: The bottom pad of QFN packages should be connected to VSS. DS30000510F-page 4 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES PIN DIAGRAMS (44-PIN QFN)(1) 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 PGEC3/RB6 PGED3/RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 FIGURE 2-5: 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 PIC24FJXXXGA204 7 8 9 10 11 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 VBUS/RB6 RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 RA10 RA7 RB14 RB15 AVSS AVDD MCLR RA0 RA1 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 RB9 RC6 RC7 RC8 RC9 VBAT VCAP PGED2/RP10/CN16/PMD2/RB10 PGEC2/RP11/CN15/PMD1/RB11 RB12 RB13 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 PIC24FJXXXGB204 6 7 8 9 10 11 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 RA10 RA7 RB14 RB15 AVSS AVDD MCLR PGED3/CVREF+/AN0/C3INC/CN2/RA0 PGEC3/CVREF-/AN1/C3IND/CN3/RA1 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 RB9 RC6 RC7 RC8 RC9 VBAT VCAP PGED2/RP10/CN16/D+/RB10 PGEC2/RP11/CN15/D-/RB11 VUSB3V3 RB13 Note 1: The bottom pad of QFN packages should be connected to VSS. 2012-2015 Microchip Technology Inc. DS30000510F-page 5 PIC24FJXXXGA2/GB2 FAMILIES PIN DIAGRAMS (44-PIN TQFP) 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 PGEC3/RB6 PGED3/RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 FIGURE 2-6: PIC24FJXXXGA204 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 VBUS/RB6 RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 RA10 RA7 RB14 RB15 AVSS AVDD MCLR RA0 RA1 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 RB9 RC6 RC7 RC8 RC9 VBAT VCAP PGED2/RP10/CN16/PMD2/RB10 PGEC2/RP11/CN15/PMD1/RB11 RB12 RB13 PIC24FJXXXGB204 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 RA10 RA7 RB14 RB15 AVSS AVDD MCLR PGED3/CVREF+/AN0/C3INC/CN2/RA0 PGEC3/CVREF-/AN1/C3IND/CN3/RA1 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 RB9 RC6 RC7 RC8 RC9 VBAT VCAP PGED2/RP10/CN16/D+/RB10 PGEC2/RP11/CN15/D-/RB11 VUSB3V3 RB13 DS30000510F-page 6 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 2.4 Memory Map The program memory map extends from 000000h to FFFFFEh. Code storage is located at the base of the memory map and supports up to 87K instruction words (about 256 Kbytes). Table 2-2 shows the program memory sizes, and the number of erase and program blocks present in each device variant. Each erase block or page contains 512 instructions and each program block or row contains 64 instructions. Locations, 800000h through 8007FEh, are reserved for executive code memory. This region stores the Programming Executive and the Debugging Executive. The Programming Executive is used for device programming and the Debugging Executive is used for in-circuit debugging. This region of memory cannot be used to store user code. TABLE 2-2: The last four implemented program memory locations are reserved for the Flash Configuration Words. The reserved addresses are provided in Table 2-2. Locations, FF0000h and FF0002h, are reserved for the Device ID registers. These bits can be used by the programmer to identify what device type is being programmed. They are described in Section 6.1 “Device ID”. The Device ID registers read out normally, even after code protection is applied. Figure 2-7 displays the memory PIC24FJXXXGA2/GB2 devices. map for the CODE MEMORY SIZE AND FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJXXXGA2/GB2 DEVICES Device PIC24FJ64GA2XX PIC24FJ64GB2XX PIC24FJ128GA2XX PIC24FJ128GB2XX User Memory Address Limit (Instruction Words) Write Blocks Erase Blocks 1 2 00ABFEh (22K) 344 43 00ABFEh 00ABFCh 00ABFAh 00ABF8h 0157FEh (44K) 688 86 0157FEh 0157FCh 0157FAh 0157F8h 2012-2015 Microchip Technology Inc. Configuration Word Addresses 3 4 DS30000510F-page 7 PIC24FJXXXGA2/GB2 FAMILIES FIGURE 2-7: PROGRAM MEMORY MAP 000000h User Flash Code Memory(1) User Memory Space Flash Configuration Words 0XXXF7h(1) 0XXXF8h(1) 0XXXFEh(1) 0XXX00h(1) Reserved 7FFFFEh 800000h Executive Code Memory (1024 x 24-bit) 8007FEh 800800h Configuration Memory Space Reserved Memory Diagnostic and Calibration Words (8 x 24-bit) 8008FEh 800880h 80088Eh Reserved Device ID (2 x 16-bit) Reserved Note 1: FEFFFEh FF0000h FF0002h FF0004h FFFFFEh The size and address boundaries for user Flash code memory are device dependent. See Table 2-2 for details. DS30000510F-page 8 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 3.0 DEVICE PROGRAMMING – ICSP FIGURE 3-1: ICSP mode is a special programming protocol that allows you to read and write to the memory of PIC24FJXXXGA2/GB2 devices. The ICSP mode is the most direct method used to program the device; note however, that Enhanced ICSP is faster. ICSP mode also has the ability to read the contents of executive memory to determine if the Programming Executive is present. This capability is accomplished by applying control codes and instructions, serially to the device, using pins, PGECx and PGEDx. Start Enter ICSP™ Perform Chip Erase In ICSP mode, the system clock is taken from the PGECx pin, regardless of the device’s Oscillator Configuration bits. All instructions are shifted serially into an internal buffer, then loaded into the Instruction Register (IR) and executed. No program fetching occurs from internal memory. Instructions are fed in, 24 bits at a time. PGEDx is used to shift data in, and PGECx is used as both the serial shift clock and the CPU execution clock. Note: 3.1 Program Memory Verify Program Program Configuration Bits During ICSP operation, the operating frequency of PGECx must not exceed 10 MHz. Verify Configuration Bits Exit ICSP Overview of the Programming Process Figure 3-1 shows the high-level overview of the programming process. After entering ICSP mode, the first action is to Chip Erase the device. Next, the code memory is programmed, followed by the device Configuration registers. Code memory (including the Configuration registers) is then verified to ensure that programming was successful. Then, the code-protect Configuration bits are programmed, if required. HIGH-LEVEL ICSP™ PROGRAMMING FLOW End 3.2 ICSP Operation Upon entry into ICSP mode, the CPU is Idle. Execution of the CPU is governed by an internal state machine. A 4-bit control code is clocked in using PGECx and PGEDx, and this control code is used to command the CPU (see Table 3-1). The SIX control code is used to send instructions to the CPU for execution and the REGOUT control code is used to read data out of the device via the VISI register. TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE 4-Bit Mnemonic Control Code 0000 SIX 0001 REGOUT 0010-1111 2012-2015 Microchip Technology Inc. N/A Description Shift in 24-bit instruction and execute. Shift out the VISI (0784h) register. Reserved. DS30000510F-page 9 PIC24FJXXXGA2/GB2 FAMILIES 3.2.1 SIX SERIAL INSTRUCTION EXECUTION Coming out of Reset, the first 4-bit control code is always forced to SIX and a forced NOP instruction is executed by the CPU. Five additional PGECx clocks are needed on start-up, resulting in a 9-bit SIX command instead of the normal 4-bit SIX command. The SIX control code allows execution of PIC24F assembly instructions. When the SIX code is received, the CPU is suspended for 24 clock cycles, as the instruction is then clocked into the internal buffer. Once the instruction is shifted in, the state machine allows it to be executed over the next four PGECx clock cycles. While the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see Figure 3-2). FIGURE 3-2: After the forced SIX is clocked in, ICSP operation resumes as normal. That is, the next 24 clock cycles load the first instruction word to the CPU. Note: To account for this forced NOP, all example code in this specification begins with a NOP to ensure that no data is lost. SIX SERIAL EXECUTION P1 1 2 PGECx 3 4 5 6 7 8 9 1 P4 P3 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 1 2 3 4 0 0 0 0 P4A P1A P1B P2 0 PGEDx 0 0 0 0 Execute PC – 1, Fetch SIX Control Code 0 0 0 0 LSB X X X X X X X X X X X X X X MSB 24-Bit Instruction Fetch Execute 24-Bit Instruction, Fetch Next Control Code Only for Program Memory Entry PGEDx = Input 3.2.1.1 Differences Between Execution of SIX and Normal Instructions There are some differences between executing instructions normally and using the SIX ICSP command. As a result, the code examples in this specification may not match those for performing the same functions during normal device operation. During SIX ICSP operation: • Two-word instructions require two SIX operations to clock in all of the necessary data. Examples of two-word instructions are GOTO and CALL. • Two-cycle instructions require two SIX operations. The first SIX operation shifts in the instruction and begins to execute it. The second SIX operation, which should shift in a NOP to avoid losing data, provides the CPU clocks required to finish executing the instruction. Examples of two-cycle instructions are Table Read and Table Write instructions. • The CPU does not automatically stall to account for pipeline changes. A CPU Stall occurs when an instruction modifies a register that is used for Indirect Addressing by the following instruction. DS30000510F-page 10 During normal device operation: • The CPU will automatically force a NOP while the new data is read. When using ICSP, there is no automatic stall, so any indirect references to a recently modified register should be preceded by a NOP. For example, the instructions, MOV #0x0,W0 and MOV [W0],W1, must have a NOP inserted between them. If a two-cycle instruction modifies a register that is used indirectly, it will require two NOPs: one to execute the second half of the instruction and the other to stall the CPU to correct the pipeline. Instructions, such as TBLWTL [W0++], [W1], should be followed by two NOPs. • The device Program Counter (PC) continues to automatically increment during ICSP instruction execution, even though the Flash memory is not being used. As a result, the PC may be incremented to point to invalid memory locations. Invalid memory spaces include unimplemented Flash addresses and the vector space (locations: 0x0 to 0x1FF). If the PC points to these locations, the device will reset, possibly interrupting the ICSP operation. To prevent this, instructions should be periodically executed to reset the PC to a safe space. The optimal method to accomplish this is to perform a GOTO 0x200. 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 3.2.2 REGOUT SERIAL INSTRUCTION EXECUTION Note 1: After the contents of VISI are shifted out, PIC24FJXXXGA2/GB2 devices maintain PGEDx as an output until the first rising edge of the next clock is received. The REGOUT control code allows for data to be extracted from the device in ICSP mode. It is used to clock the contents of the VISI register, out of the device, over the PGEDx pin. After the REGOUT control code is received, the CPU is held Idle for 8 cycles. After these 8 cycles, an additional 16 cycles are required to clock the data out (see Figure 3-3). 2: Data changes on the falling edge and latches on the rising edge of PGECx. For all data transmissions, the Least Significant bit (LSb) is transmitted first. The REGOUT code is unique because the PGEDx pin is an input when the control code is transmitted to the device. However, after the control code is processed, the PGEDx pin becomes an output as the VISI register is shifted out. FIGURE 3-3: 1 REGOUT SERIAL EXECUTION 2 3 4 1 2 7 8 1 2 3 4 5 6 11 12 13 14 15 16 1 2 3 4 PGECx P4 PGEDx 1 0 0 LSb 0 Execute Previous Instruction, Fetch REGOUT Control Code P4A P5 CPU Held in Idle PGEDx = Input 2012-2015 Microchip Technology Inc. 1 2 3 4 ... 10 11 12 13 14 MSb Shift Out VISI Register<15:0> PGEDx = Output 0 0 0 0 No Execution Takes Place, Fetch Next Control Code PGEDx = Input DS30000510F-page 11 PIC24FJXXXGA2/GB2 FAMILIES 3.3 Entering ICSP Mode The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0001’ (more easily remembered as 4D434851h in hexadecimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. As shown in Figure 3-4, entering ICSP Program/Verify mode requires three steps: 1. 2. 3. MCLR is briefly driven high, then low. A 32-bit key sequence is clocked into PGEDx. MCLR is then driven high within a specified period and held. Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as Program/Verify mode is to be maintained. An interval of at least time, P19 and P7, must elapse before presenting data on PGEDx. Signals appearing on PGECx before P7 has elapsed will not be interpreted as valid. The programming voltage applied to MCLR is VIH, which is essentially VDD in the case of PIC24FJXXXGA2/GB2 devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGEDx. FIGURE 3-4: P6 On successful entry, the program memory can be accessed and programmed in serial fashion. While in ICSP mode, all unused I/Os are placed in the high-impedance state. ENTERING ICSP™ MODE P14 MCLR P19 VDD P7 VIH VIH Program/Verify Entry Code = 4D434851h PGEDx 0 b31 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 1 b0 PGECx P18 DS30000510F-page 12 P1A P1B 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 3.4 Flash Memory Programming in ICSP Mode 3.4.1 PROGRAMMING OPERATIONS Flash memory write and erase operations are controlled by the NVMCON register. Programming is performed by setting NVMCON to select the type of erase operation (see Table 3-2) or write operation (see Table 3-3) and initiating the programming by setting the WR control bit (NVMCON<15>). In ICSP mode, all programming operations are self-timed. There is an internal delay between the user setting the WR control bit and the automatic clearing of the WR control bit when the programming operation is complete. For information about the delays associated with various programming operations, refer to Section 7.0 “AC/DC Characteristics and Timing Requirements”. TABLE 3-2: NVMCON Value NVMCON ERASE OPERATIONS Erase Operation 404Fh Erase all code memory, executive memory and Configuration registers (does not erase Device ID registers). 4042h Erase a page of code memory or executive memory. TABLE 3-3: NVMCON Value 4003h 4001h 3.4.2 NVMCON WRITE OPERATIONS Erasing Program Memory The procedure for erasing program memory (all of the code memory, data memory, executive memory and code-protect bits) consists of setting NVMCON to 404Fh and executing the programming cycle. A Chip Erase can erase all of the user memory or both the user and configuration memory. A Table Write instruction should be executed, prior to performing the Chip Erase, to select which sections are erased. The Table Write instruction is executed: • If the TBLPAG register points to user space (is less than 80h), the Chip Erase will erase only user memory and Flash Configuration Words. • If the TBLPAG register points to configuration space (is greater than or equal to 80h), the Chip Erase is not allowed. The configuration space can be erased, one page at a time. Note: The Chip Erase is not allowed when the TBLPAG points to the configuration space to avoid the diagnostic and calibration words from getting erased. Figure 3-5 displays the ICSP programming process for performing a Chip Erase. This process includes the ICSP command code, which must be transmitted (for each instruction), LSb first, using the PGECx and PGEDx pins (see Figure 3-2). Note: Program memory must be erased before writing any data to program memory. FIGURE 3-5: CHIP ERASE FLOW Write Operation Start Write a single code memory word, Configuration Word or executive memory word. Program 1 row (64 instruction words) of code memory or executive memory. STARTING AND STOPPING A PROGRAMMING CYCLE The WR bit (NVMCON<15>) is used to start an erase or write cycle. Setting the WR bit initiates the programming cycle. All erase and write cycles are self-timed. The WR bit should be polled to determine if the erase or write cycle has been completed. Starting a programming cycle is performed as follows: BSET 3.5 Write 404Fh to NVMCON SFR Set the WR bit to Initiate Erase No Is WR bit cleared (‘0’)? Yes End NVMCON, #WR 2012-2015 Microchip Technology Inc. DS30000510F-page 13 PIC24FJXXXGA2/GB2 FAMILIES TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE Command (Binary) Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Set the NVMCON register to erase all program memory. 0000 0000 2404FA 883B0A MOV MOV #0x404F, W10 W10, NVMCON Step 3: Set the TBLPAG register and perform a dummy Table Write to select what portions of memory are erased. 0000 0000 0000 0000 0000 0000 2xxxx0 8802A0 200000 BB0800 000000 000000 MOV MOV MOV TBLWTL NOP NOP #<PAGEVAL>, W0 W0, TBLPAG #0x0000, W0 W0,[W0] BSET NOP NOP NVMCON, #WR Step 4: Initiate the erase cycle. 0000 0000 0000 A8E761 000000 000000 Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 DS30000510F-page 14 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register NOP 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 3.6 Writing Code Memory The procedure for writing code memory is the same as the procedure for writing the Configuration registers, except that 64 instruction words are programmed at a time. To facilitate this operation, Working registers, W0:W5, are used as temporary holding registers for the data to be programmed. Table 3-5 provides the ICSP programming details, including the serial pattern with the ICSP command code which must be transmitted, LSb first, using the PGECx and PGEDx pins (see Figure 3-2). In Step 1, the Reset vector is exited. In Step 2, the NVMCON register is initialized for programming a full row of code memory. In Step 3, the 24-bit starting destination address for programming is loaded into the TBLPAG register and W7 register. (The upper byte of the starting destination address is stored in TBLPAG and the lower 16 bits of the destination address are stored in W7.) In Step 5, eight TBLWT instructions are used to copy the data from W0:W5 to the write latches of code memory. Since code memory is programmed, 64 instruction words at a time, Steps 4 and 5 are repeated, 16 times, to load all the write latches (Step 6). After the write latches are loaded, programming is initiated by writing to the NVMCON register in Steps 7 and 8. In Step 9, the internal PC is reset to 200h. This is a precautionary measure to prevent the PC from incrementing into unimplemented memory when large devices are being programmed. Lastly, in Step 10, Steps 3-9 are repeated until all of the code memory is programmed. FIGURE 3-6: PACKED INSTRUCTION WORDS IN W0:W5 15 8 7 W0 LSW0 To minimize the programming time, a packed instruction format is used (see Figure 3-6). W1 W2 LSW1 In Step 4, four packed instruction words are stored in Working registers, W0:W5, using the MOV instruction. The Read Pointer, W6, is initialized. The contents of W0:W5 (holding the packed instruction word data) are shown in Figure 3-6. W3 LSW2 TABLE 3-5: Command (Binary) W4 0 MSB1 MSB0 MSB3 W5 MSB2 LSW3 SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Set the NVMCON register to program 64 instruction words. 0000 0000 24001A 883B0A MOV MOV #0x4001, W10 W10, NVMCON Step 3: Initialize the Write Pointer (W7) for the TBLWT instruction. 0000 0000 0000 200xx0 8802A0 2xxxx7 MOV MOV MOV #<DestinationAddress23:16>, W0 W0, TBLPAG #<DestinationAddress15:0>, W7 Step 4: Load W0:W5 with the next 4 instruction words to program. 0000 0000 0000 0000 0000 0000 2xxxx0 2xxxx1 2xxxx2 2xxxx3 2xxxx4 2xxxx5 MOV MOV MOV MOV MOV MOV 2012-2015 Microchip Technology Inc. #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3>, W5 DS30000510F-page 15 PIC24FJXXXGA2/GB2 FAMILIES TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED) Command (Binary) Data (Hex) Description Step 5: Set the Read Pointer (W6) and load the (next set of) write latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0300 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 CLR NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL NOP NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL NOP NOP W6 [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] Step 6: Repeat Steps 4 and 5, 16 times, to load the write latches for 64 instructions. Step 7: Initiate the write cycle. 0000 0000 0000 A8E761 000000 000000 BSET NOP NOP NVMCON, #WR Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP Step 9: Reset the device’s internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 10: Repeat Steps 3 through 9 until all code memory is programmed. DS30000510F-page 16 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES FIGURE 3-7: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes Load 1 Instruction Word Write Buffer at <Addr> N=N+1 No All instruction words written? Yes N=1 LoopCount = LoopCount + 1 Start Write Sequence and Poll for WR bit to be Cleared No All locations done? Yes End 2012-2015 Microchip Technology Inc. DS30000510F-page 17 PIC24FJXXXGA2/GB2 FAMILIES 3.7 Writing Configuration Words Device configuration for PIC24FJXXXGA2/GB2 devices is stored in the Flash Configuration Words at the end of the user space program memory and in multiple Configuration Word registers located in the test space. These registers reflect values read at any Reset from program memory locations. The values for the Configuration Words for the default device configurations are listed in Table 3-6. TABLE 3-6: DEFAULT CONFIGURATION REGISTER VALUES Address Name Default Value Last Word CW1 7FFFh Last Word – 2 CW2 BFFFh(1) Last Word – 4 CW3 FFFFh Last Word – 6 CW4 FFFFh Note 1: To change the values of the Flash Configuration Word once it has been programmed, the device must be Chip Erased, as described in Section 3.5 “Erasing Program Memory”, and reprogrammed to the desired value. It is not possible to program a ‘0’ to a ‘1’; a ‘1’ to a ‘0’ may be programmed to enable code protection. Table 3-8 provides the ICSP programming details for programming the Configuration Word locations. This includes the serial pattern with the ICSP command code which must be transmitted, LSb first, using the PGECx and PGEDx pins (see Figure 3-2). In Step 1, the Reset vector is exited. In Step 2, the lower 16 bits of the source address are stored in W7. In Step 3, the NVMCON register is initialized for programming of code memory. In Step 4, the upper byte of the 24-bit starting source address for writing is loaded into the TBLPAG register. The TBLPAG register must be loaded with 00h for 64 Kbytes, and 01h for 128-Kbyte and 256-Kbyte devices. For the PIC24FJXXXGB2 family, the default value is BFFFh. For the PIC24FJXXXGA2 family, the default value is B7FFh. The values can be changed only by programming the content of the corresponding Flash Configuration Word and resetting the device. The Reset forces an automatic reload of the Flash stored configuration values by sequencing through the dedicated Flash Configuration Words and transferring the data into the Configuration registers. To verify the data by reading the Configuration Words after performing the write in order, the code protection bits should initially be programmed to a ‘1’ to ensure that the verification can be performed properly. After verification is finished, the code protection bit can be programmed to a ‘0’ by using a word write to the appropriate Configuration Word. For the PIC24FJXXXGA2/GB2 devices, certain reserved Configuration bits have default states that must always be maintained to ensure device functionality, regardless of the settings of other Configuration bits. These bits and their values are listed in Table 3-7. TABLE 3-7: RESERVED CONFIGURATION BIT LOCATIONS Family All Devices PIC24FJXXGA2XX DS30000510F-page 18 Register/Bits Value Comments CW1<15> 0 Always program as ‘0’; required to maintain device functionality. CW2<2> 1 Always program as ‘1’. CW2<14> 0 Always program as ‘0’. CW3<7> 1 Always program as ‘1’. CW4<9> 1 Always program as ‘1’. CW2<11> 0 Always program as ‘0’. 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES TABLE 3-8: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction. 0000 2xxxx7 MOV #<CW1Address15:0>, W7 Step 3: Set the NVMCON register to program CW1. 0000 0000 24003A 883B0A MOV MOV #0x4003, W10 W10, NVMCON Step 4: Initialize the TBLPAG register. 0000 0000 200xx0 8802A0 MOV MOV #<CW1Address23:16>, W0 W0, TBLPAG Step 5: Load the Configuration register data to W6. 0000 2xxxx6 MOV #<CW1_VALUE>, W6 Step 6: Write the Configuration register data to the write latch and decrement the Write Pointer. 0000 0000 0000 0000 0000 0000 0000 0000 200008 000000 BBCB88 000000 000000 BB1386 000000 000000 MOV NOP TBLWTH.B NOP NOP TBLWTL.W NOP NOP #0x0000, W8 BSET NOP NOP NVMCON, #WR W8, [W7] W6, [W7--] Step 7: Initiate the write cycle. 0000 0000 0000 A8E761 000000 000000 Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO NOP MOV MOV NOP Clock out NOP 0x200 NVMCON, W2 W2, VISI contents of the VISI register. Step 9: Reset the device’s internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 10: Repeat Steps 5 through 9 to write Configuration Word 2 to Configuration Word 4. 2012-2015 Microchip Technology Inc. DS30000510F-page 19 PIC24FJXXXGA2/GB2 FAMILIES 3.8 Reading Code Memory Reading from code memory is performed by executing a series of TBLRD instructions and clocking out the data using the REGOUT command. Table 3-9 provides the ICSP programming details for reading code memory. In Step 1, the Reset vector is exited. In Step 2, the Write Pointer, W7, is initialized. In Step 3, the 24-bit starting source address for reading is loaded into the TBLPAG and W6 registers. The upper byte of the starting source address is stored in TBLPAG and the lower 16 bits of the source address are stored in W6. TABLE 3-9: To minimize the reading time, the packed instruction word format that was utilized for writing is also used for reading (see Figure 3-6). In Step 4, two instruction words are read from code memory and clocked out of the device, through the VISI register, using the REGOUT command. Step 4 is repeated until the desired amount of code memory is read. SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY Command (Binary) Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize the Write Pointer (W7) to point to the VISI register. 0000 0000 207847 000000 MOV NOP #VISI, W7 Step 3: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction. 0000 0000 0000 200xx0 8802A0 2xxxx6 MOV MOV MOV #<SourceAddress23:16>, W0 W0, TBLPAG #<SourceAddress15:0>, W6 Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using the REGOUT command. 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0001 0000 BA0B96 000000 000000 <VISI> 000000 BADBB6 000000 000000 BAD3D6 000000 000000 <VISI> 000000 BA0BB6 000000 000000 <VISI> 000000 TBLRDL NOP NOP Clock out NOP TBLRDH.B NOP NOP TBLRDH.B NOP NOP Clock out NOP TBLRDL NOP NOP Clock out NOP [W6], [W7] contents of the VISI register [W6++], [W7++] [++W6], [W7--] contents of the VISI register [W6++], [W7] contents of the VISI register Step 5: Reset the device’s internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 6: Repeat Steps 3 through 5 until all desired code memory is read (note that “Reset the device’s internal PC” will be Step 5). DS30000510F-page 20 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 3.9 Reading Configuration Words The procedure for reading configuration memory is similar to the procedure for reading code memory, except that 16-bit data words are read instead of 24-bit words. Configuration Words are read, one register at a time. TABLE 3-10: Command (Binary) Table 3-10 provides the ICSP programming details for reading the Configuration Words. Note that the TBLPAG register must be loaded with 00h for 64 Kbytes, and 01h for 128-Kbyte and 256-Kbyte devices. W6 is initialized to the lower 16 bits of the Configuration Word location. SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize the TBLPAG register, the Read Pointer (W6) and the Write Pointer (W7) for the TBLRD instruction. 0000 0000 0000 0000 0000 200xx0 8802A0 2xxxx6 207847 000000 MOV MOV MOV MOV NOP #<CW1Address23:16>, W0 W0, TBLPAG #<CW1Address15:0>, W6 #VISI, W7 Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the VISI register using the REGOUT command. 0000 0000 0000 0001 0000 BA0BA6 000000 000000 <VISI> 000000 TBLRDL [W6--], [W7] NOP NOP Clock out contents of the VISI register NOP Step 4: Repeat Step 3 to read Configuration Word 2 to Configuration Word 4. Step 5: Reset the device’s internal PC. 0000 0000 040200 000000 GOTO NOP 2012-2015 Microchip Technology Inc. 0x200 DS30000510F-page 21 PIC24FJXXXGA2/GB2 FAMILIES 3.10 Verify Code Memory and Configuration Word The verify step involves reading back the code memory space and comparing it with the copy held in the programmer’s buffer. The Configuration registers are verified with the rest of the code. The verify process is shown in the flowchart in Figure 3-8. Memory reads occur, a single byte at a time, so two bytes must be read to compare against the word in the programmer’s buffer. Refer to Section 3.8 “Reading Code Memory” for implementation details of reading code memory. Note: Because the Configuration registers include the device code protection bit, code memory should be verified immediately after writing if code protection is enabled. This is because the device will not be readable or verifiable if a device Reset occurs after the code-protect bit in CW1 has been cleared. FIGURE 3-8: VERIFY CODE MEMORY FLOW 3.11 Reading the Application ID Word The Application ID Word is stored at address, 8007F0h, in executive code memory. To read this memory location, you must use the SIX control code to move this program memory location to the VISI register. Then, the REGOUT control code must be used to clock the contents of the VISI register out of the device. Table 3-11 provides the corresponding control and instruction codes that must be serially transmitted to the device to perform this operation. After the programmer has clocked out the Application ID Word, it must be inspected. If the Application ID has the value, CEh, the Programming Executive is resident in memory and the device can be programmed using the mechanism described in Section 4.0 “Device Programming – Enhanced ICSP”. However, if the Application ID has any other value, the Programming Executive is not resident in memory; it must be loaded to memory before the device can be programmed. The procedure for loading the Programming Executive to memory is described in Section 5.4 “Programming the Programming Executive to Memory”. 3.12 Exiting ICSP Mode Exiting Program/Verify mode is done by removing VIH from MCLR, as shown in Figure 3-9. The only requirement for exit is that an interval, P16, should elapse between the last clock, and program signals on PGECx and PGEDx, before removing VIH. Start Set TBLPTR = 0 FIGURE 3-9: EXITING ICSP™ MODE P16 Read Low Byte with Post-Increment P17 VIH MCLR Read High Byte with Post-Increment VDD VIH PGEDx Does Word = Expect Data? Yes No No Failure, Report Error PGECx PGEDx = Input All code memory verified? Yes End DS30000510F-page 22 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES TABLE 3-11: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize the TBLPAG register and the Read Pointer (W0) for the TBLRD instruction. 0000 0000 0000 0000 0000 0000 0000 0000 200800 8802A0 207F00 207841 000000 BA0890 000000 000000 MOV MOV MOV MOV NOP TBLRDL NOP NOP #0x80, W0 W0, TBLPAG #0x07F0, W0 #VISI, W1 [W0], [W1] Step 3: Output the VISI register using the REGOUT command. 0001 0000 <VISI> 000000 Clock out contents of the VISI register NOP 2012-2015 Microchip Technology Inc. DS30000510F-page 23 PIC24FJXXXGA2/GB2 FAMILIES 4.0 DEVICE PROGRAMMING – ENHANCED ICSP This section discusses programming the device through Enhanced ICSP and the Programming Executive. The Programming Executive resides in executive memory (separate from code memory) and is executed when Enhanced ICSP Programming mode is entered. The Programming Executive provides the mechanism for the programmer (host device) to program and verify the PIC24FJXXXGA2/GB2 devices, using a simple command set and communication protocol. There are several basic functions provided by the Programming Executive: • • • • • After the Programming Executive has been verified in memory (or loaded if not present), the PIC24FJXXXGA2/GB2 devices can be programmed using the command set provided in Table 4-1. FIGURE 4-1: Start Enter Enhanced ICSP™ Perform Chip Erase Read Memory Erase Memory Program Memory Blank Check Read Executive Firmware Revision Program Memory The Programming Executive performs the low-level tasks required for erasing, programming and verifying a device. This allows the programmer to program the device by issuing the appropriate commands and data. Table 4-1 summarizes the commands. A detailed description for each command is provided in Section 5.2 “Programming Executive Commands”. TABLE 4-1: COMMAND SET SUMMARY Command Description SCHECK Sanity Check READC Read Device ID Registers READP Read Code Memory PROGP Program One Row of Code Memory and Verify PROGW Program One Word of Code Memory and Verify QBLANK Query if the Code Memory is Blank QVER Query the Software Version The Programming Executive uses the device’s data RAM for variable storage and program execution. After the Programming Executive has run, no assumptions should be made about the contents of data RAM. 4.1 Overview of the Programming Process Figure 4-1 shows the high-level overview of the programming process. After entering Enhanced ICSP mode, the Programming Executive is verified. Next, the device is erased. Then, the code memory is programmed, followed by the configuration locations. Code memory (including the Configuration registers) is then verified to ensure that programming was successful. DS30000510F-page 24 HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW Verify Program Program Configuration Bits Verify Configuration Bits Exit Enhanced ICSP End 4.2 Confirming the Presence of the Programming Executive Before programming can begin, the programmer must confirm that the Programming Executive is stored in executive memory. The procedure for this task is shown in Figure 4-2. First, ICSP mode is entered. Then, the unique Application ID Word stored in executive memory is read. If the Programming Executive is resident, the Application ID Word is CEh, which means programming can resume as normal. However, if the Application ID Word is not CEh, the Programming Executive must be programmed to executive code memory using the method described in Section 5.4 “Programming the Programming Executive to Memory”. Section 3.0 “Device Programming – ICSP” describes the ICSP programming method. Section 3.11 “Reading the Application ID Word” describes the procedure for reading the Application ID Word in ICSP mode. 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES FIGURE 4-2: 4.3 CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE Entering Enhanced ICSP Mode As shown in Figure 4-3, entering Enhanced ICSP Program/Verify mode requires three steps: 1. 2. 3. Start Enter ICSP™ Mode The MCLR pin is briefly driven high, then low. A 32-bit key sequence is clocked into PGEDx. MCLR is then driven high within a specified period and held. The programming voltage applied to MCLR is VIH, which is essentially VDD in the case of PIC24FJXXXGA2/GB2 devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGEDx. Read the Application ID from Address 8007F0h Is Application ID CEh? The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0000’ (more easily remembered as 4D434850h in hexadecimal format). The device will enter Program/Verify mode only if the key sequence is valid. The MSb of the most significant nibble must be shifted in first. No Yes Prog. Executive is Resident in Memory Prog. Executive must be Programmed Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as Program/Verify mode is to be maintained. An interval of at least time, P19 and P7, must elapse before presenting data on PGEDx. Signals appearing on PGEDx, before P7 has elapsed, will not be interpreted as valid. End On successful entry, the program memory can be accessed and programmed in serial fashion. While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state. FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE P6 P14 MCLR P19 VDD P7 VIH VIH Program/Verify Entry Code = 4D434850h PGEDx 0 b31 1 b30 0 b29 0 b28 1 ... b27 0 b3 0 b2 0 b1 0 b0 PGECx P18 2012-2015 Microchip Technology Inc. P1A P1B DS30000510F-page 25 PIC24FJXXXGA2/GB2 FAMILIES 4.4 Blank Check FIGURE 4-4: FLOWCHART FOR PROGRAMMING CODE MEMORY The term, “Blank Check”, implies verifying that the device has been successfully erased and has no programmed memory locations. A blank or erased memory location is always read as ‘1’. Start The Device ID registers (FF0002h:FF0000h) can be ignored by the Blank Check since this region stores device information that cannot be erased. The device Configuration registers are also ignored by the Blank Check. Additionally, all unimplemented memory space should be ignored by the Blank Check. BaseAddress = 00h RemainingCmds = 1368 Send PROGP Command to Program BaseAddress The QBLANK command is used for the Blank Check. It determines if the code memory is erased by testing these memory regions. A ‘BLANK’ or ‘NOT BLANK’ response is returned. If it is determined that the device is not blank, it must be erased before attempting to program the chip. 4.5 4.5.1 Is PROGP Response PASS? Code Memory Programming Yes PROGRAMMING METHODOLOGY Code memory is programmed with the PROGP command. PROGP programs one row of code memory, starting from the memory address specified in the command. The number of PROGP commands required to program a device depends on the number of write blocks that must be programmed in the device. A flowchart for programming the code memory of the PIC24FJXXXGA2/GB2 devices is shown in Figure 4-4. In this example, all 87K instruction words of a 256-Kbyte device are programmed. First, the number of commands to send (called ‘RemainingCmds’ in the flowchart) is set to 1368 and the destination address (called ‘BaseAddress’) is set to ‘0’. Next, one write block in the device is programmed with a PROGP command. Each PROGP command contains data for one row of code memory of the device. After the first command is processed successfully, ‘RemainingCmds’ is decremented by 1 and compared with 0. Since there are more PROGP commands to send, ‘BaseAddress’ is incremented by 80h to point to the next row of memory. On the second PROGP command, the second row is programmed. This process is repeated until the entire device is programmed. No special handling must be performed when a panel boundary is crossed. DS30000510F-page 26 No RemainingCmds = RemainingCmds – 1 BaseAddress = BaseAddress + 80h No Are RemainingCmds 0? Yes Finish 4.5.2 Failure Report Error PROGRAMMING VERIFICATION After code memory is programmed, the contents of memory can be verified to ensure that programming was successful. Verification requires code memory to be read back and compared with the copy held in the programmer’s buffer. The READP command can be used to read back all of the programmed code memory. Alternatively, you can have the programmer perform the verification, after the entire device is programmed, using a checksum computation. 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 4.6 Configuration Bits Programming 4.6.1 OVERVIEW The PIC24FJXXXGA2/GB2 devices have Configuration bits stored in the last four locations of implemented program memory (see Table 2-2 for locations). These bits can be set or cleared to select various device configurations. There are two types of Configuration bits: system operation bits and code-protect bits. The system operation bits determine the power-on settings for system-level components, such as the oscillator and Watchdog Timer. The code-protect bits prevent program memory from being read and written. TABLE 4-2: The descriptions for the Configuration bits for the PIC24FJXXXGA2/GB2 device families are shown in Table 4-2. Note: Although not implemented with a specific function, some Configuration bit positions have default states that must always be maintained to ensure device functionality, regardless of the settings of other Configuration bits. Refer to Table 3-7 for a list of these bit positions and their default states. PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS Bit Field Register(1) Description ALTCMPI CW2<12> Alternate Comparator Input bit 1 = C1INC is on RB13, C2INC is on RB9 and C3INC is on RA0 0 = C1INC, C2INC and C3INC are on RB9 ALTRB6(2,3) CW2<11> Alternate RB6 Pin Functions Location Enable bit 1 = Appends the RP6/ASCL1/PMD6 functions of RB6 to RA1 pin functions 0 = Retains the RP6/ASCL1/PMD6 functions to RB6 BOREN CW3<12> Brown-out Reset Enable bit 1 = BOR is enabled in hardware (outside of Deep Sleep) 0 = BOR is disabled DEBUG CW1<11> Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode DSSWEN CW4<8> Deep Sleep Software Control bit 1 = Deep Sleep operation is enabled and controlled by the DSEN bit 0 = Deep Sleep operation is always disabled DSWDTEN CW4<7> Deep Sleep Watchdog Timer (DSWDT) Enable bit 1 = DSWDT is enabled in Deep Sleep 0 = DSWDT is disabled DSBOREN CW4<6> Deep Sleep BOR Enable bit 1 = BOR is enabled in Deep Sleep 0 = BOR is disabled in Deep Sleep (does not affect Sleep mode) DSWDTOSC CW4<5> DSWDT Reference Clock Select bit 1 = DSWDT uses LPRC as the reference clock 0 = DSWDT uses SOSC as the reference clock Note 1: 2: 3: 4: 5: 6: Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode. This bit must be ‘1’ whenever VBUS functionality is used. This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’. The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™). Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the Configuration Words page, the Configuration Words page will be protected. Reserved; do not use for the PIC24FJXXXGA20X family. 2012-2015 Microchip Technology Inc. DS30000510F-page 27 PIC24FJXXXGA2/GB2 FAMILIES TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Bit Field Register(1) DSWDTPS<4:0> CW4<4:0> Deep Sleep Watchdog Timer Postscale Select bits The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms. 11111 = 1:68,719,476736 (25.7 days) 11110 = 1:34,359,738368(12.8 days) 11101 = 1:17,179,869184 (6.4 days) 11100 = 1:8,589,934592 (77.0 hours) 11011 = 1:4,294,967296 (38.5 hours) 11010 = 1:2,147,483648 (19.2 hours) 11001 = 1:1,073,741824 (9.6 hours) 11000 = 1:536,870912 (4.8 hours) 10111 = 1:268,435456 (2.4 hours) 10110 = 1:134,217728 (72.2 minutes) 10101 = 1:67,108864 (36.1 minutes) 10100 = 1:33,554432 (18.0 minutes) 10011 = 1:16,777216 (9.0 minutes) 10010 = 1:8,388608 (4.5 minutes) 10001 = 1:4,194304 (135.3s) 10000 = 1:2,097152 (67.7s) 01111 = 1:1,048576 (33.825s) 01110 = 1:524288 (16.912s) 01101 = 1:262114 (8.456s) 01100 = 1:131072 (4.228s) 01011 = 1:65536 (2.114s) 01010 = 1:32768 (1.057s) 01001 = 1:16384 (528.5 ms) 01000 = 1:8192 (264.3 ms) 00111 = 1:4096 (132.1 ms) 00110 = 1:2048 (66.1 ms) 00101 = 1:1024 (33 ms) 00100 = 1:512 (16.5 ms) 00011 = 1:256 (8.3 ms) 00010 = 1:128 (4.1 ms) 00001 = 1:64 (2.1 ms) 00000 = 1:32 (1 ms) FCKSM<1:0> CW2<7:6> Clock Switching and Fail-Safe Clock Monitor Selection Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled Note 1: 2: 3: 4: 5: 6: Description Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode. This bit must be ‘1’ whenever VBUS functionality is used. This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’. The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™). Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the Configuration Words page, the Configuration Words page will be protected. Reserved; do not use for the PIC24FJXXXGA20X family. DS30000510F-page 28 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Bit Field Register(1) Description FNOSC<2:0> CW2<10:8> Initial Oscillator Source Selection bits 111 = Fast RC Oscillator with Postscaler module (FRCDIV) 110 = Reserved 101 = Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL modules (FRCPLL) 000 = Fast RC (FRC) Oscillator FWDTEN<1:0> CW1<7:6> Watchdog Timer Configuration bits 11 = Watchdog Timer is enabled in hardware 10 = Watchdog Timer is controlled with the SWDTEN bit setting 01 = Watchdog Timer is enabled only while device is active and disabled in Sleep; SWDTEN bit is disabled 00 = Watchdog Timer is disabled in hardware; SWDTEN bit is disabled FWPSA CW1<4> Watchdog Timer Prescaler Ratio Select bit 1 = Watchdog Timer prescaler ratio of 1:128 0 = Watchdog Timer prescaler ratio of 1:32 GCP CW1<13> General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space GWRP CW1<12> General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are disabled I2C1SEL CW4<14> Alternate I2C1 Location Select bit 1 = I2C1 is multiplexed to SDA1 and SCL1 (default) 0 = I2C1 is multiplexed to ASDA1 and ASCL1 ICS<1:0> CW1<9:8> ICD Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use IESO CW2<15> Internal External Switchover bit 1 = Two-Speed Start-up is enabled 0 = Two-Speed Start-up is disabled IOL1WAY CW4<15> IOLOCK Bit One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON<6>) can be set once, provided an unlock sequence has been completed. Once set, the Peripheral Pin Select (PPS) registers cannot be written to a second time. 0 = The IOLOCK is cleared as needed (provided an unlocking sequence is executed) Note 1: 2: 3: 4: 5: 6: Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode. This bit must be ‘1’ whenever VBUS functionality is used. This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’. The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™). Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the Configuration Words page, the Configuration Words page will be protected. Reserved; do not use for the PIC24FJXXXGA20X family. 2012-2015 Microchip Technology Inc. DS30000510F-page 29 PIC24FJXXXGA2/GB2 FAMILIES TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Bit Field Register(1) Description JTAGEN(4) CW1<14> JTAG Enable bit 1 = JTAG port is enabled 0 = JTAG port is disabled LPCFG CW1<10> Low-Power (Low-Voltage) Regulator Control Enable bit 1 = Low-voltage regulator is disabled, regardless of the RETEN bit 0 = Low-voltage regulator feature is available and controlled by the RETEN bit during Sleep OSCIOFCN CW2<5> OSC2 Pin Function bit (except in XT and HS modes) If POSCMD<1:0> = 11 or 00: 1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RA3 functions as port I/O (RA3) If POSCMD<1:0> = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RA3. PLLDIV<3:0> CW4<13:10> PLL Input Prescaler Select bits 1111 = PLL is disabled 1110 = 8 x PLL is selected 1101 = 6 x PLL is selected 1100 = 4 x PLL is selected 1011 = } • } • } Reserved; do not use • } 1001 = } 0111 = Oscillator divided by 12 (48 MHz input)(6) 0110 = Oscillator divided by 8 (32 MHz input)(6) 0101 = Oscillator divided by 6 (24 MHz input)(6) 0100 = Oscillator divided by 5 (20 MHz input)(6) 0011 = Oscillator divided by 4 (16 MHz input)(6) 0010 = Oscillator divided by 3 (12 MHz input)(6) 0001 = Oscillator divided by 2 (8 MHz input)(6) 0000 = Oscillator used directly (4 MHz input)(6) PLLSS CW3<11> PLL Secondary Source Select bit 1 = Primary Oscillator 0 = FRC Oscillator (8 MHz source) POSCMD<1:0> CW2<1:0> Primary Oscillator Mode Select bits 11 = Primary Oscillator mode is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = EC Oscillator mode is selected SOSCSEL Note 1: 2: 3: 4: 5: 6: CW3<8> SOSC Selection Configuration bit 1 = Secondary Crystal Oscillator (SOSC) mode 0 = Digital External Clock (SCLKI) mode Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode. This bit must be ‘1’ whenever VBUS functionality is used. This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’. The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™). Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the Configuration Words page, the Configuration Words page will be protected. Reserved; do not use for the PIC24FJXXXGA20X family. DS30000510F-page 30 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Register(1) Description WDTCLK<1:0> CW2<4:3> WDT Clock Source Select bits When WDTCMX = 1: 11 = WDT uses LPRC 10 = WDT uses 31 kHz source from FRC when active in Windowed WDT mode and when not using LPRC as the system clock; uses LPRC during Sleep mode and for all other settings 01 = WDT uses SOSC input 00 = WDT uses system clock when active, LPRC while in Sleep mode When WDTCMX = 0: WDTCLKx bits are ignored, LPRC is the WDT clock source. WDTCMX CW2<13> Watchdog Timer Clock Multiplex Select bit 1 = WDT clock source is determined by the WDTCLKx Configuration bits 0 = WDT always uses LPRC as its clock source WDTPS<3:0> CW1<3:0> Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 WDTWIN<1:0> CW3<10:9> Watchdog Timer Window Width bits 00 = 75% 01 = 50% 10 = 37.5% 11 = 25% Bit Field WINDIS CW1<5> Windowed WDT bit 1 = Standard Watchdog Timer is enabled 0 = Windowed Watchdog Timer is enabled; FWDTEN<1:0> must not be ‘00’ WPCFG CW3<14> Configuration Word Code Page Write Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected(5) 0 = Last page and Flash Configuration Words are write-protected provided WPDIS = 0 WPDIS CW3<13> Segment Write Protection Disable bit 1 = Segmented code protection is disabled 0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and WPFPx Configuration bits Note 1: 2: 3: 4: 5: 6: Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode. This bit must be ‘1’ whenever VBUS functionality is used. This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’. The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™). Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the Configuration Words page, the Configuration Words page will be protected. Reserved; do not use for the PIC24FJXXXGA20X family. 2012-2015 Microchip Technology Inc. DS30000510F-page 31 PIC24FJXXXGA2/GB2 FAMILIES TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Register(1) Description WPEND CW3<15> Segment Write Protection End Page Select bit 1 = Protected code segment upper boundary is at the last page of program memory; lower boundary is the code page specified by WPFP<6:0>(5) 0 = Protected code segment lower boundary is at the bottom of program memory (000000h); upper boundary is the code page specified by WPFP<6:0> WPFP<6:0> CW3<6:0> Write-Protect Program Flash Pages bits (valid when WPDIS = 0)(5) When WPEND = 0: Erase/write-protect Flash memory pages, starting at Page 0 and ending with Page WPFP<6:0>. When WPEND = 1: Erase/write-protect Flash memory pages, starting at Page WPFP<6:0> and ending with the last page in user Flash memory. Bit Field Note 1: 2: 3: 4: 5: 6: Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode. This bit must be ‘1’ whenever VBUS functionality is used. This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’. The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™). Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the Configuration Words page, the Configuration Words page will be protected. Reserved; do not use for the PIC24FJXXXGA20X family. DS30000510F-page 32 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 4.6.2 PROGRAMMING METHODOLOGY Configuration bits may be programmed, a single word at a time, using the PROGW command. This command specifies the configuration data and Configuration register address. When Configuration bits are programmed, any unimplemented or reserved bits must be programmed with a ‘1’. Four PROGW commands are required to program the Configuration bits. A flowchart for Configuration bit programming is shown in Figure 4-5. Note: 4.6.3 PROGRAMMING VERIFICATION After the Configuration bits are programmed, the contents of memory should be verified to ensure that the programming was successful. Verification requires the Configuration bits to be read back and compared with the copy held in the programmer’s buffer. The READP command reads back the programmed Configuration bits and verifies that the programming was successful. If the General Segment Code-Protect bit (GCP) is programmed to ‘0’, code memory is code-protected and cannot be read. Code memory must be verified before enabling read protection. See Section 4.6.4 “Code-Protect Configuration Bits” for more information about code-protected Configuration bits. FIGURE 4-5: CONFIGURATION BIT PROGRAMMING FLOW Start ConfigAddress = 0XXXF8h(1) Send PROGW Command Is PROGP response PASS? No Yes ConfigAddress = ConfigAddress + 2 No Is ConfigAddress 0XXXFEh?(1) Yes End Note 1: Failure Report Error Refer to Table 2-2 for Flash Configuration Word addresses. 2012-2015 Microchip Technology Inc. DS30000510F-page 33 PIC24FJXXXGA2/GB2 FAMILIES 4.6.4 CODE-PROTECT CONFIGURATION BITS PIC24FJXXXGA2/GB2 devices provide two complimentary methods to protect application code from overwrites and erasures. These methods also help to protect the device from inadvertent configuration changes during run time. Additional information is available in the product data sheet. 4.6.4.1 GENERAL SEGMENT PROTECTION For the PIC24FJXXXGA2/GB2 devices, the on-chip program memory space is treated as a single block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space; it has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to ‘0’, internal write and erase operations to the program memory are blocked. 4.6.4.2 Code segment protection provides an added level of protection to a designated area of program memory by disabling the NVM safety interlock whenever a write or erase address falls within a specified range. It does not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo General Segment protection for the top half. Note: 4.7 Chip Erasing in ICSP mode is the only way to reprogram code-protect bits from an ON state (‘0’) to an OFF state (‘1’). Exiting Enhanced ICSP Mode Exiting Program/Verify mode is done by removing VIH from MCLR, as shown in Figure 4-6. The only requirement for exit is that an interval, P16, should elapse between the last clock, and program signals on PGECx and PGEDx, before removing VIH. FIGURE 4-6: CODE SEGMENT PROTECTION In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes, where a separate block of write and erase-protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in PIC24FJXXXGA2/GB2 devices can be located by the user anywhere in the program space and configured in a wide range of sizes. EXITING ENHANCED ICSP™ MODE P16 P17 VIH MCLR VDD VIH PGEDx PGECx PGEDx = Input DS30000510F-page 34 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 5.0 THE PROGRAMMING EXECUTIVE Note: FIGURE 5-2: The Programming Executive (PE) can be obtained from each device page on the Microchip web site, www.microchip.com. P1 1 5.1 3 4 5 6 11 12 13 14 P1A 15 16 P3 P1B The programmer and Programming Executive have a master-slave relationship, where the programmer is the master programming device and the Programming Executive is the slave. All communication is initiated by the programmer in the form of a command. Only one command at a time can be sent to the Programming Executive. In turn, the Programming Executive only sends one response to the programmer after receiving and processing a command. The Programming Executive command set is described in Section 5.2 “Programming Executive Commands”. The response set is described in Section 5.3 “Programming Executive Responses”. COMMUNICATION INTERFACE AND PROTOCOL The Enhanced ICSP interface is a 2-wire SPI, implemented using the PGECx and PGEDx pins. The PGECx pin is used as a clock input pin and the clock source must be provided by the programmer. The PGEDx pin is used for sending command data to, and receiving response data from, the Programming Executive. Data transmits to the device must change on the rising edge and hold on the falling edge. Data receives from the device must change on the falling edge and hold on the rising edge. All data transmissions are sent, MSb first, using 16-bit mode (see Figure 5-1). FIGURE 5-1: 2 PGECx Programming Executive Communication 5.1.1 PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA RECEIVED FROM DEVICE P2 PGEDx MSb 14 13 12 11 ... 5 4 3 2 1 LSb Since a 2-wire SPI is used, and data transmissions are half-duplex, a simple protocol is used to control the direction of PGEDx. When the programmer completes a command transmission, it releases the PGEDx line and allows the Programming Executive to drive this line high. The Programming Executive keeps the PGEDx line high to indicate that it is processing the command. After the Programming Executive has processed the command, it brings PGEDx low for 15 s to indicate to the programmer that the response is available to be clocked out. The programmer can begin to clock out the response, 23 s after PGEDx is brought low, and it must provide the necessary amount of clock pulses to receive the entire response from the Programming Executive. After the entire response is clocked out, the programmer should terminate the clock on PGECx until it is time to send another command to the Programming Executive. This protocol is shown in Figure 5-3. 5.1.2 SPI RATE In Enhanced ICSP mode, the PIC24FJXXXGA2/GB2 devices operate from the Internal Fast RC Oscillator (FRCDIV), which has a nominal frequency of 8 MHz. This oscillator frequency yields an effective system clock frequency of 4 MHz. To ensure that the programmer does not clock too fast, it is recommended that a 4 MHz clock be provided by the programmer. P1 1 2 3 4 5 6 11 12 13 14 15 16 PGECx P1A P3 P1B P2 PGEDx MSb 14 13 12 11 ... 5 4 2012-2015 Microchip Technology Inc. 3 2 1 LSb DS30000510F-page 35 PIC24FJXXXGA2/GB2 FAMILIES 5.1.3 TIME-OUTS programmer. Since the Programming Executive has no time-out, it is imperative that the programmer correctly follow the described communication protocol. The Programming Executive uses no Watchdog Timer or time-out for transmitting responses to the programmer. If the programmer does not follow the flow control mechanism using PGECx, as described in Section 5.1.1 “Communication Interface and Protocol”, it is possible that the Programming Executive will behave unexpectedly while trying to send a response to the FIGURE 5-3: As a safety measure, the programmer should use the command time-outs identified and provided in Table 5-1. If the command time-out expires, the programmer should reset the Programming Executive and start programming the device again. PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL Host Transmits Last Command Word 1 2 Programming Executive Processes Command Host Clocks Out Response 15 16 1 2 15 16 1 2 15 16 PGECx PGEDx MSB X X X LSB 1 P8 PGECx = Input PGEDx = Input 5.2 Programming Executive Commands COMMAND FORMAT All Programming Executive commands have a general format, consisting of a 16-bit header and any required data for the command (see Figure 5-4). The 16-bit header consists of a 4-bit opcode field, which is used to identify the command, followed by a 12-bit command length field. DS30000510F-page 36 P20 MSB X X X LSB P21 PGECx = Input (Idle) PGEDx = Output The Programming Executive command set is shown in Table 5-1. This table contains the opcode, mnemonic, length, time-out and description for each command. Functional details on each command are provided in Section 5.2.4 “Command Descriptions”. 5.2.1 MSB X X X LSB 0 P9 PGECx = Input PGEDx = Output FIGURE 5-4: 15 12 COMMAND FORMAT 11 0 Opcode Length Command Data First Word (if required) • • Command Data Last Word (if required) The command opcode must match one of those in the command set. Any command that is received, which does not match the list in Table 5-1, will return a “NACK” response (see Section 5.3.1.1 “Opcode Field”). The command length is represented in 16-bit words since the SPI operates in 16-bit mode. The Programming Executive uses the command length field to determine the number of words to read from the SPI port. If the value of this field is incorrect, the command will not be properly received by the Programming Executive. 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 5.2.2 PACKED DATA FORMAT When 24-bit instruction words are transferred across the 16-bit SPI interface, they are packed to conserve space using the format shown in Figure 5-5. This format minimizes traffic over the SPI and provides the Programming Executive with data that is properly aligned for performing Table Write operations. FIGURE 5-5: PACKED INSTRUCTION WORD FORMAT 15 8 7 0 LSW1 MSB2 MSB1 LSW2 LSWx: Least Significant 16 bits of instruction word MSBx: Most Significant Bytes of instruction word TABLE 5-1: Opcode Note: 5.2.3 When the number of instruction words transferred is odd, MSB2 is zero and LSW2 cannot be transmitted. PROGRAMMING EXECUTIVE ERROR HANDLING The Programming Executive will “NACK” all unsupported commands. Additionally, due to the memory constraints of the Programming Executive, no checking is performed on the data contained in the programmer command. It is the responsibility of the programmer to command the Programming Executive with valid command arguments or the programming operation may fail. Additional information on error handling is provided in Section 5.3.1.3 “QE_Code Field”. PROGRAMMING EXECUTIVE COMMAND SET Mnemonic Length (16-bit words) Time-out Description 0h SCHECK 1 1 ms Sanity check. 1h READC 3 1 ms Read an 8-bit word from the specified Device ID register. 2h READP 4 1 ms/row Read N 24-bit instruction words of code memory, starting from the specified address. 3h RESERVED N/A N/A This command is reserved; it will return a NACK. 4h PROGC 4 5 ms Write an 8-bit word to the specified Device ID registers. 5h PROGP 99 5 ms Program one row of code memory at the specified address, then verify.(1) 6h RESERVED 5 5 ms This command is reserved; it will return a NACK. 7h RESERVED N/A N/A This command is reserved; it will return a NACK. 8h RESERVED N/A N/A This command is reserved; it will return a NACK. 9h RESERVED N/A N/A This command is reserved; it will return a NACK. Ah RESERVED N/A N/A This command is reserved. Bh QVER Ch RESERVED Dh Eh Note 1: 1 1 ms Query the Programming Executive software version. N/A N/A This command is reserved; it will return a NACK. PROGW 4 5 ms Program one instruction word of code memory at the specified address and then verify. QBLANK 3 30 ms/Kbyte Query if the code memory is blank. One row of code memory consists of (64) 24-bit words. Refer to Table 2-2 for device-specific information. 2012-2015 Microchip Technology Inc. DS30000510F-page 37 PIC24FJXXXGA2/GB2 FAMILIES 5.2.4 COMMAND DESCRIPTIONS 5.2.6 All commands supported by the Programming Executive are described in Section 5.2.5 “SCHECK Command” through Section 5.2.12 “QVER Command”. 5.2.5 15 READC COMMAND 12 11 Opcode 12 11 N Addr_MSB Addr_LS 0 Opcode Length Field Description Opcode 0h Length 1h The SCHECK command instructs the Programming Executive to do nothing but generate a response. This command is used as a “Sanity Check” to verify that the Programming Executive is operational. Expected Response (2 Words): 1000h 0002h Note: 0 Length SCHECK COMMAND 15 8 7 This instruction is not required for programming; it is provided for development purposes only. Field Description Opcode 1h Length 3h N Number of 8-bit Device ID registers to read (max. of 256) Addr_MSB MSB of 24-bit source address Addr_LS Least Significant 16 bits of 24-bit source address The READC command instructs the Programming Executive to read N or Device ID registers, starting from the 24-bit address specified by Addr_MSB and Addr_LS. This command can only be used to read 8-bit or 16-bit data. When this command is used to read Device ID registers, the upper byte in every data word returned by the Programming Executive is 00h and the lower byte contains the Device ID register value. Expected Response (4 + 3 * (N – 1)/2 Words for N Odd): 1100h 2+N Device ID Register 1 ... Device ID Register N Note: DS30000510F-page 38 Reading unimplemented memory will cause the Programming Executive to reset. Ensure that only memory locations present on a particular device are accessed. 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 5.2.7 READP COMMAND 15 12 11 5.2.8 8 7 Opcode 0 Length PROGC COMMAND 15 12 11 0 Length Reserved N Reserved Description Addr_MSB Addr_LS Addr_MSB Data Addr_LS Field 8 7 Opcode Field Description Opcode 2h Opcode 4h Length 4h Length 4h N Number of 24-bit instructions to read (max. of 32768) Reserved 0h Addr_MSB MSB of the 24-bit destination address Reserved 0h Addr_LS Addr_MSB MSB of 24-bit source address Least Significant 16 bits of the 24-bit destination address Addr_LS Least Significant 16 bits of 24-bit source address Data 8-bit data word The READP command instructs the Programming Executive to read N 24-bit words of code memory, including Configuration Words, starting from the 24-bit address specified by Addr_MSB and Addr_LS. This command can only be used to read 24-bit data. All data returned in response to this command uses the packed data format described in Section 5.2.2 “Packed Data Format”. Expected Response (2 + 3 * N/2 Words for N Even): 1200h 2 + 3 * N/2 Least Significant Program Memory Word 1 ... Least Significant Data Word N The PROGC command instructs the Programming Executive to program a single Device ID register located at the specified memory address. After the specified data word has been programmed to code memory, the Programming Executive verifies the programmed data against the data in the command. Expected Response (2 Words): 1400h 0002h Expected Response (4 + 3 * (N – 1)/2 Words for N Odd): 1200h 4 + 3 * (N – 1)/2 Least Significant Program Memory Word 1 ... MSB of Program Memory Word N (zero-padded) Note: Reading unimplemented memory will cause the Programming Executive to reset. Ensure that only memory locations present on a particular device are accessed. 2012-2015 Microchip Technology Inc. DS30000510F-page 39 PIC24FJXXXGA2/GB2 FAMILIES 5.2.9 PROGP COMMAND 15 12 11 5.2.10 8 7 Opcode 0 Length Reserved PROGW COMMAND 15 12 11 8 7 Opcode 0 Length Data_MSB Addr_MSB Addr_MSB Addr_LS Addr_LS D_1 Data_LS D_2 ... D_96 Field Description Field Opcode Description Dh Length 4h Reserved 0h Opcode 5h Addr_MSB MSB of the 24-bit destination address Length 63h Addr_LS Reserved 0h Least Significant 16 bits of the 24-bit destination address Addr_MSB MSB of the 24-bit destination address Data_MSB MSB of 24-bit data Addr_LS Least Significant 16 bits of the 24-bit destination address Data_LS Least Significant 16 bits of the 24-bit data D_1 16-bit Data Word 1 D_2 16-bit Data Word 2 ... 16-bit Data Word 3 through 95 D_96 16-bit Data Word 96 The PROGP command instructs the Programming Executive to program one row of code memory, including Configuration Words (64 instruction words), to the specified memory address. Programming begins with the row address specified in the command. The destination address should be a multiple of 80h. The PROGW command instructs the Programming Executive to program one word of code memory (3 bytes) to the specific memory address. After the word has been programmed to code memory, the Programming Executive verifies the programmed data against the data in the command. Expected Response (2 Words): 1600h 0002h The data to program to memory, located in command words, D_1 through D_96, must be arranged using the packed instruction word format shown in Figure 5-5. After all data has been programmed to code memory, the Programming Executive verifies the programmed data against the data in the command. Expected Response (2 Words): 1500h 0002h Note: Refer to Table 2-2 for code memory size information. DS30000510F-page 40 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 5.2.11 15 QBLANK COMMAND 12 11 Opcode 5.2.12 0 Length 15 QVER COMMAND 12 11 0 Opcode Length Field Description PSize_MSW PSize_LSW Field Description Opcode Ah Length 3h PSize Length of program memory to check in 24-bit words plus one (max. of 49152) The QBLANK command queries the Programming Executive to determine if the contents of code memory and code-protect Configuration bits (GCP and GWRP) are blank (contain all ‘1’s). The size of code memory to check must be specified in the command. Opcode Bh Length 1h The QVER command queries the version of the Programming Executive software stored in test memory. The “version.revision” information is returned in the response’s QE_Code, using a single byte with the following format: main version in upper nibble and revision in the lower nibble (i.e., 23h means Version 2.3 of Programming Executive software). Expected Response (2 Words): 1BMNh (where “MN” stands for Version M.N) 0002h The Blank Check for code memory begins at 0h and advances toward larger addresses for the specified number of instruction words. QBLANK returns a QE_Code of F0h if the specified code memory and code-protect bits are blank; otherwise, QBLANK returns a QE_Code of 0Fh. Expected Response (2 Words for Blank Device): 1AF0h 0002h Expected Response (2 Words for Non-Blank Device): 1A0Fh 0002h Note: QBLANK does not check the system operation Configuration bits, since these bits are not set to ‘1’ when a Chip Erase is performed. 2012-2015 Microchip Technology Inc. DS30000510F-page 41 PIC24FJXXXGA2/GB2 FAMILIES 5.3 Programming Executive Responses 5.3.1.1 The Programming Executive sends a response to the programmer for each command that it receives. The response indicates if the command was processed correctly. It includes any required response data or error data. The Programming Executive response set is shown in Table 5-2. This table contains the opcode, mnemonic and description for each response. The response format is described in Section 5.3.1 “Response Format”. TABLE 5-2: Opcode PROGRAMMING EXECUTIVE RESPONSE OPCODES Mnemonic Description 1h PASS Command is successfully processed 2h FAIL Command is unsuccessfully processed 3h NACK 5.3.1 Opcode Field The opcode is a 4-bit field in the first word of the response. The opcode indicates how the command was processed (see Table 5-2). If the command was processed successfully, the response opcode is PASS. If there was an error in processing the command, the response opcode is FAIL and the QE_Code indicates the reason for the failure. If the command sent to the Programming Executive is not identified, the Programming Executive returns a NACK response. 5.3.1.2 Last_Cmd Field The Last_Cmd is a 4-bit field in the first word of the response and indicates the command that the Programming Executive processed. Since the Programming Executive can only process one command at a time, this field is technically not required. However, it can be used to verify that the Programming Executive correctly received the command that the programmer transmitted. Command is not known RESPONSE FORMAT All Programming Executive responses have a general format, consisting of a two-word header and any required data for the command. 15 12 11 Opcode 8 7 Last_Cmd 0 QE_Code Length D_1 (if applicable) ... D_N (if applicable) Field Description Opcode Response opcode Last_Cmd Programmer command that generated the response QE_Code Query code or error code Length Response length in 16-bit words (includes 2 header words) D_1 First 16-bit data word (if applicable) D_N Last 16-bit data word (if applicable) DS30000510F-page 42 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 5.3.1.3 QE_Code Field The QE_Code is a byte in the first word of the response. This byte is used to return data for query commands and error codes for all other commands. When the Programming Executive processes one of the two query commands (QBLANK or QVER), the returned opcode is always PASS and the QE_Code holds the query response data. The format of the QE_Code for both queries is provided in Table 5-3. TABLE 5-3: Query QE_Code FOR QUERIES QE_Code QBLANK 0Fh = Code memory is NOT blank F0h = Code memory is blank QVER 0xMN, where Programming Executive Software Version = M.N (i.e., 32h means Software Version 3.2) When the Programming Executive processes any command other than a query, the QE_Code represents an error code. Supported error codes are shown in Table 5-4. If a command is successfully processed, the returned QE_Code is set to 0h, which indicates that there was no error in the command processing. If the verification of the programming for the PROGP or PROGC command fails, the QE_Code is set to 1h. For all other Programming Executive errors, the QE_Code is 2h. 2012-2015 Microchip Technology Inc. TABLE 5-4: QE_Code FOR NON-QUERY COMMANDS QE_Code Description 0h No error 1h Verify failed 2h Other error 5.3.1.4 Response Length The response length indicates the length of the Programming Executive’s response in 16-bit words. This field includes the 2 words of the response header. With the exception of the response for the READP command, the length of each response is only 2 words. The response to the READP command uses the packed instruction word format, described in Section 5.2.2 “Packed Data Format”. When reading an odd number of program memory words (N odd), the response to the READP command is (3 * (N + 1)/2 + 2) words. When reading an even number of program memory words (N even), the response to the READP command is (3 * N/2 + 2) words. DS30000510F-page 43 PIC24FJXXXGA2/GB2 FAMILIES 5.4 Programming the Programming Executive to Memory 5.4.1 OVERVIEW If it is determined that the Programming Executive is not present in executive memory (as described in Section 4.2 “Confirming the Presence of the Programming Executive”), it must be programmed into executive memory using ICSP, as described in Section 3.0 “Device Programming – ICSP”. TABLE 5-5: Storing the Programming Executive to executive memory is similar to normal programming of code memory. Namely, the executive memory must be erased and then the Programming Executive must be programmed, 64 words at a time. Table 5-5 provides this control flow. Note: The Programming Executive must always be erased before it is programmed, as described in Table 5-5. PROGRAMMING THE EXECUTIVE Command (Binary) Data (Hex) Description Step 1: Exit the Reset vector and erase the executive memory. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize the NVMCON register to erase the executive memory. 0000 0000 240420 883B00 MOV MOV #0x4042, W0 W0, NVMCON Step 3: Initialize the Erase Pointers to the first page of the executive and then initiate the erase cycle. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 200800 8802A0 200001 000000 BB0881 000000 000000 A8E761 000000 000000 MOV MOV MOV NOP TBLWTL NOP NOP BSET NOP NOP #0x80, W0 W0, TBLPAG #0x0, W1 W1, [W1] NVMCON, #15 Step 4: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP Step 5: Repeat Steps 3 and 4 to erase the second page of executive memory. The W1 Pointer should be incremented by 400h to point to the second page. Step 6: Initialize the NVMCON register to program 64 instruction words. 0000 0000 240010 883B00 MOV MOV #0x4001, W0 W0, NVMCON Step 7: Initialize the TBLPAG register and the Write Pointer (W7). 0000 0000 0000 0000 200800 8802A0 EB0380 000000 DS30000510F-page 44 MOV MOV CLR NOP #0x80, W0 W0, TBLPAG W7 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES TABLE 5-5: Command (Binary) PROGRAMMING THE EXECUTIVE (CONTINUED) Data (Hex) Description Step 8: Load W0:W5 with the next four words of packed Programming Executive code and initialize W6 for programming. Programming starts from the base of executive memory (800000h) using W6 as a Read Pointer and W7 as a Write Pointer. 0000 0000 0000 0000 0000 0000 2<LSW0>0 2<MSB1:MSB0>1 2<LSW1>2 2<LSW2>3 2<MSB3:MSB2>4 2<LSW3>5 MOV MOV MOV MOV MOV MOV #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3>, W5 Step 9: Set the Read Pointer (W6) and load the (next four write) latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0300 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 CLR W6 NOP TBLWTL [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTL [W6++], NOP NOP TBLWTL [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTL [W6++], NOP NOP [W7] [W7++] [++W7] [W7++] [W7] [W7++] [++W7] [W7++] Step 10: Repeat Steps 8 and 9, 16 times, to load the write latches for the 64 instructions. Step 11: Initiate the programming cycle. 0000 0000 0000 A8E761 000000 000000 BSET NOP NOP NVMCON, #15 Step 12: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP Step 13: Reset the device’s internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 14: Repeat Steps 8 through 13 until all 16 rows of executive memory have been programmed. 2012-2015 Microchip Technology Inc. DS30000510F-page 45 PIC24FJXXXGA2/GB2 FAMILIES 5.4.2 PROGRAMMING VERIFICATION After the Programming Executive has been programmed to executive memory using ICSP, it must be verified. Verification is performed by reading out the contents of executive memory and comparing it with the image of the Programming Executive stored in the programmer. TABLE 5-6: Command (Binary) Reading the contents of executive memory can be performed using the same technique described in Section 3.8 “Reading Code Memory”. A procedure for reading executive memory is provided in Table 5-6. Note that in Step 2, the TBLPAG register is set to 80h, such that executive memory may be read. The last eight words of executive memory should be verified with stored values of the diagnostic and calibration words to ensure accuracy. READING EXECUTIVE MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction. 0000 0000 0000 200800 8802A0 EB0300 MOV MOV CLR #0x80, W0 W0, TBLPAG W6 Step 3: Initialize the Write Pointer (W7) to point to the VISI register. 0000 0000 207847 000000 MOV NOP #VISI, W7 Step 4: Read and clock out the contents of the next two locations of executive memory, through the VISI register, using the REGOUT command. 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0001 0000 BA0B96 000000 000000 <VISI> 000000 BADBB6 000000 000000 BAD3D6 000000 000000 <VISI> 000000 BA0BB6 000000 000000 <VISI> 000000 TBLRDL [W6], [W7] NOP NOP Clock out contents of the VISI register NOP TBLRDH.B [W6++], [W7++] NOP NOP TBLRDH.B [++W6], [W7--] NOP NOP Clock out contents of the VISI register NOP TBLRDL [W6++], [W7] NOP NOP Clock out contents of the VISI register NOP Step 5: Reset the device’s internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 6: Repeat Steps 4 and 5 until all 1024 instruction words of executive memory are read. DS30000510F-page 46 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 6.0 DEVICE DETAILS 6.1 Device ID TABLE 6-1: Device The Device ID region of memory can be used to determine mask, variant and manufacturing information about the chip. The Device ID region is 2 x 16 bits and it can be read using the READC command. This region of memory is read-only and can also be read when code protection is enabled. Table 6-1 shows the Device ID for each device, Table 6-2 shows the Device ID registers and Table 6-3 describes the bit field of each register. TABLE 6-2: Address PIC24FJ128GB204 4C5B PIC24FJ128GB202 4C5A PIC24FJ64GB204 4C59 PIC24FJ64GB202 4C58 PIC24FJ128GA204 4C53 PIC24FJ128GA202 4C52 PIC24FJ64GA204 4C51 PIC24FJ64GA202 4C50 Bit Name DEVID FF0002h DEVREV Bit Field DEVID PIC24FJXXXGA2/GB2 DEVICE ID REGISTERS FF0000h TABLE 6-3: DEVICE IDs 15 14 13 12 11 10 9 8 7 6 5 FAMID<7:0> 4 3 2 1 0 DEV<7:0> — REV<3:0> DEVICE ID BIT DESCRIPTIONS Register Description FAMID<7:0> DEVID Encodes the ID of the device family DEV<7:0> DEVID Encodes the individual ID of the device REV<3:0> DEVREV Encodes the sequential (numerical) revision identifier of the device 2012-2015 Microchip Technology Inc. DS30000510F-page 47 PIC24FJXXXGA2/GB2 FAMILIES 6.2 Checksum Computation Table 6-4 describes how to calculate the checksum for each device. All memory locations are summed, one byte at a time, using only their native data size. More specifically, Configuration registers are summed by adding the lower two bytes of these locations (the upper byte is ignored), while code memory is summed by adding all three bytes of code memory. Checksums for the PIC24FJXXXGA2/GB2 devices are 16 bits in size. The checksum is calculated by summing the following: • Contents of code memory locations • Contents of Configuration registers TABLE 6-4: CHECKSUM COMPUTATION Erased Checksum Value Checksum with 0xAAAAAA at 0x0 and Last Code Address Read Code Protection Checksum Computation Disabled CFGB + SUM(0:157F7) F73C F53E Enabled 0 0000h 0000h Disabled CFGB + SUM(0:157F7) F73C F53E Enabled 0 0000h 0000h PIC24FJ128GB204 Disabled CFGB + SUM(0:157F7) F744h F546h Enabled 0 0000h 0000h PIC24FJ128GB202 Disabled CFGB + SUM(0:157F7) F744h F546h Enabled 0 0000h 0000h PIC24FJ64GA204 Disabled CFGB + SUM(0:0ABF7) F93C F73E Enabled 0 0000h 0000h Disabled CFGB + SUM(0:0ABF7) F93C F73E Enabled 043 0000h 0000h PIC24FJ64GB204 Disabled CFGB + SUM(0:0ABF7) F944h F746h Enabled 0 0000h 0000h PIC24FJ64GB202 Disabled CFGB + SUM(0:0ABF7) F944h F746h Enabled 0 0000h 0000h Device PIC24FJ128GA204 PIC24FJ128GA202 PIC24FJ64GA202 Legend: Note: Item SUM[a:b] CFGB = = Description Byte sum of locations, a to b inclusive (all 3 bytes of code memory) Configuration Block (masked) byte sum of ((CW1 & 0x7FFF) + (CW2 & 0xFFFF) + (CW3 & 0xFFFF) + (CW4 & 0xFFFF)) CW1 address is the last location of implemented program memory; CW2 is (last location – 2); CW3 is (last location – 4); CW4 is (last location – 6). DS30000510F-page 48 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES 7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS Standard Operating Conditions Operating Temperature: 0C to +70C. Programming at +25C is recommended. Param No. Symbol Characteristic D111 VDD Supply Voltage During Programming D112 IPP Programming Current on MCLR Min Max Units 2.20 3.60 V — 5 A Conditions Normal programming(1) D113 IDDP Supply Current During Programming — 16 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.8 VDD VDD V D080 VOL Output Low Voltage — 0.4 V IOL = 8.5 mA @ 3.6V D090 VOH Output High Voltage 3.0 — V IOH = -3.0 mA @ 3.6V D012 CIO Capacitive Loading on I/O Pin (PGEDx) — 50 pF To meet AC specifications D013 CF Filter Capacitor Value on VCAP 4.7 10 F Required for controller core P1 TPGEC Serial Clock (PGECx) Period 100 — ns ICSP™ mode 250 — ns Enhanced ICSP mode P1A TPGECL Serial Clock (PGECx) Low Time 40 — ns ICSP mode 100 — ns Enhanced ICSP mode P1B TPGECH Serial Clock (PGECx) High Time 40 — ns ICSP mode 100 — ns Enhanced ICSP mode ns P2 TSET1 Input Data Setup Time to Serial Clock 15 — P3 THLD1 Input Data Hold Time from PGECx 15 — ns P4 TDLY1 Delay Between 4-Bit Command and Command Operand 40 — ns P4A TDLY1A Delay Between 4-Bit Command Operand and Next 4-Bit Command 40 — ns P5 TDLY2 Delay Between Last PGECx of Command Byte to First PGECx of Read of Data Word 20 — ns P6 TSET2 VDD Setup Time to MCLR 100 — ns P7 THLD2 Input Data Hold Time from MCLR 25 — ms P8 TDLY3 Delay Between Last PGECx of Command Byte to PGEDx by Programming Executive 12 — s P9 TDLY4 Programming Executive Command Processing Time 40 — s P10 TDLY6 PGECx Low Time After Programming 400 — ns P11 TDLY7 Chip Erase Time 20 40 ms P12 TDLY8 Page Erase Time 20 40 ms P13 TDLY9 Row Programming Time 1.5 — ms P14 TR MCLR Rise Time to Enter ICSP mode — 1.0 s P15 TVALID Data Out Valid from PGECx 10 — ns P16 TDLY10 Delay Between Last PGECx and MCLR 0 — s P17 THLD3 MCLR to VDD 100 — ns P18 TKEY1 Delay from First MCLR to First PGECx for Key Sequence on PGEDx 10 — ms Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V of VDD and VSS, respectively. When the internal voltage regulator is enabled (i.e., ENVREG = VDD), the nominal VCAP is 1.8V. 2012-2015 Microchip Technology Inc. DS30000510F-page 49 PIC24FJXXXGA2/GB2 FAMILIES 7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions Operating Temperature: 0C to +70C. Programming at +25C is recommended. Param No. Symbol Characteristic Min Max Units P19 TKEY2 Delay from Last PGECx for Key Sequence on PGEDx to Second MCLR 1 — ms P20 TDLY11 Delay Between PGEDx by Programming Executive to PGEDx Driven by Host 23 — µs P21 TDLY12 Delay Between Programming Executive Command Response Words 8 — ns Note 1: Conditions VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V of VDD and VSS, respectively. When the internal voltage regulator is enabled (i.e., ENVREG = VDD), the nominal VCAP is 1.8V. DS30000510F-page 50 2012-2015 Microchip Technology Inc. PIC24FJXXXGA2/GB2 FAMILIES APPENDIX A: REVISION HISTORY Revision A (March 2012) Initial revision of this document, PIC24FJ128GB204 family devices. released for Revision B (August 2012) Adds the PIC24FJ128GA204 device family to the specification: Changes opcode in Table 3-4, Table 3-5, Table 3-8, Table 5-5 and Section 2.0 “Programming Overview of PIC24FJXXXGA2/GB2 Devices”. Revision C (January 2013) Redistributes pin diagrams for clarity and adds Figure 2-6. Updates Table 2-2 to include new devices. Updates Table 6-1 to update all Device IDs. Corrects notes on specification, P18 (TKEY1), and removes alternate value; key specification value of 10 ms is unchanged. Updates the history description for Revision B (previously did not mention the addition of the PIC24FJ128GA204 device family). Revision D (February 2014) This revision incorporates the following updates: • Figures: - Updated Figure 2-3, Figure 2-4, Figure 2-5, Figure 2-6 • Tables: - Updated Table 3-7, Table 4-2, Table 5-5 Revision E (May 2014) This revision incorporates the following updates: • Tables: - Updates Table 3-6, Table 3-7, Table 4-2, Table 6-4 Revision F (May 2015) This revision incorporates the following updates: • Tables: - Updates Table 3-6, Table 3-7, Table 4-2 and Table 6-4 2012-2015 Microchip Technology Inc. DS30000510F-page 51 PIC24FJXXXGA2/GB2 FAMILIES NOTES: DS30000510F-page 52 2012-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-412-5 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2012-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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