dsPIC33E/PIC24E FRM, Program Memory

dsPIC33E/PIC24E Program Memory
HIGHLIGHTS
This section of the manual contains the following topics:
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
Program Memory Address Map ..................................................................................... 1-2
Control Registers ........................................................................................................... 1-5
Program Counter ........................................................................................................... 1-6
Reading Program Memory Using Table Instructions...................................................... 1-7
Program Space Visibility from Data Space................................................................... 1-11
Program Memory Writes .............................................................................................. 1-15
Error Correcting Code.................................................................................................. 1-15
Program Memory Low-Power Mode ............................................................................ 1-15
Register Map................................................................................................................ 1-16
Related Application Notes............................................................................................ 1-17
Revision History ........................................................................................................... 1-18
 2009-2014 Microchip Technology Inc.
DS70000613D-page 1
dsPIC33/PIC24 Family Reference Manual
Note:
This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33E/PIC24E devices.
Please consult the note at the beginning of the “Memory Organization” and
“Flash Program Memory” chapters in the current device data sheet to check
whether this document supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com.
1.0
PROGRAM MEMORY ADDRESS MAP
dsPIC33E/PIC24E devices have a 4M x 24-bit program memory address space. Figure 1-1
shows a typical program memory map for dsPIC33E/PIC24E family devices. Figure 1-2 provides
an example of the program memory map for devices that also implement auxiliary memory.
The program memory space can be accessed through the following methods:
• 23-bit Program Counter (PC)
• Table Read (TBLRD) instruction
• Program Space Visibility (PSV) mapping any 32-Kbyte segment of program memory into
the data memory address space
The program memory address space in dsPIC33E/PIC24E devices is divided into two equal
halves, referred to as the User Memory Space and the Configuration Memory Space.
The User Memory Space is comprised of the following areas:
• User Program Flash Memory
• Flash Configuration Bytes (if applicable; refer to the “Special Features” chapter of the
specific device data sheet for availability)
• Auxiliary Program Flash Memory (if applicable; refer to the “Memory Organization”
chapter of the specific device data sheet for availability)
For devices that support auxiliary program Flash memory, instructions in the auxiliary program
Flash memory can be executed by the CPU, without stalling it, while the user program memory
is being erased and/or programmed. Similarly, instructions in the user program memory can be
executed by the CPU while the auxiliary program memory is being erased and/or programmed,
without stalls.
The Configuration Memory Space consists of the following areas:
• Device Configuration registers (if applicable; refer to the “Special Features” chapter of the
specific device data sheet for availability)
• Either USERID or One-Time-Programmable (OTP) locations, to store serialization and
other application-specific data (if applicable; refer to the “Special Features” chapter of the
device data sheet for specific implementation details)
• Write latches, which are used for programming user and auxiliary Flash memory (the
number of latches is device-dependent; refer to the “Memory Organization” chapter of
the specific device data sheet for the number of available write latches)
• DEVID locations, which contain the device ID and revision ID. Refer to the “Programming
Specification” for your device, which is available for download from the Microchip Web site
(www.microchip.com) for more information.
DS70000613D-page 2
 2009-2014 Microchip Technology Inc.
dsPIC33E/PIC24E Program Memory
dsPIC33E/PIC24E Program Memory Map for Devices without
Auxiliary Memory
User Memory Space
Figure 1-1:
GOTO Instruction
0x000000
Reset Address
0x000002
0x000004
0x0001FE
0x000200
Interrupt Vector Table
User Program
Flash Memory
Flash Configuration
Bytes
0x0XXXXX
0x0XXXXX
0x0XXXXX
0x0XXXXX
Unimplemented
(Read ‘0’s)
Reserved
Configuration Memory Space
USERID
0x7FFFFE
0x800000
0x800FF6
0x800FF8
0x800FFE
0x801000
Reserved
Write Latches
0xF9FFFE
0xFA0000
0xFA0002
0xFA0004
Reserved
DEVID
0xFEFFFE
0xFF0000
0xFF0002
0xFF0004
Reserved
0xFFFFFE
Note 1:
2:
 2009-2014 Microchip Technology Inc.
Memory areas are not shown to scale.
This memory map is for reference only. Refer to the “Memory Organization” chapter
of the specific device data sheet for exact memory addresses.
DS70000613D-page 3
dsPIC33/PIC24 Family Reference Manual
Figure 1-2:
dsPIC33E/PIC24E Program Memory Map for Devices with
Auxiliary Memory
GOTO Instruction(2)
Reset Address(2)
User Memory Space
Interrupt Vector Table
User Program
Flash Memory
Unimplemented
(Read ‘0’s)
Auxiliary Program
Flash Memory
0x0XXXXX
0x0XXXXX
0x7FBFFE
0x7FC000
0x7FFFF8
Auxiliary Interrupt
Vector
0x7FFFFA
GOTO Instruction(2)
0x7FFFFC
Reset Address(2)
0x7FFFFE
0x800000
Reserved
USERID
Configuration Memory Space
0x000000
0x000002
0x000004
0x0001FE
0x000200
Reserved
Device Configuration
Registers
Reserved
Write Latch
Reserved
DEVID (2 Words)
0x800FF6
0x800FF8
0x800FFE
0x801000
0xF7FFFE
0xF80000
0xF80012
0xF80014
0xF9FFFE
0xFA0000
0xFA00FE
0xFA0100
0xFEFFFE
0xFF0000
0xFF0002
Reserved
0xFFFFFE
Note 1:
DS70000613D-page 4
Memory areas are not shown to scale.
2:
Reset location is controlled by the Reset Target Vector Select bit (RSTPRI). Refer to
the “Special Features” chapter of the specific device data sheet for more information.
3:
This memory map is for reference only. Refer to the “Memory Organization” chapter
in the specific device data sheet for exact memory addresses.
 2009-2014 Microchip Technology Inc.
dsPIC33E/PIC24E Program Memory
2.0
CONTROL REGISTERS
There are two registers that can be used to manage the program Flash:
• TBLPAG: Table Page Register
• DSRPAG: Data Space Read Page Register
Register 2-1:
TBLPAG: Table Page Register
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TBLPAG<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
TBLPAG<7:0>: Table Page Address bits
The 8-bit Table Address Page bits are concatenated with the W register to form a 23-bit effective
program memory address plus a Byte Select bit.
DSRPAG: Data Space Read Page Register(1,2,3)
Register 2-2:
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
DSRPAG<9:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
DSRPAG<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
Unimplemented: Read as ‘0’
bit 9-0
DSRPAG<9:0>: Data Space Read Page Pointer bits
Note 1:
2:
3:
x = Bit is unknown
When DSRPAG = 0x000, attempts to read from the paged Data Space (DS) window will cause an address
error trap.
DSRPAG is reset to 0x001.
The Program Space (PS) can be read using DSRPAG values of 0x200 or greater.
 2009-2014 Microchip Technology Inc.
DS70000613D-page 5
dsPIC33/PIC24 Family Reference Manual
3.0
PROGRAM COUNTER
The PC increments by two with the Least Significant bit (LSb) set to ‘0’ to provide compatibility
with Data Space Addressing. Sequential instruction words are addressed in the 4M program
memory space by PC<22:1>. Each instruction word is 24 bits wide.
The LSb of the program memory address (PC<0>) is reserved as a Byte Select bit for program
memory accesses, from Data Space, that use Program Space Visibility (PSV) or table instructions. For instruction fetches via the PC, the Byte Select bit is not required, so PC<0> is always
set to ‘0’. For more information on the PSV mode of operation, see Section 5.0 “Program Space
Visibility from Data Space”.
Figure 3-1 illustrates an instruction fetch example. Note that incrementing PC<22:1> by one is
equivalent to adding two to PC<22:0>.
Figure 3-1:
Instruction Fetch Example
0x000000
23
User
Space
+1(1)
23
Program Counter
22
24
Instruction
Latch
24 Bits
Instruction
0
0
0x7FFFFE
Note 1:
DS70000613D-page 6
An increment of one to PC<22:1> is equivalent to PC<22:0> + 2.
 2009-2014 Microchip Technology Inc.
dsPIC33E/PIC24E Program Memory
4.0
READING PROGRAM MEMORY USING TABLE INSTRUCTIONS
The Table Read instruction offers a direct method of reading the least significant word (lsw) and
the Most Significant Byte (MSB) of any instruction word, within Program Space, without going
through Data Space, which is preferable for some applications. For information on programming
Flash memory, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Flash Programming”
(DS70609), which is available from the Microchip web site (www.microchip.com).
4.1
Table Instruction Summary
A set of table instructions is provided to move byte-sized or word-sized data between Program
Space and Data Space. The Table Read instructions, in conjunction with the TBLPAG register,
are used to read from the program memory space into data memory space. There are two Table
Read instructions: TBLRDL (Table Read Low) and TBLRDH (Table Read High).
For table instructions, program memory can be regarded as two 16-bit, word-wide address
spaces, residing side by side, each with the same address range (as illustrated in Figure 4-1).
This allows Program Space to be accessed as byte or aligned word-addressable, 16-bit wide,
64-Kbyte pages (i.e., same as Data Space).
The TBLRDL instruction accesses the least significant data word of the program memory and
TBLRDH accesses the upper word. Because program memory is only 24 bits wide, the upper byte
from this latter space does not exist, although it is addressable. It is, therefore, termed the
“phantom” byte.
Figure 4-1:
High and Low Address Regions for Table Operations
MSW
Address
23
0x000001
0x000003
0x000005
0x000007
least significant word
most significant word
16
8
 2009-2014 Microchip Technology Inc.
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
PC Address
(LSW Address)
Instruction Width
DS70000613D-page 7
dsPIC33/PIC24 Family Reference Manual
4.2
Table Address Generation
Figure 4-2 illustrates how for all table instructions, a W register address value is concatenated
with the 8-bit Table Page (TBLPAG) register to form a 24-bit effective Program Space address,
including a Byte Select bit (bit 0). Because there are 16 bits of Program Space address provided
from the W register, the data table page size in program memory is 32K words. Figure 4-3 shows
the organization of the table pages in the Program Space.
Note:
Figure 4-2:
In the event of an overflow or underflow, the Effective Address (EA) will wrap to the
beginning of the current page.
Address Generation for Table Operations
TBLPAG<7> Selects
User or Configuration
Space
EA<0> Selects Byte
7
0 15
0
TBLPAG
EA
8 Bits from TBLPAG
16 Bits from Wn
24-Bit EA
Figure 4-3:
Table Page Memory Map
TBLRDH
MSB
Access
Enabled
TBLRDL
LSW
Access
Enabled
TABLE PAGE
0x00
TABLE PAGE
0x00
24-Bit
Program Space Address
[TBLPAG<7:0>:Wn<15:0>]
0x000000
0x010000
TABLE PAGE
0x01
TABLE PAGE
0x01
0x020000
TABLE PAGE
0x02
TABLE PAGE
0x02
0x030000
0xFD0000
TABLE PAGE
0xFD
TABLE PAGE
0xFD
0xFE0000
TABLE PAGE
0xFE
TABLE PAGE
0xFE
0xFF0000
TABLE PAGE
0xFF
TABLE PAGE
0xFF
0xFFFFFE
DS70000613D-page 8
 2009-2014 Microchip Technology Inc.
dsPIC33E/PIC24E Program Memory
4.3
Program Memory Low Word Access
The TBLRDL instruction is used to access the lower 16 bits of program memory data. The LSb of
the W register, which is used as a pointer, is ignored for word-wide table accesses. For byte-wide
accesses, the LSb of the W register address determines which byte is read. Figure 4-4
demonstrates the program memory data regions accessed by the TBLRDL instruction.
Figure 4-4:
Program Data Table Access (Lower 16 Bits)
PC Address
23
16
8
0
0x000100
00000000
TBLRDL.W
0x000102
0x000104
00000000
00000000
TBLRDL.B (Wn<0> = 1)
0x000106
00000000
TBLRDL.B (Wn<0> = 0)
‘Phantom’ Byte
(Read as ‘0’)
4.4
Program Memory High Word Access
The TBLRDH instruction is used to access the upper 8 bits of the program memory data.
Figure 4-5 illustrates how these instructions also support Word or Byte Access modes for
orthogonality, but the high byte of the program memory data will always return ‘0’.
Figure 4-5:
Program Data Table Access (Upper 8 Bits)
‘Phantom’ Byte
(Read as ‘0’)
TBLRDH.W
TBLRDH.B (Wn<0> = 1)
23
16
8
0 PC Address
00000000
0x000100
00000000
0x000102
00000000
0x000104
00000000
0x000106
TBLRDH.B (Wn<0> = 0)
 2009-2014 Microchip Technology Inc.
DS70000613D-page 9
dsPIC33/PIC24 Family Reference Manual
4.5
Accessing Program Memory Using Table Instructions
In Example 4-1, table instructions are used to access the program memory using an assembly
language subroutine. In Example 4-2, program memory is accessed using the built-in functions,
__builtin_tblpage and __builtin_tbloffset, that are provided by the MPLAB® XC16
C compiler.
Example 4-2 uses the space(prog) attribute to allocate the buffer in program memory. The
MPLAB XC16 Compiler also has built-in functions, such as __builtin_tblpage and
__builtin_tbloffset, that can be used to access the buffer. For more information, refer to the
“MPLAB XC16 C Compiler User’s Guide” (DS50002071).
Example 4-1:
Using Table Instructions to Access Program Memory
extern
long
unsigned long
int
{
MemRead (unsigned int TablePage, unsigned int TableOffset);
Data1, Data2, Data3;
main(void)
/* Read
Data1 =
Data2 =
Data3 =
Configuration Register addresses 0xF80000 and 0xF80002 */
MemRead (0xF8, 0x0006);
MemRead (0xF8, 0x0008);
MemRead (0xF8, 0x000A);
while(1);
}
.section .text
.global _MemRead
;************************
; Function _MemRead:
;
; W0 = TBLPAG value
; W1 = Table Offset
; Return: Data in W1:W0
;************************
_MemRead:
MOV
W0, TBLPAG
NOP
TBLRDL
[W1], W0
TBLRDH
[W1], W1
RETURN
Using MPLAB® XC16 C Compiler to Access Program Memory
Example 4-2:
int prog_data[10] __attribute__((space(prog))) = {0x0000, 0x1111, 0x2222,
0x3333, 0x4444, 0x5555, 0x6666, 0x7777, 0x8888, 0x9999};
unsigned
unsigned
int lowWord[10], highWord[10];
int tableOffset, loopCount;
int main(void)
{
TBLPAG = __builtin_tblpage (prog_data);
tableOffset = __builtin_tbloffset (prog_data);
/* Read all 10 constants into the lowWord and highWord arrays */
for (loopCount = 0; loopCount < 10; loopCount ++)
{
lowWord[loopCount] = __builtin_tblrdl (tableOffset);
highWord[loopCount] = __builtin_tblrdh (tableOffset);
tableOffset +=2;
}
while(1);
}
DS70000613D-page 10
 2009-2014 Microchip Technology Inc.
dsPIC33E/PIC24E Program Memory
5.0
PROGRAM SPACE VISIBILITY FROM DATA SPACE
The upper 32 Kbytes of the dsPIC33E/PIC24E data memory address space can optionally be
mapped into any 16K word Program Space page. The PSV mode of operation provides transparent
access of stored constant data from X Data Space without the need to use special instructions
(i.e., TBLRD, TBLWT instructions).
5.1
PSV Configuration
The dsPIC33E/PIC24E core extends the available Data Space through a paging scheme to make
it appear linear for pre-modified and post-modified Effective Addresses.
The upper half of the base Data Space address (0x8000 to 0xFFFF) is used with the 10-bit Data
Space Read Page (DSRPAG) register to form a PSV address and can address 8 Mbytes of PSV
address space. The paged memory scheme provides access to multiple 32-Kbyte windows in the
PSV memory. The PSV in the paged data memory space is illustrated in Figure 5-1.
Program Space (PS) can be read with a DSRPAG register of 0x200 or greater. Reads from PS
are supported using the DSRPAG register. Writes to PS are not supported; therefore, the Data
Space Write Page (DSWPAG) register is dedicated exclusively to Data Space (DS), including
Extended Data Space (EDS).
For more information on the paged memory scheme, refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Data Memory” (DS70595).
Figure 5-1:
PSV Memory Mapping
16-Bit
Data Space
Address
0x0000
SFR and
Non-Mappable
Data Space
0x8000
Mappable
Data Space
0xFFFF
24-Bit
Program
Space
Address
When DSRPAG<9> = 1:
MSB
Access
LSW
Access
(DSRPAG<8> = 1) (DSRPAG<8> = 0)
0x000000
PSV PAGE
0x300
PSV PAGE
0x200
0x008000
PSV PAGE
0x301
PSV PAGE
0x201
0x010000
PSV PAGE
0x302
PSV PAGE
0x202
0x018000
0x7E8000
PSV PAGE
0x3FD
PSV PAGE
0x2FD
0x7F0000
PSV PAGE
0x3FE
PSV PAGE
0x2FE
PSV PAGE
0x3FF
PSV PAGE
0x2FF
0x7F8000
0x7FFFFE
 2009-2014 Microchip Technology Inc.
DS70000613D-page 11
dsPIC33/PIC24 Family Reference Manual
5.1.1
PSV ADDRESS GENERATION
Allocating different Page registers for read and write access allows the architecture to support
data movement from different PSV pages to EDS pages, by configuring DSRPAG and DSWPAG
to address PSV and EDS space, respectively. The data can be moved from PSV to EDS space
by a single instruction.
Figure 5-2 illustrates the generation of the PSV address. The 15 Least Significant bits (LSbs) of
the PSV address are provided by the W register that contains the Effective Address. The Most
Significant bit (MSb) of the W register is not used to form the address. Instead, the MSb specifies
whether to perform a PSV access from program memory space or a normal access from the data
memory space. If the Effective Address of the W register is 0x8000 or greater, the data access
will occur from program memory space, depending on the page selected by the DSRPAG register. All data access occurs from the data memory when the Effective Address of the W register
is less than 0x8000.
DSRPAG<8>
PSV Address Generation
DSRPAG<9>
Figure 5-2:
1
x
EA<15>
1
0
EA
x
Byte
Select
DSRPAG<7:0>(2)
8 Bits
15 Bits
23-Bit PS Effective Address
User Program Space Read
EA<15>
DSRPAG
Operation and Target
<9>
<8>
1
1
1
PSV, Upper Word (MSB)(1)
1
1
0
PSV, Lower Word (lsw) (byte selected by EA<0>)(1)
1
0
x
EDS Read (uses DSPAG<8:0> for a 24-bit EA)
x
x
Data Memory Space
0
Note 1:
PSV access is only valid for DSPAG<7:0> values for 0x200 to 0x3FF, inclusive.
The remaining address bits are provided by the 8 LSbs of the Data Space Read Page register
(DSRPAG<7:0>). The DSRPAG<7:0> bits are concatenated with the 15 LSbs of the W register
holding the Effective Address, and the MSb is forced to ‘0’, thereby forming a 24-bit program
memory address.
Note:
PSV can only be used to access values in the program memory space. Table
instructions must be used to access values in the user configuration space.
The LSb of the W register value is used as a Byte Select bit, which allows instructions using PSV
to operate in Byte or Word mode.
The PSV address is split into lsw and MSB. When DSRPAG<9:8> = 10, the lsw 16 bits of the
24-bit PS word can be accessed using PSV. When DSRPAG<9:8> = 11, the MSB of the 24-bit
PS word can be accessed using PSV. The range of valid DSRPAG values for a lsw read starts
at DSRPAG = 0x200 and the range of valid DSRPAG values for a MSB read starts at
DSRPAG = 0x300.
DS70000613D-page 12
 2009-2014 Microchip Technology Inc.
dsPIC33E/PIC24E Program Memory
5.2
PSV Timing
All instructions that use PSV require five instruction cycles to complete execution.
5.2.1
USING PSV IN A REPEAT LOOP
Instructions that use PSV with Indirect Addressing mode, using a post-modification offset of +2 or
-2 within a REPEAT loop, eliminate some of the cycle count overhead required for the instruction
access from program memory. These instructions have an effective execution throughput of one
instruction cycle per iteration. However, the following iterations of the REPEAT loop will execute in
five instruction cycles:
• First iteration
• Instruction execution prior to exiting the loop due to an interrupt
• Instruction execution upon re-entering the loop after an interrupt is serviced
The last iteration of the REPEAT loop will execute in six instruction cycles.
If the PSV Addressing mode uses an offset range other than +2 or -2 within a REPEAT loop, five
instruction cycles are needed to execute each iteration of the loop.
Note:
Unlike PSV accesses, a TBLRDL/H instruction requires five instruction cycles for
each iteration.
5.2.2
PSV AND INSTRUCTION STALLS
For more information about instruction stalls using PSV, refer to the appropriate “dsPIC33/PIC24
Family Reference Manual”, “CPU” or “dsPIC33E Enhanced CPU” (DS70359 or DS70005158,
respectively) specified in the device data sheet.
5.3
PSV Code Examples
Example 5-1 illustrates how to create a buffer and access the buffer in the compiler-managed
PSV section. The auto_psv space is the compiler-managed PSV section. Sections greater than
32K are allowed and automatically managed. By default, the compiler places all const qualified
variables into the auto_psv space.
When auto_psv is used, the compiler will save/restore the DSRPAG register dynamically, as
needed. The tool chain will arrange for the DSRPAG to be correctly initialized in the compiler
run-time start-up code.
Example 5-1:
Compiler-Managed PSV Access
const int m[5] __attribute__((space(auto_psv))) = {1, 2, 3, 4, 5};
int x[5] = {10, 20, 30, 40, 50};
int
sum;
int
vectordot (int *, int *);
int
{
main(void)
// Compiler-managed PSV
sum = vectordot ((int *) m, x);
while(1);
}
int
{
}
Note:
vectordot (int *m, int *x)
int i, sum = 0;
for (i = 0; i < 5; i ++)
sum += (*m++) * (*x++);
return (sum);
The auto_psv option must be used if the user application is using both PSV and
EDS accesses on a device with more than 28 Kbytes of RAM.
 2009-2014 Microchip Technology Inc.
DS70000613D-page 13
dsPIC33/PIC24 Family Reference Manual
Example 5-2 illustrates buffer placement and access in the user-managed PSV section. The psv
space is the user-managed PSV section. Example 5-3 illustrates the placement of constant data
in program memory and accesses this data through the PSV data window using an assembly
program.
Example 5-2:
User-Managed PSV Access
const
int m[5] = {1, 2, 3, 4, 5};
const
int m1[5] __attribute__ ((space(psv))) = {2, 4, 6, 8, 10};
const
int m2[5] __attribute__ ((space(psv))) = {3, 6, 9, 12, 15};
int x[5] = {10, 20, 30, 40, 50};
int sum, sum1, sum2;
int vectordot (int *, int *);
int main(void)
{
int temp;
temp = DSRPAG;
// Save original PSV page value
DSRPAG = __builtin_psvpage (m1);
sum1 = vectordot ((int *) m1, x);
DSRPAG = __builtin_psvpage (m2);
sum2 = vectordot ((int *) m2, x);
DSRPAG = temp;
// Restore original PSV page value
sum = vectordot ((int *) m, x);
while(1);
}
int vectordot (int *m, int *x)
{
int i, sum = 0;
for (i = 0; i < 5; i ++)
sum += (*m++) * (*x++);
return (sum);
}
Example 5-3:
PSV Code Example in Assembly
.section .const, psv
fib_data:
.word 0, 1, 2, 3, 5, 8, 13
; Start of code section
.text
.global __main
__main:
; Set DSRPAG to the page that contains the “fib_data” array
MOVPAG #psvpage(fib_data), DSRPAG
; Set up W0 as a pointer to “fib_data” through the PSV data window
MOV #psvoffset(fib_data), W0
; Load the data values into registers W1 - W7
MOV [W0++], W1
MOV [W0++], W2
MOV [W0++], W3
MOV [W0++], W4
MOV [W0++], W5
MOV [W0++], W6
MOV [W0++], W7
done:
BRA done
RETURN
DS70000613D-page 14
 2009-2014 Microchip Technology Inc.
dsPIC33E/PIC24E Program Memory
6.0
PROGRAM MEMORY WRITES
There are two methods by which the user application can program Flash memory:
• Run-Time Self-Programming (RTSP)
• In-Circuit Serial Programming™ (ICSP™)
For more information on RTSP, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Flash
Programming” (DS70609). For more information on ICSP, refer to the specific “Flash Programming Specification” for your device, which can be obtained from the Microchip web site
(www.microchip.com).
7.0
ERROR CORRECTING CODE
In order to improve program memory performance and durability, select dsPIC33E and PIC24E
devices include Error Correcting Code (ECC) functionality as an integral part of the Flash memory controller. ECC can determine the presence of single-bit errors in program data, including
which bit is in error, and correct the data without user intervention. When implemented, ECC is
automatic and cannot be disabled.
When data is written to program memory, ECC generates a 7-bit Hamming code parity value for
every two (24-bit) instruction words. The data is stored in blocks of 48 data bits and 7 parity bits;
parity data is not memory-mapped and is inaccessible. When the data is read back, the ECC calculates parity on it and compares it to the previously stored parity value. If a parity mismatch
occurs, there are two possible outcomes:
• Single-bit errors are automatically identified and corrected on read back. An optional
device-level interrupt (ECCSBEIF) is also generated.
• Double-bit errors will generate a generic hard trap. If special exception handling for the trap
is not implemented, a device Reset will also occur.
To use the single-bit error interrupt, set the ECC Single-Bit Error Interrupt Enable (ECCSBEIE)
bit and configure the ECCSBEIP bits to set the appropriate interrupt priority.
Aside from the single-bit error interrupt, error events are not captured or counted by hardware.
This functionality can be implemented in the software application, but it is the user’s responsibility
to do so.
8.0
PROGRAM MEMORY LOW-POWER MODE
The voltage regulator for the program Flash memory can be placed in Standby mode when the
device is in Sleep mode, resulting in a reduction in device Power-Down Current (IPD).
When the VREGSF bit (RCON<11>) is equal to ‘0’, the Flash memory voltage regulator goes into
Standby mode during Sleep. When the VREGSF bit is equal to ‘1’, the Flash memory voltage
regulator is active during Sleep mode; however, this mode increases the device wake-up delay.
 2009-2014 Microchip Technology Inc.
DS70000613D-page 15
REGISTER MAP
A summary of the registers associated with the dsPIC33E/PIC24E Program Memory is provided in Table 9-1.
Table 9-1:
File
Name
CPU Core Register Map
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
PCH
—
—
—
—
—
—
DSRPAG
—
—
—
—
—
—
DSWPAG
—
—
—
—
—
—
—
TBLPAG
—
—
—
—
—
—
—
PCL
Legend:
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Program Counter Low Register
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
Program Counter High Register
DSRPAG<9:0>
DSWPAG<8:0>
—
TBLPAG<7:0>
Bit 1
Bit 0
All
Resets
—
0000
0000
0001
0001
0000
 2009-2014 Microchip Technology Inc.
dsPIC33/PIC24 Family Reference Manual
DS70000613D-page 16
9.0
dsPIC33E/PIC24E Program Memory
10.0
RELATED APPLICATION NOTES
This section lists application notes that are related to this section of the manual. These
application notes may not be written specifically for the dsPIC33/PIC24 Product Families, but the
concepts are pertinent and could be used with modification and possible limitations. The current
application notes related to the dsPIC33E/PIC24E Program Memory module are:
Title
Application Note #
No related application notes at this time.
Note:
N/A
For additional Application Notes and code examples for the dsPIC33/PIC24 families
of devices, visit the Microchip web site (www.microchip.com).
 2009-2014 Microchip Technology Inc.
DS70000613D-page 17
dsPIC33/PIC24 Family Reference Manual
11.0
REVISION HISTORY
Revision A (September 2009)
This is the initial released version of this document.
Revision B (July 2010)
This revision includes the following updates:
• All code examples have been updated (see Example 4-1 through Example 5-3)
• Updated the Program Memory Map (see Figure 1-2)
• Updated the first paragraph and the shaded note in Section 4.1 “Table Instruction Summary”
• Added a shaded note after Figure 4-1 with information on writing to the TBLPAG register
• Updated Section 4.2 “Table Address Generation”
• Updated the second sentence in Section 4.3 “Program Memory Low Word Access”
• Added the new figure Table Page Memory Map (see Figure 4-3) in Section 4.4 “Program
Memory High Word Access”
• Added a shaded note and updated the last paragraph in Section 5.1 “PSV Configuration”
• Updated the Paged Data Memory Space (see Figure 5-1)
• Updated the PSV Address Generation (see Figure 5-2)
• Changed the number of required instruction cycles from two to five throughout Section 5.2
“PSV Timing”
• Added a shaded note after Example 5-1 with information on using the auto_psv option
• Added a reference to the “dsPIC33E/PIC24E Flash Programming Specification” (DS70619)
to Section 6.0 “Program Memory Writes”
Revision C (December 2011)
This revision includes the following updates:
• Updated Section 1.0 “Program Memory Address Map”
• Updated the existing Program Memory Map for devices with auxiliary memory (see
Figure 1-2)
• Added a new Program Memory Map for devices without auxiliary memory (see Figure 1-1)
• Updated Using Table Instructions to Access Program Memory (see Example 4-1)
• Updated Using MPLAB® C Compiler to Access Program Memory (see Example 4-2)
• Removed 4.4.5 “Data Storage in Program Memory”
• Removed 4.5.2 “PSV Mapping with X and Y Data Space”
• Updated Compiler-Managed PSV Access (see Example 5-1)
• Updated User-Managed PSV Access (see Example 5-2)
• Updated Section 6.0 “Program Memory Writes”
• Updated Section 8.0 “Program Memory Low-Power Mode”
• Updated the Register Map table (see Table 9-1)
• Minor updates to text and formatting were incorporated throughout the document
DS70000613D-page 18
 2009-2014 Microchip Technology Inc.
dsPIC33E/PIC24E Program Memory
Revision D (November 2014)
Updates the document format and removes the previously assigned master section number as
part of the realignment of dsPIC33E technical documentation. The document reference number
format is also updated.
Updates the document title to “dsPIC33E/PIC24E Program Memory” for clarity.
Adds Section 7.0 “Error Correcting Code”. Subsequent sections are renumbered accordingly.
Updates Section 1.0 “Program Memory Address Map” to mention OTP locations, in addition
to USERID locations
Reorganizes Section 4.0 “Reading Program Memory Using Table Instructions” to include
the “Table Memory Map” (formerly Figure 4-5) with the text of Section 4.2 “Table Address
Generation”, as Figure 4-3.
Updates Section 5.0 “Program Space Visibility from Data Space” by revising Figures 5-1 and
5-2 for clarity, and removing Figures 5-3 and 5-4 as redundant. Adds the subhead,
Section 5.1.1 “PSV Address Generation” to delineate topics without changing the previously
existing text.
Other minor changes to text and typographic changes throughout the document.
 2009-2014 Microchip Technology Inc.
DS70000613D-page 19
dsPIC33/PIC24 Family Reference Manual
NOTES:
DS70000613D-page 20
 2009-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-814-8
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2009-2014 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70000613D-page 21
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