dsPIC33E/PIC24E FRM, Reset

Section 8. Reset
HIGHLIGHTS
This section of the manual contains the following major topics:
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Introduction .................................................................................................................... 8-2
System Reset................................................................................................................. 8-6
Using the RCON Status Bits ........................................................................................ 8-10
Special Function Register Reset States....................................................................... 8-10
Register Map................................................................................................................ 8-11
Design Tips .................................................................................................................. 8-12
Related Application Notes............................................................................................ 8-13
Revision History ........................................................................................................... 8-14
8
Reset
© 2010 Microchip Technology Inc.
DS70602B-page 8-1
dsPIC33E/PIC24E Family Reference Manual
Note:
This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33E/PIC24E devices.
Please consult the note at the beginning of the “Reset” chapter in the current
device data sheet to check whether this document supports the device you are
using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
8.1
INTRODUCTION
The Reset module combines all the reset sources, and controls the device Master Reset Signal,
SYSRST. The following is a list of device Reset sources:
•
•
•
•
•
•
POR: Power-on Reset
BOR: Brown-out Reset
MCLR: Master Clear Pin Reset
SWR: RESET Instruction
WDTO: Watchdog Time-out Reset
CM: Configuration Mismatch Reset
(This source is not available on all devices. Refer to the specific device data sheet for
details.)
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
A simplified block diagram of the Reset module is shown in Figure 8-1. Any active source of reset
will make the SYSRST signal active. On system Reset, some of the registers associated with the
CPU and peripherals are forced to a known Reset state, while some are unaffected.
Note:
Refer to the specific peripheral section or Section 2. “CPU” (DS70359) in the
“dsPIC33E/PIC24E Family Reference Manual” for register Reset states.
All types of device Reset set a corresponding status bit in the RCON register to indicate the type
of reset (see Register 8-1). A POR clears all bits except for the POR and BOR bits (RCON<1:0>),
which are set. The user application can set or clear any bit at any time during code execution.
The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not
cause a device Reset.
The RCON register also contains bits associated with the Watchdog Timer and device power- saving
states. For more information, refer to Section 9. “Watchdog Timer and Power-Saving Modes”
(DS70615).
DS70602B-page 8-2
© 2010 Microchip Technology Inc.
Section 8. Reset
Figure 8-1:
Reset System Block Diagram
RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator
SYSRST
VDD
VDD Rise
Detect
POR
Trap Conflict
Illegal Opcode
Uninitialized W Register
Security Reset
8
Configuration Mismatch(1)
Note 1: The configuration mismatch is not available on all devices. Refer to the specific device
data sheet for details.
Reset
© 2010 Microchip Technology Inc.
DS70602B-page 8-3
dsPIC33E/PIC24E Family Reference Manual
RCON: Reset Control Register(1)
Register 8-1:
R/W-0
R/W-0
TRAPR
IOPUWR
R/W-1
U-0
(4)
SBOREN
—
R/W-0
VREGSF
U-0
—
R/W-0
CM
(2)
R/W-0
VREGS
bit 15
bit 8
R/W-0
R/W-0
EXTR
SWR
R/W-0
(3)
SWDTEN
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
WDTO
SLEEP
IDLE
BOR
POR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or an uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or uninitialized W register Reset has not occurred
bit 13
SBOREN: Software BOR Enable/Disable bit(4)
1 = BOR is turned on in software
0 = BOR is turned off in software
bit 12
Unimplemented: Read as ‘0’
bit 11
VREGSF: Flash Voltage Regulator Stand-by During Sleep bit
1 = Flash voltage regulator is active during Sleep
0 = Flash voltage regulator goes into Stand-by mode during Sleep
bit 10
Unimplemented: Read as ‘0’
bit 9
CM: Configuration Mismatch Flag bit(2)
1 = A configuration mismatch Reset has occurred
0 = A configuration mismatch Reset has not occurred
bit 8
VREGS: Voltage Regulator Stand-by During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Stand-by mode during Sleep
bit 7
EXTR: External Reset Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5
SWDTEN: Software Enable/Disable of WDT bit(3)
1 = WDT is enabled
0 = WDT is disabled
Note 1:
2:
3:
4:
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
The configuration mismatch Reset flag is not available on all devices. (Refer to the specific device data
sheet.)
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
The SBOREN bit is ignored if the BOREN Configuration bit = 0 (FPOR<3>).
DS70602B-page 8-4
© 2010 Microchip Technology Inc.
Section 8. Reset
Register 8-1:
RCON: Reset Control Register(1) (Continued)
bit 4
WDTO: Watchdog Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2
IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset or Power-on Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1:
2:
3:
4:
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
The configuration mismatch Reset flag is not available on all devices. (Refer to the specific device data
sheet.)
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
The SBOREN bit is ignored if the BOREN Configuration bit = 0 (FPOR<3>).
8
Reset
© 2010 Microchip Technology Inc.
DS70602B-page 8-5
dsPIC33E/PIC24E Family Reference Manual
8.2
SYSTEM RESET
The dsPIC33E/PIC24E family of devices have two types of Reset: cold Reset and warm Reset.
A cold Reset is the result of a Power-on Reset (POR) or Brown-out Reset (BOR). On a cold
Reset, the FNOSC configuration bits in the FOSC device configuration register select the device
clock source.
A warm Reset is the result of all other Reset sources, including the RESET instruction. On a warm
Reset, the device will continue to operate from the current clock source as indicated by the
Current Oscillator Selection bits (COSC<2:0>) in the Oscillator Control register
(OSCCON<14:12>).
The device is kept in a Reset state until the system power supplies have stabilized at appropriate
levels and the oscillator clock is ready. Refer to Section 7. “Oscillator” (DS70580) for more
information.
When the oscillator clock is ready, the processor begins execution from location 0x000000. The
user application programs a GOTO instruction at the Reset address, which redirects program
execution to the appropriate start-up routine.
The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the
system clock is ready and the delay TFSCM has elapsed.
Oscillator Delay(1,2,3)
Table 8-1:
Oscillator
Mode
Oscillator
Startup Delay
Oscillator
Startup Timer
FRC
TOSCD
—
—
TOSCD
FRCDIV16
TOSCD
—
—
TOSCD
FRCDIVN
TOSCD
—
—
TOSCD
FRCPLL
TOSCD
—
TLOCK
TOSCD + TLOCK
XT
TOSCD
TOST
—
TOSCD + TOST
HS
TOSCD
TOST
—
TOSCD + TOST
EC
—
—
—
—
XTPLL
TOSCD
TOST
TLOCK
TOSCD + TOST + TLOCK
HSPLL
TOSCD
TOST
TLOCK
TOSCD + TOST + TLOCK
ECPLL
—
—
TLOCK
TLOCK
SOSC
TOSCD
TOST
—
TOSCD + TOST
LPRC
TOSCD
—
—
TOSCD
Note 1:
2:
3:
Note:
DS70602B-page 8-6
PLL Lock Time Total Oscillator Delay
TOSCD = Oscillator Start-up Delay. Crystal Oscillator start-up times vary with crystal
characteristics, load capacitance, and so on. Refer to the ‘’Electrical
Characterisitic’’ chapter of the specific device data sheet for TOSCD specifications
when using the internal FRC or internal LPRC oscillator.
TOST = Oscillator Start-up Timer Delay (1024 oscillator clock periods). For example,
TOST = 102.4 μs for a 10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
TLOCK = PLL lock time, if the PLL is enabled. Refer to the ‘’Electrical
Characterisitic’’ chapter of the specific device data sheet for TLOCK specifications.
When the device exits the Reset condition (begins normal operation), the device
operating parameters (voltage, frequency, temperature, etc.) must be within their
operating ranges, otherwise the device may not function correctly. The user application must ensure that the delay between the time at which the power is first
applied and the time when the device comes out of Reset is long enough to get all
operating parameters within specification.
© 2010 Microchip Technology Inc.
Section 8. Reset
8.2.1
Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is Reset from power-on. The POR circuit is
active until VDD crosses the VPOR threshold and the power-up delay, TPU, has elapsed. The delay
TPU ensures the internal device bias circuits become stable.
The device supply voltage characteristics must meet the specified starting voltage and rise rate
requirements to generate the POR. Refer to the “Electrical Characteristics” chapter of the
specific device data sheet for details.
In addition to TPU and TOST/TPWRT (if applicable), a NVM power-up delay, TNPD, is incurred
before code execution begins.
The Power-on Reset status bit (POR) in the Reset Control (RCON<0>) register is set to indicate
the Power-on Reset.
The device start-up time line and POR timing characteristics are described in the “Electrical
Characteristics” chapter of the specific device data sheet.
8.2.2
Brown-out Reset (BOR) and Power-up Timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR) circuit that resets the device when the VDD
is too low (VDD < VBOR) for proper device operation. The BOR circuit keeps the device in Reset
until VDD crosses the VBOR threshold. Refer to the “Electrical Characteristics” chapter of the
specific device data sheet for the minimum BOR pulse width (TBOR) specifications.
The Brown-out Reset status bit (BOR) in the Reset Control register (RCON<1>) is set to indicate
the Brown-out Reset. Set the Software BOR Enable/Disable bit (SBOREN) in the Reset Control
register (RCON<13>) to enable BOR in software, or clear this bit to disable BOR in software.
Alternately, BOR can be disabled in hardware by programming the BOREN Configuration bit
(FPOR<3>) to ‘0’.
The power-up timer delay (TPWRT) is programmed by the Power-on Reset Timer Value Select
bits (FPWRT<2:0>) in the POR Configuration register (FPOR<2:0>), which provide eight settings
(from 0 ms to 128 ms). Refer to Section 30. “Device Configuration” (DS70618) for further
details.
8.2.3
External Reset (EXTR)
The External Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger
input with an additional glitch filter. Reset pulses that are longer than the minimum pulse-width
will generate a Reset. Refer to the “Electrical Characteristics” chapter of the specific device
data sheet for minimum MCLR pulse width specifications (TMCLR). The External Reset Pin bit
(EXTR) in the Reset Control register (RCON<7>) is set to indicate the MCLR Reset.
Many systems have external supervisory circuits that generate Reset signals to Reset multiple
devices in the system. This external Reset signal can be directly connected to the MCLR pin to
Reset the device when the rest of the system is Reset.
When using other sources to Reset the device, the external reset pin (MCLR) should be tied
directly or resistively to VDD. In this case, the MCLR pin will not be used to generate a Reset. The
external reset pin (MCLR) does not have an internal pull-up and must not be left unconnected.
8.2.4
Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the device will enter a warm Reset state. This
Reset state will not reinitialize the clock. The clock source in effect prior to the RESET instruction
will remain in effect. The device will be released from a Reset state at the next instruction cycle,
and the Reset vector fetch will commence.
The Software Reset (Instruction) Flag bit (SWR) in the Reset Control register (RCON<6>) is set
to indicate the software Reset.
© 2010 Microchip Technology Inc.
DS70602B-page 8-7
Reset
The device will not run at full speed after a BOR as the VDD must rise to acceptable levels for
full-speed operation. The PWRT provides a power-up timer delay (TPWRT) to ensure that the
system power supplies have stabilized at the appropriate levels for full-speed operation before
the device comes out of Reset.
8
dsPIC33E/PIC24E Family Reference Manual
8.2.5
Watchdog Time-out Reset (WDTO)
Whenever a Watchdog time-out occurs, the device will asynchronously assert SYSRST. The
clock source will remain unchanged. A WDT time-out during Sleep or Idle mode will wake-up
the processor, but will not reset the processor.
The Watchdog Time-out Flag bit (WDTO) in the Reset Control register (RCON<4>) is set to
indicate the Watchdog Reset. Refer to Section 9. “Watchdog Timer and Power-Saving
Modes” (DS70615) for more information on Watchdog Time-out Reset.
8.2.6
Trap Conflict Reset
If a lower-priority hard trap occurs while a higher-priority trap is being processed, a hard trap
conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15,
inclusive. The address error (level 13) and oscillator error (level 14) traps fall into this category.
The Trap Reset Flag bit (TRAPR) in the Reset Control register (RCON<15>) is set to indicate the
Trap Conflict Reset. Refer to Section 6. “Interrupts” (DS70600) for more information on Trap
Conflict Reset.
8.2.7
Configuration Mismatch Reset
To maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware. If an unexpected change occurs in any of the registers
(such as cell disturbances caused by ESD or other external events), a configuration mismatch
Reset occurs.
The Configuration Mismatch Flag bit (CM) in the Reset Control register (RCON<9>) is set to
indicate the configuration mismatch Reset. Refer to Section 10. “I/O Ports” (DS70598) for
more information on the Configuration Mismatch Reset.
Note:
8.2.8
The configuration mismatch feature and associated Reset flag are not available on
all devices. (Refer to the specific device data sheet.)
Illegal Condition Device Reset
An illegal condition device Reset occurs due to the following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset Flag bit (IOPUWR) in the Reset Control
register (RCON<14>) is set to indicate the illegal condition device Reset.
8.2.8.1
ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to execute an illegal opcode value that is
fetched from the program memory.
The illegal opcode Reset function can prevent the device from executing program memory
sections that are used to store constant data. To take advantage of the illegal opcode Reset, use
only the lower 16 bits of each program memory section to store the data values. The upper 8 bits
should be programmed with 0x3F, which is an illegal opcode value.
8.2.8.2
UNINITIALIZED W REGISTER RESET
Any attempts to use the uninitialized W register as an address pointer will Reset the device. The
W register array (with the exception of W15) is cleared during all resets and is considered
uninitialized until written to.
DS70602B-page 8-8
© 2010 Microchip Technology Inc.
Section 8. Reset
8.2.8.3
SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that operation will cause a security Reset.
The PFC occurs when the Program Counter is reloaded as a result of a Call, Jump, Computed
Jump, Return, Return from Subroutine, or other form of branch instruction.
The VFC occurs when the Program Counter is reloaded with an Interrupt or Trap vector.
Refer to Section 23. “CodeGuard™ Security” (DS70634) for more information on Security
Reset.
Note 1: If a POR or BOR event occurs while a Run-Time Self-Programming (RTSP) erase
or programming operation is in progress, the RTSP operation is aborted
immediately. The user should execute the RTSP operation again after the device
comes out of Reset.
2: If an EXTR, SWR, WDTO, TRAPR, CM, or IOPUWR reset event occurs while an
RTSP erase or programming operation is in progress, the device will be Reset only
after the RTSP operation is complete.
8
Reset
© 2010 Microchip Technology Inc.
DS70602B-page 8-9
dsPIC33E/PIC24E Family Reference Manual
8.3
USING THE RCON STATUS BITS
The user application can read the Reset Control register (RCON) after any device Reset to
determine the cause of the reset.
Note:
The status bits in the RCON register should be cleared after they are read so that
the next RCON register value after a device Reset will be meaningful.
Table 8-2 provides a summary of the Reset flag bit operation.
Table 8-2:
Reset Flag Bit Operation
Flag Bit
Cleared by:
TRAPR (RCON<15>)
Trap conflict event
POR, BOR
IOPWR (RCON<14>)
Illegal opcode or uninitialized
W register access or Security
Reset
POR, BOR
CM (RCON<9>)
Configuration Mismatch
POR, BOR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET instruction
POR, BOR
WDTO (RCON<4>)
WDT time-out
PWRSAV instruction,
CLRWDT instruction, POR, BOR
SLEEP (RCON<3>)
PWRSAV #SLEEP instruction
POR, BOR
IDLE (RCON<2>)
PWRSAV #IDLE instruction
POR, BOR
BOR (RCON<1>)
POR, BOR
—
POR (RCON<0>)
POR
—
Note:
8.4
Set by:
All Reset flag bits can be set or cleared by the user software.
SPECIAL FUNCTION REGISTER RESET STATES
Most of the Special Function Registers (SFRs) associated with the dsPIC33E/PIC24E CPU and
peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their
peripheral or CPU function and their Reset values are specified in the appropriate sections of this
manual.
The Reset value for each SFR does not depend on the type of Reset, with the exception of seven
registers. The Reset value for the Reset Control register, RCON, will depend on the type of
device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the
type of Reset and the programmed values of the oscillator configuration bits in the FOSC Device
Configuration register. In addition, the oscillator SFRs (OSCCON, CLKDIV, PLLFBD, OSCTUN,
ACLKCONx and ACLKDIVx) and Real-Time Clock and Calendar (RTCC) registers are reset only
at POR.
DS70602B-page 8-10
© 2010 Microchip Technology Inc.
© 2010 Microchip Technology Inc.
8.5
REGISTER MAP
Table 8-3 maps the bit functions for the RCON register.
Table 8-3:
Reset Control Register Map
SFR
Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RCON
TRAPR
IOPUWR
SBOREN
—
VREGSF
—
CM
VREGS
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
POR
0003
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Section 8. Reset
DS70602B-page 8-11
8
Reset
dsPIC33E/PIC24E Family Reference Manual
8.6
DESIGN TIPS
DS70602B-page 8-12
Question 1:
How do I use the RCON register?
Answer:
The initialization code after a device Reset should examine the RCON register
and confirm the source of the Reset. In certain applications, this information can
be used to take appropriate action to correct the problem that caused the Reset
to occur. All Reset status bits in the RCON register should be cleared after
reading them to ensure the RCON value will provide meaningful results after the
next device Reset.
Question 2:
The BOR module does not have the programmable trip points that my
application needs. How can I work around this?
Answer:
The BOR circuitry is used to avoid violation of the V/F specification of the device.
In many devices, the minimum voltage for full-speed operation is much higher
than in dsPIC33E/PIC24E devices. Therefore, in such devices, a programmable
BOR circuit is needed to provide the multiple speed option. However, the
dsPIC33E/PIC24E devices, support full-speed operation at a much lower
voltage, so the simple BOR module is enough. If the device operating voltage
drops to a value where full-speed operation is not possible, then BOR is asserted.
If the device is in a non-BOR state, then full-speed operation is valid.
Question 3:
I initialized a W register with a 16-bit address, but the device appears to
reset when I attempt to use the register as an address.
Answer:
Because all data addresses are 16-bit values, the uninitialized W register logic
only recognizes that a register has been initialized correctly if it was subjected to
a word load. Two-byte moves to a W register, even if successive, will not work,
resulting in a device Reset if the W register is used as an address pointer in an
operation.
© 2010 Microchip Technology Inc.
Section 8. Reset
8.7
RELATED APPLICATION NOTES
This section lists application notes that are related to this section of the manual. These
application notes may not be written specifically for the dsPIC33E/PIC24E product family, but the
concepts are pertinent and could be used with modification and possible limitations. The current
application notes related to the Reset module include the following:
Title
Application Note #
Power-up Trouble Shooting
AN607
Power-up Considerations
AN522
Note:
Please visit the Microchip web site (www.microchip.com) for additional Application
Notes and code examples for the dsPIC33E/PIC24E family of devices.
8
Reset
© 2010 Microchip Technology Inc.
DS70602B-page 8-13
dsPIC33E/PIC24E Family Reference Manual
8.8
REVISION HISTORY
Revision A (July 2009)
This is the initial released version of this document.
Revision B (December 2010)
This revision includes the following updates:
• Added a note at the beginning of the section, which provides information on
complementary documentation
• Updated the dsPIC33E references in the entire document as dsPIC33E/PIC24E
• Added Security Reset to the Reset System Block Diagram (see Figure 8-1)
• Added Note 4 and the VREGSF bit to the Reset Control Register (see Register 8-1)
• Updated the third paragraph (removed numbered references) in 8.2 “System Reset”
• Updated Note1 and Note 3 in Oscillator Delay (see Table 8-1)
• Removed the System Reset Timing diagram
• Updated all paragraphs of 8.2.1 “Power-on Reset (POR)”
• Updated the first and second paragraphs, removed the last paragraph, and removed the
Brown-out Scenarios diagram in 8.2.2 “Brown-out Reset (BOR) and Power-up Timer
(PWRT)”
• Added Note 1 and Note 2 to 8.2.8.3 “Security Reset”
• Removed 8.4 “Device Start-up Time Lines”
• Updated the last paragraph of 8.4 “Special Function Register Reset States”
• Added the VREGSF bit to the Reset Control Register Map (see Table 8-3)
• Updates to formatting and minor text changes have been incorporated throughout the
document
DS70602B-page 8-14
© 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-750-7
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2010 Microchip Technology Inc.
DS70602B-page 8-15
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
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Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
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Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
08/04/10
DS70602B-page 8-16
© 2010 Microchip Technology Inc.
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