CDP1881C, CDP1882, CDP1882C CMOS 6-Bit Latch and Decoder Memory Interfaces March 1997 Features Description • Performs Memory Address Latch and Decoder Functions Multiplexed or Non-Multiplexed The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit memory latch and decoder circuits intended for use in CDP1800 series microprocessor systems. They can interface directly with the multiplexed address bus of this system at maximum clock frequency, and up to four 4K x 8-bit memories to provide a 16K byte memory system. With four 2K x 8-bit memories an 8K byte system can be decoded. • Decodes Up to 16K Bytes of Memory • Interfaces Directly with CDP1800-Series Microprocessors at Maximum Clock Frequency • Can Replace CDP1866 and CDP1867 (Upward Speed and Function Capability) Ordering Information PACKAGE 5V 10V TEMP. RANGE (oC) PKG. NO. PDIP CDP1881CE - -40 to +85 E20.3 PDIP CDP1882CE - -40 to +85 E18.3 PDIP Burn-In CDP1882CEX - -40 to +85 E18.3 - CDP1882D -40 to +85 D18.3 SBDIP The devices are also compatible with non-multiplexed address bus microprocessors. By connecting the clock input to VDD, the latches are in the data-following mode and the decoded outputs can be used in general purpose memorysystem applications. The CDP1881C, CDP1882 and CDP1882C are intended for use with 2K or 4K byte RAMs and are identical except that in the CDP1882 MWR and MRD are excluded. The CDP1882 is functionally identical to the CDP1882C. It differs in that the CDP1882 has recommended operating voltage range of 4V to 10.5V and the C version has a recommended operating voltage range of 4V to 6.5V. The CDP1881C, CDP1882 and CDP1882C are supplied in 20 lead and 18 lead packages, respectively. The CDP1881C is supplied only in a dual-in-line plastic package (E suffix). The CDP1882 is supplied in dual-in-line, hermetic side-brazed ceramic (D suffix) and in plastic (E suffix) packages. Pinouts CDP1881C (PDIP) TOP VIEW CLOCK 1 MA5 MA4 CDP1882, CDP1882C (PDIP, CERDIP) TOP VIEW CLOCK 1 18 VDD A8 MA5 2 17 A8 A9 MA4 3 16 A9 MA3 4 15 A10 MA2 5 14 A11 MA1 6 13 CS0 MA0 7 12 CS1 CE 8 11 CS2 VSS 9 10 CS3 20 VDD 2 19 3 18 MA3 4 17 A10 MA2 5 16 A11 MA1 6 15 CS0 MA0 7 14 CS1 MRD 8 13 CS2 MWR 9 12 CS3 VSS 10 11 CE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 4-1 File Number 1367.2 CDP1881C, CDP1882, CDP1882C Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1881C and CDP1882C. . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) 18 Lead PDIP . . . . . . . . . . . . . . . . . . . 85 N/A 20 Lead PDIP . . . . . . . . . . . . . . . . . . . 80 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 85 22 Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 ±1/32 In. (1.59 ± 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Recommended Operating Conditions At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: CDP1882 PARAMETER MIN MAX MIN MAX UNITS 4 10.5 4 6.5 V VSS VDD VSS VDD V DC Operating Voltage Range Input Voltage Range At TA = -40oC to +85oC, VDD ± 5%, Except as Noted: Static Electrical Specifications CONDITIONS PARAMETER Quiescent Device Current Output Low Drive (Sink) Current Output High Drive (Source) Current Output Voltage Low-Level (Note 2) Output Voltage High-Level (Note 2) Input Low Voltage Input High Voltage CDP1881C, CDP1882C CDP1882 CDP1881C, CDP1882C SYMBOL VO (V) VIN (V) VDD (V) MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX UNITS IDD - 0, 5 5 - 1 10 - 5 50 µA - 0, 10 10 - 10 100 - - - µA 0.4 0, 5 5 1.6 3.2 - 1.6 3.2 - mA 0.5 0, 10 10 3.2 6.4 - - - - mA 4.6 0, 5 5 -1.15 -2.3 - -1.15 -2.3 - mA 9.5 0, 10 10 -2.3 -4.6 - - - - mA - 0, 5 5 - 0 0.1 - 0 0.1 V - 0, 10 10 - 0 0.1 - - - V - 0, 5 5 4.9 5 - 4.9 5 - V - 0, 10 10 9.9 10 - - - - V 0.5, 4.5 - 5 - - 1.5 - - 1.5 V 1, 9 - 10 - - 3 - - - V 0.5, 9.5 - 5 3.5 - - 3.5 - - V 1, 9 - 10 7 - - - - - V IOL IOH VOL VOH VIL VIH 4-2 CDP1881C, CDP1882, CDP1882C At TA = -40oC to +85oC, VDD ± 5%, Except as Noted: (Continued) Static Electrical Specifications CONDITIONS CDP1882 CDP1881C, CDP1882C VO (V) VIN (V) VDD (V) MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX UNITS Any Input 0, 5 5 - - ±1 - - ±1 µA 0, 10 10 - - ±2 - - - µA 0, 5 0, 5 5 - - 2 - - 2 mA 0, 10 0, 10 10 - - 4 - - - mA CIN - - - - 5 7.5 - 5 7.5 pF Output Capacitance COUT - - - - 10 15 - 10 15 pF Minimum Data Retention Voltage VDR VDD = VDR - 2 2.4 - 2 2.4 V Data Retention Current IDR VDD = 2.4V - 0.01 1 - 0.5 5 µA PARAMETER SYMBOL Input Leakage Current IIN Operating Current (Note 2) IDD1 Input Capacitance NOTES: 1. Typical values are for TA = +25oC. 2. IOL = IOH = 1µA. 3. Operating current measured at 200kHz for VDD = 5V and 400kHz for VDD = 10V, with outputs open circuits (equivalent to typical CDP1800 system at 3.2MHz, 5V; and 6.4MHz, 10V). MA0 7 D Q 19 A8 MA0 7 C MA1 6 5 D Q MA1 18 A9 6 4 MA2 17 A10 D Q 5 3 16 A9 15 A10 D Q C MA3 16 A11 D Q 4 C MA4 D Q C C MA3 17 A8 C C MA2 D Q 14 A11 D Q C D Q MA4 15 CS0 3 C Q D Q 13 CS0 C Q 14 CS1 MA5 2 12 CS1 MA5 D Q 2 C Q D Q C Q 13 CS2 CLOCK 1 MRD 8 MWR 9 11 CS2 CLOCK 1 12 CS3 10 CS3 VDD = 20 CE VSS = 10 8 VDD = 18 VSS = 9 CE 11 FIGURE 1. FUNCTIONAL DIAGRAM FOR THE CDP1881C FIGURE 2. FUNCTIONAL DIAGRAM FOR THE CDP1882, CDP1882C 4-3 CDP1881C, CDP1882, CDP1882C TRUTH TABLE INPUTS OUTPUTS (NOTE 1) MWR (NOTE 1) MRD CE CLK MA4 MA5 CS0 CS1 CS2 CS3 1 1 X X X X 1 1 1 1 X X 1 X X X 1 1 1 1 0 X 0 1 0 0 0 1 1 1 0 X 0 1 1 0 1 0 1 1 0 X 0 1 0 1 1 1 0 1 0 X 0 1 1 1 1 1 1 0 0 X 0 0 X X X 0 0 1 0 0 0 1 1 1 X 0 0 1 1 0 1 0 1 1 X 0 0 1 0 1 1 1 0 1 X 0 0 1 1 1 1 1 1 0 X 0 0 0 X X Previous State Previous State NOTE: 1. CDP1881C Only INPUTS OUTPUTS CE CLK MA0, MA1, MA2, MA3 A8, A9, A10, A11 X 1 1 1 X 1 0 0 X 0 X Previous State Logic 1 = High, Logic 0 = Low, X = Don’t Care Dynamic Electrical Specifications at TA = -40oC to +85oC, VDD ± 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF, (See Figure 1) CDP1882 PARAMETER Minimum Setup Time tMACL Memory Address to CLOCK Minimum Hold Time tCLMA Memory Address After CLOCK Minimum CLOCK Pulse Width tCLCL CDP1881C, CDP1882C VDD (V) MIN (NOTE 1) TYP (NOTE 2) MAX MIN (NOTE 1) TYP (NOTE 2) MAX UNITS 5 - 10 35 - 10 35 ns 10 - 8 25 - - - ns 5 - 8 25 - 8 25 ns 10 - 8 25 - - - ns 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns 4-4 CDP1881C, CDP1882, CDP1882C Dynamic Electrical Specifications at TA = -40oC to +85oC, VDD ± 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF, (See Figure 1) (Continued) CDP1882 PARAMETER CDP1881C, CDP1882C VDD (V) MIN (NOTE 1) TYP (NOTE 2) MAX MIN (NOTE 1) TYP (NOTE 2) MAX UNITS 5 - 75 150 - 75 150 ns 10 - 45 100 - - - ns 5 - 75 150 - 75 150 ns 10 - 40 100 - - - ns 5 - 100 175 - 100 175 ns 10 - 65 125 - - - ns 5 - 100 175 - 100 175 ns 10 - 65 125 - - - ns 5 - 100 175 - 100 175 ns 10 - 75 125 - - - ns 5 - 80 125 - 80 125 ns 10 - 40 60 - - - ns PROPAGATION DELAY TIMES Chip Enable to Chip Select tCECS MRD or MRW to Chip Select (Note 3) CLOCK to Chip Select tMCS tCLCS CLOCK to Address tCLA Memory Address to Chip Select Memory Address to Address tMACS tMAA NOTES: 1. Typical values are for TA = 25oC. 2. Maximum limits of minimum characteristics are the values above which all devices function. 3. For CDP1881C type only. VALID CHIP ENABLE CE tCECS tCECS CS0, CS1, CS2, CS3 (A) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY MRD OR MWR tMCS tMCS CS0, CS1, CS2, CS3 (B) MRD OR MWR TO CHIP SELECT PROPAGATION DELAY (CDP1881C ONLY) MA0 - MA5 tMACL tCLMA CLOCK tCLCL tCLCS tMACS tMACS CS0, CS1, CS2, CS3 tMAA tCLA A8 - A11 (C) MEMORY ADDRESS SETUP AND HOLD TIME FIGURE 3. TIMING WAVEFORMS 4-5 tMAA CDP1881C, CDP1882, CDP1882C Signal Descriptions/Pin Functions Application Information CLOCK: Latch-Input Control - a high at the clock input will allow data to pass through the latch to the output pin. Data is latched on the high to low transition of the clock input. This input is connected to TPA in CDP1800-series systems. The CDP1881C, CDP1882, CDP1882C can interface directly with the multiplexed address bus of the CDP1800series microprocessor family at maximum clock frequency. A single CDP1881C or CDP1882 is capable of decoding up to 16K-bytes of memory. MA0 - MA3: Address inputs to the high-byte address latches. MA4 - MA5: High byte address inputs decoded to produce chip selects CS0 - CS3. MRD, MWR: MEMORY READ (MRD) and MEMORY WRITE (MWR) signal inputs on the CDP1881C. A low at either input, when the CE pin is low, will enable the decoder chip select outputs (CS0 - CS3). CE: CHIP ENABLE input - a low at the CE input of CDP1882, CDP1882C will enable the chip select decoder. A low at the CE input of CDP1881C, coincident with a low at either MRD or MRW pin, will enable the chip select decoder. A high on this pin forces CS0, CS1, CS2, and CS3 to a high (false) state. A8 - A11: Latched high-byte address outputs. CS0 - CS3: One of four latched and decoded Chip Select outputs. VDD, VSS: Power and ground pins, respectively. The CDP1881C is provided with MRD and MWR inputs for controlling bus contention, and is especially useful for interfacing with RAMs that do not have an output enable function (OE). Figure 4 shows the CDP1881C in a minimum system configuration which includes the CDP1833 ROM (1K x 8) and two 2K x 8 RAMS. The CDP1881C in this example performs the following functions: 1) Latch and decode high-order address bits for use as chip selects. 2) Gate chip selects with MRD and MWR to prevent bus contention with the CPU. 3) Latch high-order address bits A8 to A11. A system using the CDP1882 is shown in Figure 5. The CDP1882 performs the memory address latch and decoder functions. Note that the RAM has an output enable (OE) pin which eliminates the need for MRD and MWR inputs on the latch/decoder. Instead, the MRD line is connected directly to the RAM output enable (OE) pin. In Figure 6 the CDP1882 is used to decode a 16K-byte ROM system consisting of four CDM5332s. ADDRESS BUS MA0 - MA5 A0 - A7 WAIT CLR TPA CDP1800 SERIES CPU A0 - A7 (2) 2K x 8 RAMS CLK TPA CDP1883 1K x 8 ROM CDP1881C LATCH/ DECODER A8 - A10 A11 CEA (NOTE 1) CEB (NOTE 1) CS0 CS1 CEO MRD MRD CE CS2 MRD CS3 MWR MWR DATA BUS NOTE: CEA = CE RAM NUMBER 1 CEB = CE RAM NUMBER 2 FIGURE 4. MINIMUM 1800-SERIES USING THE CDP1881C 4-6 CS R/W CDP1881C, CDP1882, CDP1882C CDP1882 LATCH/ DECODER CS3 CLK CS2 CE TO OTHER CHIP SELECTS CS1 CS0 MA0 - MA5 A8 - A11 WAIT ADDRESS BUS CLR A8 - A11 CS2 TPA CDP1800 SERIES CPU ADDRESS BUS A8 - A10 CE A0 - A7 A0 - A7 CDM6116A 2K x 8 RAM CDM5332 4K x 8 ROM OE CSI/OE MRD MWR WE DATA BUS FIGURE 5. CDP1800-SERIES SYSTEM USING THE CDP1882 CDP1882 LATCH/ DECODER CS3 CLK CE CS2 CS1 CS0 MA0 - MA5 A8 - A11 WAIT ADDRESS BUS CLR A8 - A11 TPA A8 - A11 ADDRESS BUS CDP1800 SERIES CPU MRD A0 - A7 CDM5332 4K x 8 ROM CSI/OE A8 - A11 CS2 CS2 A0 - A7 CDM5332 4K x 8 ROM CSI/OE A0 - A7 CDM5332 4K x 8 ROM CSI/OE DATA BUS FIGURE 6. 6K-BYTE ROM SYSTEMS USING THE CDP1882 4-7 A8 - A11 CS2 CS2 A0 - A7 CDM5332 4K x 8 ROM CSI/OE CDP1881C, CDP1882, CDP1882C All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 8 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029