Semiconductor February 1999 ADSL Analog Front End Chip Features Description • 14-Bit 5 MSPS DAC The HC6094 performs the Analog processing for the ADSL chip set. The transmit chain has a 14 Bit DAC, a third-order Chebyshev reconstruction filter and a programmable attenuator (-12 to 0dB) capable of driving a 220Ω differential load. The receiver chain has a high impedance input stage, programmable gain stage (0 to 24dB), additional programmable gain (-9 to 18dB) and a third-order Chebyshev anti-aliasing filter for driving an off-chip A/D. • Programmable Gain Stages • Anti-Aliasing and Reconstruction Filters Applications • FDM DMT ADSL Laser trimmable thin-film resistors are used to set the filter cutoff frequency and DAC linearity. The transmit and receive signal chains are specified at 65dB MTPR. • CAP ADSL • EC DMT ADSL • Communications Receiver Ordering Information PART NUMBER TEMP. RANGE (oC) HC6094IN -40 to 85 PACKAGE PKG. NO. 44 Ld MQFP Q44.10x10 Pinout D11 D10 TXO+ TXO- VDDA_ATT GNDA_TX CTLOUT CTLIN GNDD_TX CLK VDDD_TX D13 (MSB) D12 HC6094 (MQFP) TOP VIEW 44 43 42 41 40 39 38 37 36 35 34 33 2 32 1 VSSA_ATT VDDA_TX VDDD_RX D6 6 28 CS D5 7 27 SDI D4 8 26 RST D3 9 25 SCLK D2 10 24 GNDD__RX D1 11 23 12 13 14 15 16 17 18 19 20 21 22 VSSA_TX GNDA_RX RXI- RXI+ 29 PGAO- 5 PGAO+ ARTN D7 PGAI+ 30 PGAI- 4 VDDA_RX D8 VSSA_RX 31 RXO- 3 RXO+ D9 D0 (LSB) [ /Title (HC60 94) /Subject (ADSL Analog Front End Chip) /Autho r () /Keywords (Harris Semiconductor, Telecom, SLICs, SLACs , Telephone, Telephony, WLL, Wireless Local Loop, PBX, Private Branch Exchan ge, NT1+, CO, Cen- HC6094 T UCT ROD ACEMEN 47 P E 7 T L OLE REP 00-442-7 OBS ENDED 8 M ns 1 .com COM pplicatio @harris E R NO ntral A entapp Ce : c Call or email CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1999 1 File Number 4260.2 HC6094 Functional Block Diagram CLK TRANSMITTER -12 TO 0dB PGA0 14 DAC D0-D13 1ST ORDER 1.1MHz LPF TX O± 2ND ORDER 1.1MHz LPF LATCH SCLK SDI SHIFT REGISTER AND LATCHES CS RST RXO+ 2ND ORDER 1.1MHz LPF 1ST ORDER 1.1MHz LPF RECEIVER RXI± PGA2 PGA1 -9 TO 18dB 0 TO 24dB PGAI± PGAO± Typical Setup VSSA_TX CTLIN CTLOUT -12 TO 0dB 14 PGA0 D0-D13 DAC CLK 1ST ORDER 1.1MHz LPF + TX O± 2ND ORDER 1.1MHz LPF RL = 220 SCLK SDI VDDD_TX, RX +5V VDDA_TX, RX +5V CS VSSA_TX, RX -5V RST GNDD_TX, RX SHIFT REGISTER AND LATCHES GNDA_RX, TX -9 TO 18dB 0 TO 24dB PGA2 PGA1 + RXO± RL = 2000 2ND ORDER 1.1MHz LPF RXI± 1ST ORDER 1.1MHz LPF RECEIVER PGA IN 2 PGA OUT HC6094 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.18W Maximum Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5.5V Analog Input Voltage to Ground . . . . . . . . . . . . VDD +0.5, VSS -0.5V Digital Input Voltage to Ground. . . . . . . . . . . . . . . .VDD +0.5V, -0.5V Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER VDD = 5V, VSS = -5V, RL Open, Over Temperature Range; Unless Otherwise Specified. Designed for ±5% Power Supply. TEST CONDITIONS SYMBOL MIN TYP MAX UNITS OVERALL Supply Currents Power Dissipation IDD VDD (Note 2) - 66 - mA ISS VSS (Note 3) - -79 - mA ICC VCC - 0 - µA PD Quiescent, No Load - 725 - mW - - 0.8 V DIGITAL INTERFACE Input Voltage Thresholds VIL VIH 2.7 - - V IIL VIN = 0V -10.0 0 10.0 µA IIH VIN = VDD -10.0 0 10.0 µA T1 0.1 - 5.0 µs CS Active Before Shift Edge T2 T1/2 -10 - - ns Write Data Valid After Shift Edge T3 - - 10 ns Input Currents Serial Clock Period CS Inactive After Latch Edge T4 T1 - 10 - T1 +10 ns Write Data Hold After Latch Edge T5 T1/2 -5 - T1/2 +5 ns DAC Setup Time tS - - 100 ns DAC Hold Time tH - - 100 ns 14 - - Bits 14-BIT DAC Resolution/Monotonicity Integral Linearity ILE Differential Linearity DLE Measured at TX Outputs Max Sample Rate - ±1.5 - LSB - ±0.9 - LSB 4.416 - - Ms/s TRANSMITTER OUTPUT Output Drive TXOD Sink or Source Differential Output Swing TXOS RL = 220Ω Differential Balance TXDB Gain Match Between Outputs Transmit Output Offset TXOFF Multi-Tone Power Ratio TXMTPR Power Supply Rejection PSRR Max Gain Single Ended (Note 4) RL = 220Ω 30 55 - mA 11.7 12.03 12.3 VPP - 0.5 - % -200 25 200 mV - 65 - dB Input Referred - VDD 40 65 - dB Input Referred - VSS 55 84 - dB 3 HC6094 Electrical Specifications PARAMETER VDD = 5V, VSS = -5V, RL Open, Over Temperature Range; Unless Otherwise Specified. Designed for ±5% Power Supply. (Continued) TEST CONDITIONS SYMBOL MIN TYP MAX UNITS RL = 220Ω, 0dB Setting -0.22 +0.02 0.22 dB RL= 220Ω, Each Step Relative to 0dB -0.15 0.02 0.15 dB TRANSMITTER GAIN STAGE Gain Error TXPG TRANSMITTER FREQUENCY RESPONSE Gain Ripple Peak to Peak GP Across 1.104MHz Bandwidth - 0.2 0.6 dB Stopband Attenuation GS At 2.65MHz 14 17 - dB Floor Attenuation GM At 9.94MHz - 58 - dB - - 12 VPP - MΩ RECEIVER INPUT (PGA1 AND PGA2) Input Swing Input Impedance RXIS RXRIN Common Mode Rejection RXCMRR Common Mode Range RXCMIR Differential PGA1 1.0 PGA2 1.0 12 - kΩ - 90 - dB -0.25 - 1.1MHz Continuous Input Voltage VSS-0.5 0.25 V VDD +0.5 V RECEIVER OUTPUT (INCLUDING PGA1 OUT) Differential Output Swing RXOS Differential Balance RXDB PGA1 Output Offset RXOFF PGA2 Output Offset RXOFF Multi-Tone Power Ratio RXMTPR Power Supply Rejection PSRR RXOUT (RL = 2000Ω) 12.0 15.8 - VPP PGA1OUT (RL = 2000Ω) 12.0 16.0 - VPP - 0.5 - % Max Gain Single Ended (Note 4) -200 40 200 mV Max Gain Single Ended (Note 4) -200 30 200 mV End to End (RXIN to RXOUT) RL = 2000Ω - 65 - dB Input Referred - VDD 45 69 - dB Input Referred - VSS 55 84 - dB -0.3 0.01 0.3 dB - 0.4 0.6 dB RECEIVER GAIN STAGE Absolute Gain Error RXPG Any Step (RXIN to RXOUT) RECEIVER FREQUENCY RESPONSE Gain Ripple Peak to Peak GP Across 1.104MHz Bandwidth Stopband Attenuation GS At 2.65MHz 14 19.4 - dB Floor Attenuation GM At 9.94MHz - 53 - dB TRANSMITTER AND RECEIVER FILTER CUTOFF FREQUENCY TX Filter FC TXFC -0.15dB point 1.104 1.18 1.25 MHz RX Filter FC RXFC -0.15dB point 1.104 1.125 1.16 MHz NOTES: 2. VDD = 5V typical, supply range ±5%. 3. VSS = -5V typical, supply range ±5%. 4. Single ended operation for reference only. Probed to these limits, but not packaged tested. 4 HC6094 Definitions 1. Supply currents/power dissipation measured in a quiescent (static) state with RL open. 2. Logic input levels and timing are verified by using them as conditions for testing DAC and filter. 3. Digital input currents are measured at 0V and VCC. 4. DAC resolution and monotonicity guaranteed by ILE and DLE tests. 5. DAC ILE is relative to best fit straight line. 6. Output drive current is the output current at 0V for each output when they are driven to ± Full Scale. 7. Output offset measured with VIN = 0V differential for the RX, and the DAC at mid scale for the TX. 8. PSRR is the change in differential input voltage vs. change in supply voltage at DC. 9. TX Gain is calculated as 20*Log((TXoutDACFS - TXoutDACZS)/12V) at DC. 10. RX input swing is verified by using this as condition for gain testing. 11. RX Input Impedance is calculated as ∆VIN/∆IIN where VIN is the maximum input voltages, with the PGA set to 0dB. 12. RX CMRR is calculated as 20*Log(VOUT/VIN)-PGA Gain. VIN is set to 250mVPEAK (CMIR) at 1.1MHz, and PGA gain is set to maximum. 13. RX Gain is calculated as 20*Log(dVOUT/dVIN), where VIN is set to give a nominal ± Output Swing, or the maximum input swing, whichever is smaller. It is tested DC. 14. Filter Gain/Attenuation is relative to low frequency passband gain. TX tested by driving the DAC (with sinX/X correction), RX tested by driving PGA2. Wafer probe will use special test points to bypass the DAC for laser trimming. 15. MTPR - (Multi-Tone Power Ratio). A DMT waveform is generated which has a specific crest factor or peak to average ratio (PAR) with specific carriers missing. The waveform is then passed through the TX or RX chain. The total integrated power of the notch at the location of the missing carriers is measured with respect to the adjacent carriers. Notch depth is measured for several DMT waveforms with different PARs. The notch depths for each DMT waveform are averaged to give an MTPR number. 5 HC6094 Shift Register Format Each write operation to a control register involves 16 bits of data. The CS- signal must be enabled low during any serial write operation. The data on SDI shall be clocked in during the rising edge of SCLK. A3-A0 supply the address of the control register, and D7-D0 supply the data. CS- SCLK SDI 0 A0 A1 A2 A3 0 0 0 D0 D1 D2 D3 D4 D5 D6 D7 FIGURE 1. SERIAL CONTROL Logic Timing Definitions CS SCLK t2 t1 t4 SCLK SDI t3 t5 FIGURE 2. SERIAL INTERFACE CLK DAC DATA tS tH FIGURE 3. DAC INTERFACE 6 HC6094 Shift Registers Format REGISTER A0 A1 A2 A3 RX Gain 1 0 X X TX Gain 0 0 X X D0 D1 D2 D3 D4 PGA1 Gain TX PGA0 GAIN D1 D0 1 1 X -12 1 0 1 -10 1 0 0 -8 0 1 1 -6 0 1 0 -4 0 0 1 -2 0 0 0 0 GAIN IN dB RX PGA1 GAIN D3 D2 D1 D0 GAIN IN dB 0 0 0 0 0 0 0 0 1 3 0 0 1 0 6 0 0 1 1 9 0 1 0 0 12 0 1 0 1 15 0 1 1 0 18 0 1 1 1 21 1 X X X 24 NOTE: PGA1 is an inverting amplifier. RX PGA2 GAIN D7 D6 D5 D4 GAIN IN dB 0 0 0 0 -9 0 0 0 1 -6 0 0 1 0 -3 0 0 1 1 0 0 1 0 0 3 0 1 0 1 6 0 1 1 0 9 0 1 1 1 12 1 X X 0 15 1 X X 1 18 Filter Mask Template AVERAGE GP PASSBAND -GP GAIN GS GM 1.104 2.65 9.94 FREQUENCY (MHz) 7 D6 PGA2 Gain PGA0 Gain D2 D5 D7 HC6094 Pin Descriptions PIN NUMBER PIN NAME 43, 44 D13-D12 Digital Input bits 13 and 12. D13 is MSB. 1-12 D11-D0 Digital Input bits 11 thru 0. D0 is LSB. 13, 14 RXO± 15 VSSA_RX Receiver -5V supply. 16 VDDA_RX Receiver +5V supply. 17, 18 PGAI± PGA2 differential inputs. 19, 20 PGAO± PGA1 differential outputs. 21, 22 RXI± 23 GNDA_RX Receiver ground. 24 GNDD_RX Serial interface ground. 25 SCLK Serial interface clock pin. 26 RST Serial interface reset pin. 27 SDI Serial interface data input. 28 CS Serial interface chip select. 29 VDDD_RX 30 ARTN Analog return (ground). 31 VSSA_TX Transmitter -5V supply. 32 VDDA_TX Transmitter +5V supply. 33 VSSA_ATT Attenuator -5V supply. 34, 35 TXO± 36 VDDA_ATT Attenuator +5V supply. 37 GNDA_TX Analog ground for transmitter. 38 CTLOUT Control Amplifier Output. Provides precision control of the current sources. Typically connected to CTLIN. 39 CTLIN Input to the Current Source Base Rail. Typically connected to CTLOUT. Requires a 0.1µF capacitor to VSSA_TX. Allows external decoupling of the current sources. 40 GNDD_TX 41 CLK 42 VDDD_TX PIN DESCRIPTION Receiver differential outputs. Receiver differential inputs (PGA1 inputs). Shift register Digital +5V supply. Transmitter differential outputs. Digital Ground. DAC input latch clock. DAC digital +5V supply. 8 HC6094 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) Q44.10x10 (JEDEC MO-108AA-2 ISSUE A) D 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D1 -D- -B- -AE E1 e PIN 1 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.093 - 2.35 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - B 0.012 0.018 0.30 0.45 6 B1 0.012 0.016 0.30 0.40 - D 0.510 0.530 12.95 13.45 3 D1 0.390 0.398 9.90 10.10 4, 5 E 0.510 0.530 12.95 13.45 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.026 0.037 0.65 0.95 N 44 44 e 0.032 BSC 0.80 BSC SEATING A PLANE -H- 7 Rev. 1 1/94 NOTES: 0.10 0.004 0.40 0.016 MIN -C- 5o-16o 0.20 A-B S 0.008 M C 0o MIN A2 A1 L 5o-16o 2. All dimensions and tolerances per ANSI Y14.5M-1982. D S 3. Dimensions D and E to be determined at seating plane -C- . B 4. Dimensions D1 and E1 to be determined at datum plane -H- . B1 0o-7o 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 0.13/0.17 0.005/0.007 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. BASE METAL WITH PLATING 0.13/0.23 0.005/0.009 9