Dec 2005 Negative High Voltage Hot Swap Controllers Incorporate an Accurate Supply Monitor and Power Module Sequencing

DESIGN FEATURES
Negative High Voltage Hot Swap
Controllers Incorporate an Accurate
Supply Monitor and Power Module
Sequencing
by Kevin Wong
Introduction
Typical Application
When a circuit board is inserted into a
live backplane slot, discharged supply
bypass capacitors on the board can
draw large transient currents from
the system supplies. In high-voltage
systems like the –48V backplanes
prevalent in high reliability telecom
systems, such transients can reach
hundreds of amps and damage connector pins, PCB traces and board
components. In addition, current
spikes can cause voltage glitches on
the power bus, causing other boards
in the system to reset. This is particularly unacceptable in telecom systems
where the ability to safely Hot Swap
modules is a primary system requirement.
The LTC4253A and LTC4253A-ADJ
facilitate safe board insertion and
removal from a live backplane by applying power in a controlled manner.
Running off a simple, fast responding
– 48V RTN
(LONG PIN)
shunt regulated supply that allows
very high voltage operation, they are
uniquely suited for applications on
the –48V bus.
User programmable, high accuracy
undervoltage and overvoltage detectors
act as supply monitors and ensure the
supply is stable and within tolerance
before applying power to the load. An
inrush current control loop then takes
over, resulting in a controlled startup
current profile. When the external pass
transistor is fully enhanced, Power
Good status outputs then allow time
adjustable or load feedback enabled
sequencing of up to four load modules.
Short circuits or excessive supply
current events trigger protective circuits which quickly isolate the fault
to prevent glitching of the backplane
supply. With all these features, these
devices offer a comprehensive solution
for –48V Hot Swap applications.
R3 22k
RIN
10k
20k(1/4W)/2
VIN1
R5
2.2k
R4
2.2k
CIN
1µF
PUSH
RESET
– 48V RTN
(SHORT PIN)
Q2
FZT857
Figure 1 shows a typical –48V Hot
Swap application using the LTC4253A.
The LTC4253A floats on the negative
rail and uses an internal shunt regulator that together with RIN and CIN,
regulates VIN to about 13V above the
negative rail. The MOSFET N-channel
transistor Q1 is placed in the power
path to control turn on and turn off
with input from resistor RS which
senses the load current. RC and CC
provides compensation for the current
limit loop. R1 and R2 form a resistive
divider that allows MOSFET turn on
only when the –48V supply is between
the user programmed undervoltage
and overvoltage thresholds. The resistive divider R1/R2 connects to the
–48V RTN rail via a short pin so that
during plug in, the MOSFET is held
off by the undervoltage condition until
the longer power pins are properly
seated. The five opto-couplers form an
CL
100µF
R6
2.2k
+
POWER
MODULE 1
POWER
MODULE 2
EN
EN
POWER
MODULE 3
EN
CSS 33nF
UV
PWRGD1
OV
PWRGD2
RESET
PWRGD3
EN2
SS
DRAIN
R9
47k
CSQ
0.1µF
TIMER
CT
0.68µF
VEE
EN2
VIN1
RD 1M
Q1
IRF530S
GATE
SENSE
POWER
MODULE 2
OUTPUT
EN3
EN3
SQTIMER
– 48V
(LONG PIN)
†
†
LTC4253A
C1
10nF
R1
30.1k
1%
†
VIN
R2
392k
1%
RC
10Ω
CC
10nF
RS
0.02Ω
VIN1
R7
POWER
MODULE 1
OUTPUT
R8
†
†
†MOC207
Figure 1. –48V/2.5A Hot Swap controller with opto-isolated Power Good sequencing
16
Linear Technology Magazine • December 2005
DESIGN FEATURES
–48RTN
(SHORT PIN)
R3
392k
1%
OV SHUTDOWN = 71.8V
OV RECOVERY = 70.3
UV RECOVERY =38V
UV SHUTDOWN = 34V
LTC4253A
UV
R2
4.32k
1%
C1
10nF
OV
R1
30.1k
1%
–48V
(LONG PIN)
VEE
Figure 2. Undervoltage and overvoltage
resistive divider connection to the LTC4253A
electrically isolated interface between
LTC4253A and the load modules for
power sequencing.
Undervoltage and
Overvoltage Detection
The LTC4253A and LTC4253A-ADJ
have 1% accurate undervoltage and
overvoltage threshold detectors that
can be set to any desired power supply range. This level of accuracy and
flexibility allow these parts to be easily
designed to conform to any operating
UVL
UV
1
VIN
ranges specified by the various prevailing –48V standards.
In the LTC4253A, an UV hysteretic
comparator detects undervoltage conditions at the UV pin, with the following
thresholds (with respect to VEE):
❑ UV low-to-high (VUV) = 3.08V
❑ UV low-to-high hysteresis (VUVHST)
= 0.324V
An OV hysteretic comparator detects overvoltage conditions at the OV
pin, with the following thresholds(with
respect to VEE):
❑ OV low-to-high (VOV) = 5.09V
❑ OV low-to-high hysteresis
(VOVHST) = 0.102V
The undervoltage recovery and
overvoltage shutdown thresholds
are designed to match the standard
telecom operating range of 43V to
71V with the UV and OV pins shorted
as in Figure 1. The undervoltage
shutdown and overvoltage recovery
thresholds are then 38.5V and 69.6V
respectively. The UV and OV pins can
also be separated for implementing
different operating ranges as shown
in Figure 2.
UVIN
–
3.08V
+
OVL
UVD
2
3
OV
4
VLKO
1
VIN
36V
(UNDERVOLTAGE
SHUTDOWN
VOLTAGE)
38V
(UNDERVOLTAGE
RECOVERY VOLTAGE)
(–48V RTN)
SHORT PIN
UVD
OVD
UVLO
UNDERVOLTAGE
SHUTDOWN
NORMAL OPERATION
a. Undervoltage comparator
+
OVD
3
71V
(OVERVOLTAGE
SHUTDOWN VOLTAGE)
OVIN
UNDERVOLTAGE
SHUTDOWN
OVIN
4
OV
0VL
UVLO
NORMAL
OPERATION
69V
(OVERVOLTAGE
RECOVERY
VOLTAGE)
VOVLO
5.08V
VOVHI
5.09V
OVL
OV
UV
–
VLKO
(–48V RTN)
SHORT PIN
UVL
UV
UVL
5.09V
2
VUVLO
3.08V
VUVHI
3.08V
UVIN
The LTC4253A-ADJ offers additional flexibility in allowing the user to
implement any required undervoltage
recovery, undervoltage shutdown,
overvoltage recovery and overvoltage
shutdown thresholds. It achieves
this by having two extra pins UVL
and OVL connected to the internal
comparators as shown in Figure 3.
The undervoltage comparator has
multiplexed inputs from UVL and
UV, which is tapped off a resistive
string across the power supply as in
Figure 4. When comparator output
UVD is high, UV is multiplexed to the
comparator input UVIN. When UVD
is low, UVL is multiplexed to UVIN.
The overvoltage comparator similarly
implements the overvoltage function.
The various thresholds to note are
(with respect to VEE):
❑ UV low-to-high (VUVHI) = 3.08V
❑ UVL high-to-low (VUVLO) = 3.08V
❑ OV low-to-high (VOVHI) = 5.09V
❑ OVL high-to-low (VOVLO) = 5.08V
By tapping UVL, UV, OVL and
OV off a resistive string across the
power supply, undervoltage recov-
OVERVOLTAGE SHUTDOWN
NORMAL
OPERATION
b. Overvoltage comparator
Figure 3. The LTC4253A-ADJ UV/OV detector block
Linear Technology Magazine • December 2005
17
DESIGN FEATURES
– 48V RTN
(LONG PIN)
+
RIN
10k
20k(1/4W)/2
– 48V RTN
(SHORT PIN)
294k
1%
2.74k
1%
CIN
1µF
R5
VIN EN2 EN3
LTC4253A-ADJ
UVL
R4
2.37k
1%
R3
2.1k
1%
VIN
UV
OVL
PWRGD1
OV
PWRGD3
R2
20k
1%
CSQ
0.1µF
POWER
MODULE 1
EN
POWER
MODULE 2
EN
POWER
MODULE 3
EN
†
POWER
MODULE 4
EN
†
R10
3k
†
RD
1M
VOUT
SS
TIMER
VEE
Q1
IRF530S
GATE
SENSE
SEL
RC
10Ω
CC
10nF
CT
0.68µF
– 48V
(LONG PIN)
R9
100k
C3
0.1µF
R8
100k
DRAIN
SQTIMER
R1
20k
1%
R7
100k
PWRGD2
RESET
C1 10nF
CSS 33nF
R6
100k
C2
100µF
RS
0.02Ω
†
FMMT493
Figure 4. A –48V/2.5A Hot Swap controller with transistor enabled Power Good sequencing
ery = 43V, undervoltage shutdown
= 39V, overvoltage recovery = 78V
and overvoltage shutdown = 82V are
implemented in Figure 4. Any required
supply operating range can thus be
implemented with great accuracy.
dI/dt Soft Start
The LTC4253A offers a current soft
start pin (SS) that acts as the reference
for the analog current limit amplifier (VACL = VSS/20). By attaching a
capacitor at the SS pin, the analog
current limit threshold ramps up in
an exponential profile with an RC time
constant equal to 50kΩ • CSS. The
analog current limit amplifier forces
the inrush current to follow this profile
when the GATE pin rises above the
external MOSFET threshold and turns
on the MOSFET. In this way, inrush
current ramps up with a controlled
slew rate (dI/dt) that is approximately
fixed and adjustable by CSS (Figure 5a).
Controlling the load current slew rate
reduces system EMI and disturbances
to the supply rail during startup.
The LTC4253A-ADJ offers an additional mode when the SEL pin is held
low (it has an internal pullup to VIN
of 20μA ). In this mode, the SS pin is
servoed from the time the GATE pin
is released until it clears the external
MOSFET threshold and turns the
MOSFET on. The result is that the
LTC4253A-ADJ enters analog current
limit with VACL ramping up from close
to zero. The resultant inrush current
GATE
10V
GATE
10V
SS
1V
SS
1V
SENSE
50mV
SENSE
50mV
VOUT
50V
VOUT
50V
1ms/DIV
1ms/DIV
a. dI/dt inrush current control using the
LTC4253A or LTC4253A-ADJ with SEL = 1
(Figure 1 circuit)
b. Enhanced dI/dt inrush current control
using the LTC4253A-ADJ with SEL = 0
(Figure 4 circuit)
Figure 5. dI/dt soft-start waveforms
18
profile presents a smooth ramp up
from zero and the load current slew
rate is able to maintain an approximately fixed dI/dt gradient right from
turn on (Figure 5b). This dI/dt gradient
is similarly adjustable by CSS.
Power Good Sequencing
The LTC4253A has three sequenced
PWRGD outputs and two enable (EN)
inputs. This allows three load modules
to be enabled sequentially, minimizing
any sudden load power demand on the
backplane supply.
The three load modules can be timer
sequenced as in Figure 4 where the
EN pins are enabled by tying them to
VIN. The three PWRGD signals assert
sequentially with a fixed time delay
adjustable by capacitor CSQ (approximate TD = 600ms • (CSQ/1µF)). The
load modules can also be load feedback sequenced as in Figure 1 where
the load modules control the EN pin
inputs. In this way when Load Module
1 is enabled by PWRGD1 and fully
started up, it can signal back via the
EN2 input to enable Load Module 2,
which is enabled after one SQTIMER
delay ramp. Load Module 2 can similarly enable Load Module 3 when it
is ready. This mode of sequencing is
shown in Figure 6.
The interface between the Hot Swap
controller and the load modules is
implemented with opto-couplers as in
Figure 1 to take care of the differing
Linear Technology Magazine • December 2005
DESIGN FEATURES
signal common. If the load modules’
EN inputs have sufficient protection
against negative bias current, a simpler NPN interface can be implemented
as in Figure 4.
Figure 7 highlights an additional
feature of the LTC4253A-ADJ. The
PWRGD1 signal only activates after
one SQTIMER ramp delay from the
time GATE goes high and DRAIN goes
low. This feature can be exploited to
provide an additional EN1 signal so up
to four load modules can be sequenced
as in Figure 4.
VOUT
50V/DIV
VOUT
50V/DIV
GATE
10V/DIV
GATE
10V/DIV
SQTIMER
5V/DIV
SQTIMER
5V/DIV
PWRGD1
10V/DIV
EN1
2V/DIV
PWRGD1
10V/DIV
EN2
10V/DIV
Short Circuit Operation
Current faults are controlled in three
stages using three thresholds: 50mV
for a timed circuit breaker function,
60mV for an analog current limit loop
and 200mV for a fast comparator
that limits peak current in the event
of a catastrophic short-circuit. This
three-stage fault current minimizes
backplane supply disturbances due
to current faults.
A voltage across the SENSE resistor (RS) of greater than 50mV triggers
TIMER to source 200µA into a timing
capacitor CT. CT eventually charges to
a 4V threshold and the part latches
off. If the fault goes away before CT
reaches 4V, CT slowly discharges (5µA).
A low impedance short can glitch the
voltage across RS above 200mV. This
triggers a fast comparator that asserts
a hard pulldown on the MOSFET gate
to quickly bring the voltage across RS
PWRGD2
10V/DIV
PWRGD2
10V/DIV
PWRGD3
10V/DIV
EN3
10V/DIV
50ms/DIV
PWRGD3
10V/DIV
50ms/DIV
Figure 6. The LTC4253A controlling
the turn on of three load modules
using Load Feedback Sequencing
back below 200mV. This effectively
limits the initial transient fault current. An analog current limit loop
then controls the voltage across RS
to 60mV until TIMER reaches 4V (see
Figure 8).
RD in Figure 1 allows the MOSFET
drain to pump current into the DRAIN
pin internally clamped at around
SUPPLY RING OWING
TO MOSFET TURN-OFF
–48V RTN
50V
SENSE
200mV
SUPPLY RING OWING
TO CURRENT OVERSHOOT
TRACE 1
ONSET OF OUTPUT
SHORT CIRCUIT
TRACE 2
GATE
10V
FAST CURRENT LIMIT
ANALOG CURRENT LIMIT
TIMER
5V
CTIMER RAMP
TRACE 3
TRACE 4
LATCH OFF
0.5ms/DIV
Figure 8. Output short-circuit waveforms
Linear Technology Magazine • December 2005
Figure 7. The LTC4253A-ADJ
controlling the turn on of four load
modules using Timing Sequencing
6V. This current is multiplied up by
eight times and added to the 200μA
circuit breaker TIMER pullup current.
This adds a component to the circuit
breaker timeout period that is linearly
proportional to the VDS of the MOSFET,
thus allowing the MOSFET to be designed to function closer to its SOA
limits under different conditions.
Conclusion
The LTC4253A and LTC4253A-ADJ
inherit the proven capabilities of
Linear Technology’s –48V Hot Swap
family and add enhanced features.
Chief among these is a highly flexible
and 1% accurate undervoltage and
overvoltage detection capability. Additional features include enhanced
slew rate controlled inrush current
profile and the ability to sequence up
to four load modules. The LTC4253A
is available in a 16-pin SSOP package
and is completely pin compatible to
the LTC4253. The LTC4253A-ADJ is
available in a 20-pin SSOP package
as well as a 20-pin 4mm × 4mm QFN
package.
Authors can be contacted
at (408) 432-1900
19
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