ISL8723, ISL8724 ® Data Sheet December 21, 2006 FN6413.0 Power Sequencing Controllers Features The Intersil ISL8723 and ISL8724 are 4 channel sequencers controlling the on and off sequence of voltages with under voltage supply fault protection and a “sequence completed” signal (RESET#). For larger systems, more than 4 voltages can be sequenced by a simple connection of multiple IC's. These sequencers use an integrated charge pump to drive 4 external low-cost N-channel MOSFET switch gates above the IC bias voltage by 5.3V. These IC's can be biased from and control any supply from 2.5V to 5V and additionally monitor any voltage above 0.7V. Individual product descriptions are below. • Enables arbitrary turn-on and turn-off sequencing of up to four power supplies (0.7V to 5V) The four channel ISL8723 (ENABLE input), ISL8724 (ENABLE# input) offer the designer 4 voltage control when it is required that all four rails are in minimal compliance prior to turn on and that compliance must be maintained during operation. The ISL8723 has a low power standby mode when it is disabled suitable for battery powered applications. • 30µA Sleep State (ISL8723) External resistors provide flexible voltage threshold programming of monitored voltages. Delay and sequencing timing are programmable by external capacitors for both ramp up and ramp down. TEMP. RANGE PART (°C) MARKING • Active high (ISL8723) or low (ISL8724) ENABLE# input • Pb-free plus anneal available (RoHS compliant) QFN Package Applications • Graphics cards • FPGA/ASIC/microprocessor/PowerPC supply sequencing • Network Routers Pinout PACKAGE PKG. DWG. # ISL8723, ISL8724 (24 LD QFN) TOP VIEW 1 UVLO_A NC 23 22 21 20 19 1 18 DLY_OFF_A GATE_A 2 17 UVLO_C DLY_OFF_C 3 16 DLY_ON_C 4mmx4mm 4 15 DLY_ON_D GATE_B 5 14 UVLO_D GATE_C 6 13 DLY_OFF_B 7 8 9 10 11 12 UVLO_B DLY_OFF_D NC NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 24 ENABLE/ ENABLE# GND Evaluation Platform DLY_ON_A -40 to +85 24 Ld 4x4 QFN L24.4x4 (Pb-free) L24.4x4 Tape & Reel SYSRST# -40 to +85 24 Ld 4x4 QFN L24.4x4 (Pb-free) L24.4x4 NC ISL8723EVAL1 • Under voltage lockout for each monitored supply voltage VDD ISL8723IRZ-T (Note) 8723IRZ ISL8724IRZ-T (Note) 8724IRZ • Glitch immunity DLY_ON_B 8724IRZ • Multiple sequencers can be easily daisy-chained to sequence an infinite number of independent voltages RESET# 8723IRZ • Adjustable voltage slew rate for each rail GATE_D ISL8723IRZ (Note) ISL8724IRZ (Note) • Supplies VDD +5.3V of charge pumped gate drive • Telecommunications Systems Ordering Information PART NUMBER • Operates from 2.5V to 5V supply voltage CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL8723, ISL8724 AIN AOUT BIN BOUT CIN COUT DIN VDD ENABLE AIN BIN CIN DLY_OFF_D DLY_OFF_C DLY_ON_C DLY_ON_B DLY_OFF_A DLY_ON_A DLY_OFF_B RESET# DLY_ON_D UVLO_A UVLO_B UVLO_C UVLO_D SYSRST# GROUND DIN GATE A GATE B GATE C GATE D DOUT FIGURE 1. TYPICAL ISL8723 APPLICATION USAGE Pin Descriptions PIN # PIN NAME 23 VDD Chip Bias Bias IC from nominal 2.5V to 5V 10 GND Bias Return IC ground 1 ENABLE/ ENABLE# Input to start on/off sequencing. Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is disabled for 10ms after UVLO is satisfied. ISL8723 has ENABLE. ISL8724 has ENABLE#. 24 RESET# RESET# Output RESET# provides a high signal ~160ms after all GATEs are fully enhanced. This delay is for stabilization of output voltages. RESET# will assert low upon any UVLO not being satisfied or ENABLE/ENABLE# being deasserted. The RESET# output is an open drain N-channel FET and is guaranteed to be in the correct state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X. 20 UVLO_A 12 UVLO_B Under Voltage Lock Out/Monitoring Input These inputs provide for a programmable UV lockout referenced to an internal 0.631V reference and are filtered to ignore short (<7µs) transients below programmed UVLO level. 17 UVLO_C 14 UVLO_D 21 DLY_ON_A 8 DLY_ON_B Gate On Delay Timer Output Allows for programming the delay and sequence for VOUT turn-on using a capacitor to ground. Each cap is charged with 1µA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current source providing delayed enhancement of the associated FETs GATE to turn-on. 16 DLY_ON_C 15 DLY_ON_D 18 13 DLY_OFF_A Gate Off Delay Timer Output DLY_OFF_B Allows for programming the delay and sequence for VOUT turn-off through ENABLE/ENABLE# via a capacitor to ground. Each cap is charged with a 1µA internal current source to an internal reference voltage causing the corresponding gate to be pulled down thus turning-off the FET. 3 DLY_OFF_C 4 DLY_OFF_D 2 GATE_A 5 GATE_B 6 GATE_C 7 GATE_D FUNCTION FET Gate Drive Output 2 DESCRIPTION Drives the external FETs with a 10µA current source to soft start ramp into the load. During sequence off, 10µA is sunk from this pin to control the FET turn-off. During a turn-off due to a fault, the gate will sink ~75mA to ensure a rapid turn-off. FN6413.0 December 21, 2006 ISL8723, ISL8724 Pin Descriptions PIN # PIN NAME 22 SYSRST# (Continued) FUNCTION System Reset I/O DESCRIPTION As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low. This pin can also be used to initiate the programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from input signal on this pin being driven high to first GATE. As an output when there is a UV condition this pin pulls low. If common to other SYSRST# pins in a multiple IC configuration it will cause immediate and unconditional latch-off of all other GATEs on all other ISL872x sequencers. This pin is released to go high once all UVLO and enable conditions are satisfied and is pulled low concurrent with the last GATE being turned off after EN disabled. 9,11, 19 No Connect No Connect 3 No Connect FN6413.0 December 21, 2006 ISL8723, ISL8724 Absolute Maximum Ratings Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V UVLO, ENABLE, ENABLE#, SYSRST# . . . . . . -0.3V to VDD +0.3V RESET#, DLY_ON, DLYOFF . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) 4 x 4 QFN Package . . . . . . . . . . . . . . . 48 9 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +125°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Operating Conditions VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +2.5V to +5.0V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 3. All voltages are relative to GND, unless otherwise specified. Electrical Specifications VDD = 3.3V to +5V, TA = TJ = -40°C to +85°C, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 619 631 647 mV UVLO Undervoltage Lockout Falling Threshold VUVLOvth Undervoltage Lockout Falling Threshold VUVLOvth 604 631 656 mV Undervoltage Lockout Hysteresis VUVLOhys - 9 - mV Undervoltage Lockout Threshold Range RUVLOvth Max VUVLOvth- Min VUVLOvth - 6 18 mV Undervoltage Lockout Delay TUVLOdel ENABLE satisfied - 10 - ms VDD, UVLO, ENABLE glitch filter - 7 - μs 0.9 1 1.115 μA - 0.01 0.05 μA 1.21 1.273 1.32 V - 1.28 1.35 V - 0.5 VDD - V Transient Filter Duration tFIL TA = TJ = +25°C DELAY ON/OFF Delay Charging Current DLY_ichg Delay Charging Current Range DLY_ichg_r Delay Threshold Voltage VDLY = 0V DLY_ichg(max) - DLY_ichg(min) DLY_Vth ENABLE/ENABLE#, RESET# AND SYSRST# I/O ENABLE Threshold VENh ENABLE# Threshold VENh Measured at VDD = 5V ENABLE/ENABLE# Hysteresis VENh -VENl Measured at VDD = 5V - 0.1 0.2 V ENABLE/ENABLE# Lockout Delay TdelEN_LO UVLO satisfied, EN to DLY_ON - 10 - ms ENABLE/ENABLE# Input Capacitance Cin_en - 5 - pF RESET# Pull-up Voltage Vpu_rst - VDD - V RESET# Pull-Down Current IRSTpd5 VDD = 5V, RST = 0.1V - 13 - mA RESET# Delay after GATE High TRSTdel GATE = VDD+5V - 160 - ms Measured at VDD = 5V, 1mA sourcing current - - 0.1 V RESET# Output Low VRSTl RESET Output Capacitance Cout_rst - 10 - pF SYSRST# Pull-up Voltage Vpu_srst - VDD-0.5V - V SYSRST# Pull-up Current Ipu_srst VDD = 3.3V, SYSRST# = 0.5V - 12 - μA VDD = 5V - 2.7 - μA VDD = 5V, IOUT = 100μA - 0.1 V SYSRST# Pull Down Current Ipu_5 SYSRST# Low Output Voltage Vol_srst 4 FN6413.0 December 21, 2006 ISL8723, ISL8724 Electrical Specifications VDD = 3.3V to +5V, TA = TJ = -40°C to +85°C, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL SYSRST# Output Capacitance TEST CONDITIONS Cout_srst MIN TYP MAX UNIT - 10 - pF SYSRST# Low to GATE Turn-off TdelSYS_G_1 GATE = 80% of VDD+5V - 40 - ns SYSRST# High to GATE Turn-on TdelSYS_G_2 GATE = 50% of VDD+5V - 0.4 - ms 8.3 10.2 12.5 μA -12.5 -10.2 -8.3 μA GATE GATE Turn-On Current IGATEon GATE Turn-Off Current IGATEoff_l GATE = 0V GATE = VDD, Disabled IGATE_range Within IC IGATE max-min - 0.6 3 μA GATE Pull-Down High Current IGATEoff_h GATE = VDD, UVLO = 0V - 75 - mA GATE High Voltage VGATEh5 VDD = 5V VDD+5.3V VDD+5.6V - V GATE Low Voltage VGATEl Gate Low Voltage, VDD = 1V - 0.01 0.1 V IC Supply Current IVDD_5V VDD = 5V, Enabled and static - 0.27 0.31 mA ISL8723 Stand By IC Supply Current IVDD_sb VDD = 5V, ENABLE = 0V - 30 40 μA VDD rising - 2.2 2.41 V GATE Current Range BIAS VDD Power On Reset VDD_POR ISL8723, ISL8724 Descriptions and Operation The ISL8723 and ISL8724 sequencers are quad voltage sequencing controllers designed for use in multiple-voltage systems requiring power sequencing of various supply voltages. Individual voltage rails are gated on and off by external N-Channel MOSFETs, the gates of which are driven by an internal charge pump to ~VDD +5.6V (VQP) in a user programmed sequence. With the ISL8723 the ENABLE must be asserted high and all four voltages to be sequenced must be above their respective user programmed Under Voltage Lock Out (UVLO) levels before programmed output turn on sequencing can begin. Sequencing and delay determination is accomplished by the choice of external cap values on the DLY_ON and DLY_OFF pins. The SYSRST# goes high once all 4 UVLO inputs and ENABLE are satisfied. Once all 4 UVLO inputs and ENABLE are satisfied for 10ms, the four DLY_ON caps are simultaneously charged with 1μA current sources to the DLY_Vth level of 1.28V. As each DLY_ON pin reaches the DLY_Vth level its associated GATE will then turn-on with a 10μA source current to the VQP voltage of VDD+5.6V. Thus all four GATEs will sequentially turn on. Once at DLY_Vth the DLY_ON pins will discharge to be ready when next needed. After the entire turn on sequence has been completed and all GATEs have reached the charge pumped voltage (VQP), a 160ms delay is started to ensure stability after which the RESET# output will be released to go high. Subsequent to turn-on, if any input falls below its UVLO point for longer than the glitch filter period, TFIL (~7μs) this is considered a fault. RESET#, SYSRST# and all GATEs are simultaneously pulled low. In this mode the 5 GATEs are pulled low with ~75mA. Normal shutdown mode is entered when no UVLO is violated and the ENABLE is deasserted. When ENABLE is deasserted, RESET# is asserted and pulled low. Next, all four shutdown ramp caps on the DLY_OFF pins are charged with a 1μA source and when any ramp-cap reaches DLY_Vth, a latch is set and a 10μA current is sunk on the respective GATE pin to turn off its external MOSFET. When the falling GATE voltage is approximately 1.5V, the GATE is pulled down the rest of the way at a higher current level to ensure a hard turn-off. Each individual external FET is thus turned off removing the voltages from the load in the programmed sequence. The SYSRST# will pull low concurrent with the last GATE being pulled low. The ISL8723 and ISL8724 have the same functionality except for the complimentary ENABLE active polarity with the ISL8724 having an ENABLE# input. Additionally the ISL8723 also has a low power sleep state when disabled. Upon bias the SYSRST# and RESET# pins are held low before bias voltage = 1V. The SYSRST# has both an input and output function. As an output the SYSRST# pin is useful when implementing multiple sequencers in a design needing simultaneous shutdown as with a kill switch across all sequencers. Once any UVLO is unsatisfied for longer than TFIL the related SYSRST# will pull low and pull all other SYSRST# pins low that are on a common connection thus unconditionally shutting down all outputs across multiple sequencers. As an input, if it is pulled low all GATEs will be unconditionally shut off and RESET# pulled low, see Figure 17. This pin can also be used as a ‘no wait’ enabling input, if all inputs (ENABLE and UVLO) are satisfied it does not wait through FN6413.0 December 21, 2006 ISL8723, ISL8724 the ~10ms enable delay to initiate DLY_ON cap charging when released to go high. This feature can be used where 4 voltages can be monitored in addition to a on-off switch position or, in the case of the ISL8724 a present pin pull down. Restart of the turn on sequence is automatic once all requirements are met. This allows for no interaction between the sequencer and a controller IC if so desired. If no capacitors are connected between DLY_ON or DLY_OFF pins and ground then all such related GATEs start to turn on immediately after the 10ms (TUVLOdel) ENABLE stabilization time out has expired and the GATEs start to immediately turn off when ENABLE is deasserted. Table 1 illustrates the nominal time delay from the start of charging to the 1.27V reference for various capacitor values on the DLY_X pins. This table does not include the 10ms of enable lock out delay during a start up sequence but represents the time from the end of the enable lock out delay to the start of GATE transition. There is no enable lock out delay for a sequence off, so this table illustrates the delay to GATE transition from a disable signal. TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD DLY PIN CAPACITANCE TIME (ms) Open 0.02 100pF 0.135 1000pF 1.35 0.01μF 13.5 0.1μF 135 1μF 1350 NOTE: Nom. TDEL_SEQ = dly_cap (µF) X 1.35MΩ Figure 2 illustrates the turn-on and Figure 3 the nominal turnoff timing diagrams of the ISL8723 and ISL8724 product. Note the delay and flexible sequencing possibilities. Multiple series, parallel or adjustable capacitors can be used to easily fine tune timing between that offered by standard value capacitors. 6 FN6413.0 December 21, 2006 ISL8723, ISL8724 l VUVLOVth <tFIL UVLO_A VUVLOVth UVLO_B VUVLOVth UVLO_C VUVLOVth UVLO_D ENABLE# (ISL8724) TUVLOdel VEN ENABLE (ISL8723) DLY_Vth DLYON_B DLY_Vth DLYON_D DLY_Vth DLYON_A DLY_Vth DLYON_C VQPUMP VQPUMP VQPUMP GATE_B VQPUMP GATE_D VQPUMP-1V GATE_C TRSTdel GATE_A RESET# SYSRST# FIGURE 2. ISL8723, ISL8724 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM UVLO_X>VUVLOVth ENABLE(ISL8723) ENABLE# (ISL8724) VEN DLY_Vth DLYOFF_A DLY_Vth DLYOFF_B DLY_Vth DLYOFF_C DLY_Vth DLYOFF_D GATE_C GATE_D GATE_A GATE_B RESET# SYSRST# FIGURE 3. ISL8723, ISL8724 TURN-OFF TIMING DIAGRAM 7 FN6413.0 December 21, 2006 ISL8723, ISL8724 Typical Performance Curves 650 VDD = 5V 0.25 645 640 0.20 VDD = 3.3V UVLO (mV) BIAS CURRENT (mA) 0.30 0.15 0.10 ISL8723 DISABLED 635 630 625 620 0.05 615 0.00 -40 -20 0 25 45 75 85 100 610 -40 125 -20 0 25 TEMPERATURE (°C) FIGURE 4. BIAS CURRENT DLY_ON/OFF CURRENT (µA) DLY_OFF Vth DLY VTH (V) 1.28 1.27 1.26 DLY_ON Vth 1.25 1.24 -20 0 25 45 75 75 85 100 125 FIGURE 5. UVLO THRESHOLD VOLTAGE 1.29 1.23 -40 45 TEMPERATURE (°C) 85 100 125 1.020 1.000 DLY_ON 0.980 DLY_OFF 0.960 0.940 0.920 -40 -20 0 TEMPERATURE (°C) 25 45 75 85 100 125 100 125 TEMPERATURE (°C) FIGURE 6. DLY THRESHOLD VOLTAGE FIGURE 7. DLY CHARGE CURRENT 1.29 6.0 Q-PUMP VOLTAGE (V) DLY_OFF Vth DLY VTH (V) 1.28 1.27 1.26 DLY_ON Vth 1.25 1.24 1.23 -40 5.8 VDD = 5V 5.6 5.4 5.2 VDD = 2.5V 5.0 4.8 -20 0 25 45 75 85 TEMPERATURE (°C) FIGURE 8. BIAS POWER ON RESET 8 100 125 -40 -20 0 25 45 75 85 TEMPERATURE (°C) FIGURE 9. CHARGE PUMP VOLTAGE FN6413.0 December 21, 2006 ISL8723, ISL8724 Typical Performance Curves (Continued) FAULT GATE CURRENT (mA) 10.3 GATE CURRENT (µA) 10.2 10.1 I_GATE_ON 10.0 9.9 I_GATE_OFF 9.8 9.7 9.6 9.5 9.4 -40 -20 0 25 45 75 85 100 125 TEMPERATURE (°C) FIGURE 10. GATE TURN-OFF/ON (DIS)CHARGE CURRENT Using the ISL8723EVAL1 Platform The ISL8723EVAL1 platform allows evaluation of the ISL8723, easily providing access to the critical nodes, see Figure 21 for schematic and Figure 22 for a photograph of the evaluation platform. The board has a SMD layout with a ISL8723 illustrating the possible small implementation size for a typical four rail sequencing application. There are bias and function labeled test points to give access to the IC pins for evaluation. Remember that significant current or capacitive loading of particular I/O pins will affect functionality and performance. The default configuration of the ISL8723EVAL1 circuit was built around the following design assumptions: 1. Using the ISL8723IR 2. The four supplies being sequenced are 5V (IN_A), 3.3V (IN_B), 2.5V (IN_D) and 1.5V (IN_C), the UVLO levels are ~80% of nominal voltages. Resistors chosen such that the total resistance of each divider is ~ 10k using standard value resistors to approximate 80% of nominal voltage supply = 0.63V on UVLO input. 100 90 80 70 60 50 40 -40 -20 0 25 45 75 85 100 125 TEMPERATURE (°C) FIGURE 11. FAULT GATE TURN-OFF SINK CURRENT VOUT voltage for a single channel being turned on and off respectively. RESET# and SYSRST# functionality and relationships are shown in Figures 16 through 20. Figure 16 illustrates that with a rising VDD, EN tied to VDD, and all UVLO configured to be satisfied, both the RESET# and SYSRST# are held low before VDD = 1V. SYSRST# is released to go high once the last UVLO is satisfied and RESET# is released to go high at TRSTdel after the last GATE is high. Figure 17 shows GATE and RESET# response to SYSRST# being pulled low. Figure 18 shows EN high to SYSRST# delay with all UVLO inputs satisfied. Figure 19 shows RESET# and SYSRST# delay to EN pulled low. Figure 20 shows ~8µs of glitch filter duration, tFIL during which the RESET# and SYSRST# do not react. 3. The desired order turn-on sequence is 5V first, then 3.3V about 12ms later then the 2.5V supply about 19ms later and lastly the 1.5V supply about 40ms later. 4. The desired turn-off sequence is first the 2.5V, the 3.3V 12ms later, then the 1.5V supply about 36ms later and lastly the 5V supply about 72ms after that. 5. LED off indicates sequence has completed and RESET has released and pulled high. All scope shots are taken from ISL8723EVAL1 board. Figures 12 and 13 illustrate the desired turn-on and turn-off sequences respectively. The sequencing order and delay between voltages sequencing is set by external capacitance values so other than that illustrated can be accomplished. Figures 14 and 15 illustrate the timing relationships between the EN input, RESET#, DLY and GATE outputs and the 9 FN6413.0 December 21, 2006 ISL8723, ISL8724 Typical Performance Waveforms ENABLE ENABLE RESET# RESET# SYSRST# I/O = 5V/DIV SYSRST# I/O = 5V/DIV 5VOUT 5VOUT 3.3VOUT 3.3VOUT 2.5VOUT 1.5VOUT 1.5VOUT 2.5VOUT VOUT = 2V/DIV 40ms/DIV VOUT = 2V/DIV 20ms/DIV FIGURE 13. ISL8723 SEQUENCED TURN-OFF FIGURE 12. ISL8723 SEQUENCED TURN-ON EN 5V/DIV EN 5V/DIV GATE 2V/DIV TdelENLO DLY_Vth DLY_Vth DLY_ON 0.5V/DIV DLY_OFF 0.5V/DIV GATE 2V/DIV 3.3VO 2V/DIV 3.3VO 2V/DIV 4ms/DIV 10ms/DIV FIGURE 14. ISL8723 3.3V TURN-ON FIGURE 15. ISL8723 3.3V TURN-OFF GATE VDD SYSRST# SYSRST# RESET# RESET# FIGURE 16. SYSRST# and RESET# vs VDD (EN = VDD, 4 UVLO > UVLO Vth) 10 FIGURE 17. SYSRST# LOW to GATE and RESET# LOW FN6413.0 December 21, 2006 ISL8723, ISL8724 Typical Performance Waveforms (Continued) SYSRST# SYSRST# RESET# ENABLE FIGURE 18. 4 UVLOs VALID, ENABLE HIGH to SYSRST HIGH ENABLE FIGURE 19. ENABLE LOW to RESET# and SYSRST LOW UVLO RESET# SYSRST# FIGURE 20. UVLO INVALID to RESET# and SYSRST$# LOW 11 FN6413.0 December 21, 2006 ISL8723, ISL8724 +3.3V 1.5V +2.5V +5V C1 1 EN 23 VDD DLY_ON_B ENABLE DLY_ON_D R1 7.681K R4 4.99K R2 6.98K R6 8.45K 17 14 20 SYSRST R5 4.99K R3 3.01K UVLO_B DLY_OFF_C UVLO_C DLY_OFF_D UVLO_D DLY_OFF_B UVLO_A DLY_OFF_A GATE_A GATE_B GATE_D 9,11 19 GATE_C SYSRST 0.068μF 3 C6 4 13 0.047μF C8 18 0.01μF 0.022μF C5 C7 OPEN C9 2 5 6 FDS6990S 4 5 Q1A 3 7 7 8 FDS6990S 2 6 NC RESET 24 GND C3 0.01μF C4 0.1μF ISL8723IR 22 C2 OPEN U1 R11 1.47K 1 15 DLY_ON_C 16 21 DLY_ON_A 12 R12 2.26K 1μF 8 Q1B 1 D1 5 6 4 FDS6990S Q2A FDS6990S 3 R9 7 8 2 750 10 Q2B 1 R9 10 R10 10 R13 10 R14 10 FIGURE 21. ISL8723EVAL1 BOARD SCHEMATIC FIGURE 22. EVAL BOARD PHOTOGRAPH 12 FN6413.0 December 21, 2006 ISL8723, ISL8724 TABLE 2. ISL872XSEQEVAL1 BOARD COMPONENT LISTING COMPONENT DESIGNATOR U1 COMPONENT FUNCTION COMPONENT DESCRIPTION ISL8723, 4 Supply Sequencer Intersil, ISL8723IR 4 Supply Sequencer Voltage Rail Switches FDS6990S or equiv, Dual N-Channel MOSFET R6 5V to UVLO_A Resistor for Divider String 8.45kΩ 1%, 0402 R11 UVLO_A to GND Resistor for Divider String 1.47kΩ 1%, 0402 R1 3.3V to UVLO_B Resistor for Divider String 7.68kΩ 1%, 0402 R12 UVLO_B to GND Resistor for Divider String 2.26kΩ 1%, 0402 R2 2.5V to UVLO_D Resistor for Divider String 6.98kΩ 1%, 0402 R3 UVLO_D to GND Resistor for Divider String 3.01kΩ 1%, 0402 R4 1.5V to UVLO_C Resistor for Divider String 4.99kΩ 1%, 0402 R5 UVLO_D to GND Resistor for Divider String 4.99kΩ 1%, 0402 R9 RESET LED Current Limiting Resistor 750Ω 10%, 0805 C5 5V turn-on Delay Cap. A (~10ms) DNP, 0402 C9 5V turn-off Delay Cap. A (~140ms) 0.1μF 10%, 6.3V, 0402 C2 3.3V turn-on Delay Cap.B (~13ms) 0.01μF 10%, 6.3V, 0402 C8 3.3V turn-off Delay Cap. B (~13ms) 0.01μF 10%, 6.3V, 0402 C3 2.5V turn-on Delay Cap.D (~25ms) 0.022μF 10%, 6.3V, 0402 C7 2.5V turn-off Delay Cap. D (0ms) DNP, 0402 C4 1.5V turn-on Delay Cap. C (~100ms) 0.068μF 10%, 6.3V, 0402 C6 1.5V turn-off Delay Cap. C (~60ms) 0.047μF 10%, 6.3V, 0402 C1 Decoupling Capacitor 1μF, 0805 D1 RESET Indicating LED 0805, SMD LEDs Red R9 5V Load Resistor 10Ω 20%, 3W Carbon R10 3.3V Load Resistor 10Ω 20%, 3W Carbon R13 2.5V Load Resistor 10Ω 20%, 3W Carbon R14 1.5V Load Resistor 10Ω 20%, 3W Carbon Q1, Q2 Test Points Labeled as to Function 13 FN6413.0 December 21, 2006 ISL8723, ISL8724 Application Implementations HIGH = POWER GOOD Multiple Sequencer Implementations In order to control the sequencing of more than 4 voltages in applications where the integrity of these critical voltages must be assured prior to sequencing, several of the ISL8723 or ISL8724 devices can configured together to accomplish this. Figure 23 shows a typical multi sequencer implementation, note the common SYSRST# signal that asserts once all monitored voltages are valid allowing the sequence to initiate. The sequencing is straight forward across multiple sequencers as all DLY_ON capacitors will simultaneously start charging once all monitored voltages area valid and ~10ms after the common ENABLE input signal is delivered. This allows the choice of capacitors to be related to each other no different than using a single sequencer. When the common enabling signal is deasserted this configuration will then execute the turn-off sequence across all sequencers as programmed by the DLY_OFF capacitor values. With all the SYSRST# pins bused together once the on sequence is complete simultaneous shutdown upon any UVLO input failure is assured as the SYSRST# output will pull low, simultaneously turning off all GATE outputs. SYSRST# ISL872X UVLO ENABLE ENABLE# G A T E RESET# SYSRST# ISL872X POWER SUPPLY UVLO ENABLE# G A T E RESET# HIGH = SEQUENCE COMPLETED FIGURE 23. MULTIPLE ISL872X CONFIGURATION All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN6413.0 December 21, 2006 ISL8723, ISL8724 Package Outline Drawing L24.4x4 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 4X 2.5 4.00 A 20X 0.50 B PIN 1 INDEX AREA PIN #1 CORNER (C 0 . 25) 24 19 1 4.00 18 2 . 10 ± 0 . 15 13 0.15 (4X) 12 7 0.10 M C A B 0 . 07 24X 0 . 23 +- 0 . 05 4 24X 0 . 4 ± 0 . 1 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C C 0 . 90 ± 0 . 1 BASE PLANE ( 3 . 8 TYP ) SEATING PLANE 0.08 C SIDE VIEW ( 2 . 10 ) ( 20X 0 . 5 ) C 0 . 2 REF 5 ( 24X 0 . 25 ) 0 . 00 MIN. 0 . 05 MAX. ( 24X 0 . 6 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 15 FN6413.0 December 21, 2006